Figure 1— Experimental setup of the Software Defined Radio. Software on the host notebook computer generates the code required to program the DSP and FPGA hardware the Lyr Signal Processing SignalMaster development board on its edge in the background. After the code is downloaded to the hardware, the notebook also serves as the radio’s user interface. The receiver RF pre-amp, transmitter power-amp, anti alias filter, and T/R switching are on the copper clad board behind and to the left of the microphone.

Introduction In the January 1948 issue of QST, SSB was heralded as being “… the most significant development that has ever occurred in amateur radiotelephony... ”.

We are now on the brink of another step in technology that will eventually change how HF and all high performance radios will be constructed. This technology will ultimately lead to lower cost, improved performance and vastly increased flexibility.

One of the most remarkable components to evolve over the past decade is the Field Programmable Gate Array or FPGA. The FPGA is uniquely suited for high speed digital signal processing (RF data rates) due to its scalable and parallel hardware resources. As mind bending as the FPGA is, it is made even more remarkable by the latest design tools that allows a high fidelity simulation of the system and then automatically generates the VHDL code to program the device. An engineer’s dream, come true!

The same situation holds for the Digital Signal Processing chips. Tools exist that do both system simulation and automatic code generation. And as if all that was not enough, the design environment turns into a graphical user interface to control, monitor, and adjust parameters on your creation while it is running! Yes, it seems too good to be true, but it is real.

This note describes how these tools and components are used to create an HF SSB radio.

Some Definitions A Software Defined Radio is a radio that is made from general purpose reconfigurable / programmable components. It is the programming of these components that define its operational characteristics. For instance bandwidth and modulation (ssb, cw, am, fsk, psk, qpsk etc) are completely determined by how the reconfigurable parts are programmed, not by hardware filters, mixers, amplifiers, and other “traditional” components. DSP (chip) is a computing device that is optimized for the processing of data streams (signals). The holy grail of signal processing is the “multiply-add” operation since virtually all algorithms need myriad of these computations. In conjunction with a fast hardware multiplier and accumulator, the DSP memory addressing is computed in the same instruction cycle using memory address generation hardware such that two values (coefficient and data) can be fetched from fast memory to feed the multiplier. This allows

the multiply-add operation to be done in one machine cycle. Although it is true that a general purpose processor (e.g. Intel Pentium) can in fact computationally outpace the DSP, the power consumption but its cost is commensurate with this performance. The FPGA is a re-programmable logic device that can contain the equivalent of millions of gates. On board these remarkable devices reside RAM, 18x18 parallel multipliers, registers, look up tables, and the equivalent of general purpose logic. The key advantage the FPGA enjoys over the DSP is its ability to utilize the hardware in a parallel fashion. In other words, one is not constrained to process data streams through one (or at most 4) arithmetic elements, but it literally may have thousands of elements to perform the computations in parallel. This allows the FPGA to process data streams that are running in the 100s of MHz. Until recently, the downside of the FPGA was its difficulty to write the required code to program it. It required knowledge of a Hardware Descriptor Language such as Verilog or VHDL. This has now all changed with the introduction and evolution of the Xilinx System Generator for DSPTM.

By Dick Benson, W1QG (v0.1)

An HF SSB Software Defined Radio

Figure 2— Block Diagram. The radio architecture can be described with only 12 major components. The color code is as follows:

black : continuous time signals red : the fastest sampling rate, 64 MSPS green : I/Q data at 64 MSPS/4096 rate blue : audio data at 64 MSPS/8192 (7.8125 kHz)

Radio Architecture Figure 2 shows the utter simplicity of this radio! True, millions of transistors are required, but thanks to modern semiconductor manufacturing techniques, the cost per transistor is less than the cost of a 1 turn wire loop serving as an inductor! Who would have thought that to ever be possible? As can be seen, the radio uses multiple sampling rates for the signal processing and the high speed work is done in the FPGA while the audio bandwidth work is done in the DSP. A rather perfect division of labor, with each component doing what makes the most sense.

Weaver’s Third Method Prior to 1956 there were two primary methods known for generating SSB signals: phasing and filtering. Each of these methods had its pro’s and con’s. The phasing method required a circuit that generated a 90 degree phase shift across the audio frequency range (300-3000 Hz). Deviations from 90 degrees led to a reduction in the unwanted sideband suppression. The filter method eventually won out with both crystal and mechanical filters being used. In 1956, Donald Weaver came up with a third method that apparently had been overlooked. It required filters, and phase shifts, but the phase shifts were fixed with respect to frequency and the filters were low-pass, not band-pass. However, the

technology of the time was not really up to the task, and the filtering approach worked well, so the new “Third Method” was not adopted. Implementing Weaver’s technique in DSP hardware is quite easy! The main issues of dc offset, and filter gain-phase match that prevented the idea from being adopted in 1956, simply do not exist. Figure 3 shows a block diagram, created with the Mathworks Simulink environment, of a simple SSB generator using Weaver’s scheme. To provide a recognizable shape to the spectrum, a weighted sum of sine waves is used as the audio input. The first translation and filtering operation centers the desired sideband around DC and removes the other sideband. Then it is a simple matter to up convert this complex (I & Q) signal to the desired RF frequency. The output of the final two mixers is either summed or differenced to get the upper or lower sideband. The spectra shown in Figure 3 tell the story.

Figure 4— Filter Frequency Response

Figure 3— Weaver’s Third Method. A simple SSB generator made from Simulink blocks is useful to understand the spectral shifting, filtering, and up translation to RF.

Filter Design The previous simplified example shifted the upper sideband to approximately 25 kHz. The actual radio will need to go far higher, almost 30 MHz. To accomplish this, multi-stage, multi-rate filtering is required. The Mathworks has a superior set of filter design tools that make this design job quite easy. To cover the 30 MHz HF spectrum, a sampling clock of greater than 2x30 MHz is needed. The on-board 64 MHz clock satisfies this requirement. The desired audio rate is around 8000 Hz, and 64e6/8192 = 7812.5 Hz is a good fit here. Focusing on the receiver for a moment, the first filter will be a Cascaded Integrator Comb (CIC) filter since it maps very well to FPGA hardware. The remaining filters will be FIR decimators or interpolators for the transmit chain. The filter p-rocessing is as follows: CIC (D=64), FIR_1 (D=8), FIR_2 (D=8), FIR_3 (D=2) for an overall sample rate reduction of 64*8*8*2=8192. Figure 4 shows the overall frequency response of the multi stage filter. The same filter coefficients are used for transmit as well. The last filter (D=2) determines the ultimate frequency response characteristics. It therefore borders on being trivial to change

the filter characteristics since they are all defined by software.

-1.5 -1 -0.5 0 0.5 1 1.5 2

x 104

-100

-90

-80

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-60

-50

-40

-30

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-10

0

Hertz

Ove

rall

Filt

er R

espo

nse

in d

B

Figure 5— Local Oscillators

Figure 4— Hardware Independent Model (Top Level)

Figure 6— SSB Modulator

Figure 7— SSB Demodulator

Evolving the Design The basics are now laid out, and more detail now needs to be added. The first step in this process is to create a hardware independent model. This is easily done by using Simulink’s DSP Block Library. Figure 4 shows the general signal flow in the radio. The local oscillators are shared by both receive and transmit processing chains. The receiver consists of a digital down converter followed by a final filter-demodulator stage. The transmitter is simply the receiver blocks turned around with interpolating rather than decimating filters!

Once satisfactory simulation results have been obtained indicating the general signal flow and filtering are correct, it is time to split the model between the FPGA and the DSP. For this design, it is quite straightforward to partition the functions. The light green blocks will be implemented in the DSP chip while the light red blocks will be implemented in the Xilinx FPGA. And yes, this is still the Weaver scheme, but using modern terminology (digital down / up converters).

Simulink HF SSB Transceiver

Red = 64MHzCyan = 64MHz/4096Dark Green = 64MHz/8192

Tx_out

B-FFT

Tx RF Spectrum

lo_sin

lo_cos

IQ_in

RF_out

Tx Digital UpConverter

0

Sideband Select

lsb_sel

bfo_sin

bfo_cos

Audio_in

IQ_out

SSB Modulator

IQ_in

bfo_sin

bfo_cos

lsb_sel

Audio_out

SSB Demodulator

Rx_out

Fo

Rx/Tx Frequency

RF_in

lo_sin

lo_cos

IQ_out

Rx Digital DownConverter

RF input

B-FFT

RF Input Spectrum

Color Track

Fin

LSB_sel

hf_lo_sin

hf_lo_cos

bfo_sin

bfo_cosLocal Oscillators

-K-

Gain

28.4

Freq (MHz)

B-FFT

AF Spectrum

AF Input

double (2) double

double

double

double

double

double

double (c)

double

doubledouble

double (c)

double (2) double

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4bfo_cos

3bfo_sin

2hf_lo_cos

1hf_lo_sin

-K-

m1

Switch

Vinsin

cos

LO_dds

Vinsin

cos

BFO_dds

Fbfo

BFO Freq

2LSB_sel

1Fin

double

double

double

double

double

double

double

double

double

double

SSB DEMOD

1Audio_out

SwitchMix 2

Mix 1

-K-

Gain1

x[2n]

FIRDecimation2

Re(u)Im(u)

Complex toReal-Imag

4lsb_sel

3bfo_cos

2bfo_sin

1IQ_in

double (c)

double

double

double

double

double

double

double

double

double

double

double (c)

SSB Modulator

1IQ_out

-K-

m1

Switch1

ReIm

Real-Imag toComplex1

Product3

Productx[n/2]

FIRInterpolation by 2

4Audio_in

3bfo_cos

2bfo_sin

1lsb_sel

double

double

double

double (c)double (c)double

double double

double

double

The FPGA Design The Xilinx System Generator for DSP is a state-of-the-art tool that provides design entry, data path definition, bit / cycle true simulations, test bench generation, hardware co-simulation, VHDL code generation, and more! The key to the tool is that the Xilinx system Generator Bock Library maps to Xilinx LogiCores which are highly optimized implementations of typical DSP functions (filters, direct digital synthesizer, FFT, etc.). One merely picks blocks from the library, defines the parameters (e.g. word size,

binary point position), and hooks them together just like standard Simulink blocks. Gateways are used to go between the standard Simulink double precision and the fixed point representation used by the Xilinx blocks. Referring to figure 10, there are blocks that are specific to the Lyr SignalMaster hardware and these are marked with an “LSP”. The ADC (red) represents the 64 MSPS converter, while the DAC (red) is the 64 MSPS DAC. The gate_1 gateway is a 32 bit register that the DSP can write to change the frequency of the Direct Digital Synthesizer in the RF Local Oscillator block. The downconverted IQ stream from the Rx_Mix_Filters is fed to a 32 bit gateway that interfaces to

0.5-29 MHz, Fs=64MSPS

SSB Rx/Tx Part I: FPGA Frequency Translator

D1 Q1

gate_1

In1RX_IQ

demux IQ

DAC

dacsim

fpt dbl

center freq

RF_DAC

LO_sin

LO_cos

IQin

TX_Filters_Mix

IQout

LO_sin

LO_cos

RF_adc

RX_Mix_Filters

B-FFT

RX Output

RF input

RF in/out

Freq_in

LO_sin

LO_cos

RF Local Oscillator

B-FFT

Output Spectrum

Color TrackLSP FPGAGenerator

B-FFT

Input Spectrum

IQ_muxd

IQ for Xmit

D1 Q1

IQ To DSP

D1 Q1

IQ From DSP

-K-

Gain1

6.4e+007

Fs_ADC&DAC

28.399999991059

Frequency (MHz)

-C-

Frequency

I : O

Freq

xldsamp 2z-1

Down Sample

D1 Q1

DAC1

Codec Sync

D1 Q1

ADC

SystemGenerator

doubledouble

Fix_14_13

Fix_14_13

Fix_14_13

double

doublexmit_rf_out

double

double double

double Fix_32_0

double double (c)

Fix_32_32

UFix_32_0

UFix_12_0

UFix_32_0

double

Figure 10— FPGA top Level

Digital Down Converter

1IQ_out

ReImiq2c

Product

x[8n]

FIR_2Decimation by 8

x[8n]

FIR_1Decimation by 1

CIC Decimator D=643

lo_cos

2lo_sin

1RF_in

double (c)double (c)

double

double

double

double (c) double (c) double (c)

Digital Up Converter

1RF_out

Mixer 2

Mixer 1x[n/8]

FIRInterpolation1

x[n/8]

FIRInterpolation

Re(u)Im(u)

Complex toReal-Imag

CIC Interpolator3IQ_in

2lo_cos

1lo_sin

double

double

double (c) double (c) double (c) double (c) double

double

double

double

double

Figure 8— Rx Digital Down Converter

Figure 9— Tx Digital Up Converter

Figure-12 Rx Down-Sampling Filters

Figure-14 Xilinx ISE 5.2i

Figure-11 DDS HF Local Oscillator

Figure-13 Tx Up-Sampling Filters

Figure-15 Xilinx Floor Planner

the TI DSP. On the transmit side, another gateway (IQ from DSP) takes data form the TI DSP and drives the IQ input of the TX_Filters_Mix block. This diagram is the top level and further detail is contained within each block as shown in Figures 11-13 to the right. Once the data paths and processing is defined, simulation reveals if the design meets the objectives of dynamic range, and spurious responses introduced by the fixed point implementation. If not, chances are that more bits need to be used in the filter coefficients and/or data paths. Once the objectives are met, a click of the mouse generates the circa 200 files of VHDL required to implement the design. It is then a matter of using the normal Xilinx tool flow (Figure 14) of synthesis, place and rout, and finally to bit-stream generation to program the FPPGA. This process requires virtually no user intervention and a bit-stream can be accomplished with a single mouse click.

One of the more interesting reports that can be generated is a “floor-plan” of the FPGA design. This tool (Figure 15) provides a graphical representation of the FPGA resources used by each major component (DDS, FIR filter etc). As can be seen, virtually all (95%) of the FPGA fabric is used by the digital up/down converter. The design did not initially fit in the xc2v1000 part. Bits were trimmed from the transmit data paths and rounding / saturation were abandoned. The simulation results indicated that this would not cause any severe problems if the proper audio signal conditioning were done in the DSP chip portion of the design. The ability to easily make these tradeoffs is a key attribute of the design flow. Much more can be done to shrink the design allowing the use of a lower cost FPGA, but for this example, there is little point.

2

hf_lo_cos

1

hf_lo_sin

xlusamp 8192

Up Sample2

xlcastforce

Reinterpret

z-1

Delay2

z-1

Delay1

xldds

sin

cos

data

we

DDS

k =1

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1

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Bool

UFix_32_32Fix_32_32

Fix_14_13

Fix_14_13

Fix_14_13

Fix_14_13UFix_32_32

1

IQ_out

I

Q

d8_2

I

Q

d64_CICxlmult

z-3

a

b(ab)

M2

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b(ab)

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Q

Out

IQ muxto make 32b stream

I : O

IQ data rate

I: O

Freq2

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Freq1

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I

Q

d8_1

3

RX_ADC

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LO_cos

1

LO_sin

Fix_16_15 Fix_16_14

Fix_16_14Fix_16_15

double

double

double

Fix_16_15

Fix_16_15

Fix_14_13

Fix_14_13

Fix_14_13

Fix_16_15

Fix_16_15

UFix_32_0

1

RF_out

I

Q

i8_2

I

Q

i64_CIC

xladdsubz-1

a+ba

b

TX sum

xlmultz-3

a

b(ab)

M2

xlmultz-3

a

b(ab)

M1

I n

I

Q

IQ demuxfor 12.11 fmt

In1 Out1

Fix2UFix

xlconvertz-1

cast

Convert2

I

Q

i8_1

3

Tx_IQ

2

LO_sin

1

LO_cos

Fix_12_11

Fix_12_11

Fix_16_15

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Fix_12_11

Fix_12_11

Fix_16_15Fix_12_11

Fix_12_11

Fix_14_13

Fix_14_13

Fix_12_11Fix_12_11

Fix_12_11

Fix_32_0UFix_12_0

.

Figure-17 Audio Processing

Figure-18 Reverberation Module

Figure-19 Tx SSB top Level Modulator

The DSP Design Figure 16 shows the top level of the radio partition which is implemented with the TI C6711 DSP chip on the Lyr SignalMaster development hardware. Like the preceding models, the model is hierarchical. The Audio Processing block is shown in Figure 17. The left most manual switch selects either the audio ADC in the Mic. Input block, or, two audio sine generators that are summed together to make a built in 2-tone generator. Reverberation is not used with the two tone test, but if the ADC is selected, the output of the Reverberation module is routed to the block output. The details of the Reverberation module are shown in Figure 18. For processor efficiency, most of the signal processing is done with “frames” of data. On the block diagram, frame based signals show as a wide line. However, feedback systems such as the reverb, need to be implemented on a sample by sample basis, therefore there is an un-buffer and buffer combination to go to sample based and then back to frame based processing.

The transmit chain modulator is shown in Figure 19. The main subsystem is only enabled during transmit to lower the DSP processing load. Figure 20 has the modulator and a compressor which rather than being in the audio chain, is applied to the IQ data stream from the modulator block output.

FPGA Freq Control

Interface to - from FPGA Digital Frequency Translator

SSB Rx/Tx Part II: TI DSP Filters + Modulator / Demodulator

Tx==1

Audio_in

lsb_sel

Tx

IQ_to_FPGA

BFO_out

cmprs

Tx SSB Modulator

Test / Rx Out

SMC6xxAsynchonous

Interface

SMC6xx AsynchronousBus Interface

IQ_from_FPGABFO_inlsb_selTxcmprs

Audio_out

Smeter

Rx SSB Demodulator

Profiler

Color TrackLevel

LSB==1

LED

7.274Freq

Fine F

lsb/usb

Freq1

Freq2

Out1

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0

DSPConstant1

1

DSPConstant

Coarse F

CS4228_cntl

CS4228Playback

CMD FileGenerator

Audio Out

Audio Processing

Time

Audio Out

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30

AF Gain

26.38

% CPU Loading

single [64x1]

[64x1]

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single [64x1]

double

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Figure-16 DSP Partition in TI C6711

3

cmprs

2

BFO_out

1

IQ_to_FPGA

IQin Out1

mpx IQ to a 32bit wordSwitch4

Switch2

Repeat2x

Repeat

Audio

BFO

lsb

Out1

Out2

Modulator + Compressor

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Audio_in

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double

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1

Audio Out

In1 Out1

reverb2else { }Out1

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Switch

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if { }out

Mic Input

Merge

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u1if(u1 ~=0)

else

IfAudio / Test1

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single [64x1]single [64x1]single single [64x1]single

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Figure-20 Tx SSB Modulator, Filter and Compressor

Figure-21 Tx IQ Compressor

Figure-22 Rx SSB Demodulator

Figure-22 Rx AGC

Figure-23 Rx SSB Demodulator

Figure-24 FPGA DDS Frequency Control

2

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Im

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1

IQin

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single

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Referring to Figure 19, the output of the Compressor feeds a switch that only passes the IQ stream on to the subsequent blocks during transmit. The final block in figure 19 converts the complex single precision IQ data stream into a 32 bit fixed point word (16 bits for I and 16 bits for Q) to be passed to the FPGA by the Asynchronous Interface block in Figure 16.

2

Smeter

1

Audio_out

Switch

IQin

lsb_sel

BFOin

IpQAudio

SSB demod

NOT

LogicalOperator

x[2n]

FIRDecimation

In

Out

Smeter

RF AGC

AGC

AGC

ADC Gain and more

In1Out1

32bit IQ demux

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cmprs

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T x

3

lsb_sel

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1

IQ_from_FPGA

int32 [64x1] single (c) [64x1]single (c) [64x1]

single [64x1]

single (c) [64x1]

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single

double

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double

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doubledouble

The first block in Figure 22 converts the 32 bit fixed point combined IQ signal from the FPGA to a complex (IQ) single precision float which drives the downsample-by-2 FIR filter. This filter determines the information bandwidth of the receiver. Its up-sample-by-2 counterpart in the transmitter does the same thing. To switch between various information filters, one need only to create them using the DSP filter design tools, and place the filters in “enabled subsystems” in a manner similar to the mechanism used to select between the mic and the two-tone source.

The FIR filter IQ output drives the AGC subsystem which is shown in Figure 23. The AGC is similar to the transmit compressor in that it is a feed forward scheme rather than a feedback scheme. Feed forward is difficult in analog hardware, but easy with DSP. Note that one of the paths (RF AGC) also drives a programmable gain amplifier before the

64 MSPS in the Lyr SignalMasterhardware. Also, some numeric displays are shown measuring signal levels.

The normalized IQ level from the AGC subsystem is then fed to the SSB demodulator block along with the BFO signal from the (complex) audio oscillator that was in the Tx SSB Modulator block (Figure 19).

1

IpQAudio

-1

m1

SwitchProduct1

Product

Re(u)

Im(u)

Complex toReal-Imag1

Re(u)Im(u)

Complex toReal-Imag

3

BFOin

2

lsb_sel

1

IQin

single [64x1]

single [64x1]

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double

single [64x1]

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single (c) [64x1]

The output of the demodulator (Figure 23) forms the Audio Out signal in Figure 19.

To control tuning frequency, transmit/receive, and sideband selection, a simple user interface was made (Figure 16) from switches and sliders. The light bulb icon turns on some LEDs on the SignalMaster during transmit. A wire run from the LED driver is the electrical Transmit / Receive signal for the external (analog) hardware.

1

Out1

-1

m1

Zero-OrderHold

Switch1

1e6 -K-

-K-

SMC6xxCustomRegister

FPGA DDS Freq

64

Downsample

Fbfo

DSPConstant1

3

Freq2

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lsb/usb

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double

double double

double

double double

The processing of these control signals is shown in Figure 24. The 32 bit word to set the FPGA Direct Digital Synthesizer frequency is computed in this block. Notice that the DDS frequency is offset from the tuned frequency by an amount that is equal to the BFO frequency, and, this frequency shift is up or down depending on the sideband select mode. This places the tuned frequency to the point where there would be a carrier in a non-suppressed carrier system.

3

RF AGC

2

Smeter

1

Out

Unbuffer

Saturation

0

RFA1

2129

RFA

2129.4

RF gain

Product3

max

MinMax

log10

MathFunction

z-192

Integer Delay1

z-1

Integer Delay

1

Gain5

300

Gain4

3

Gain3

.9995

Gain2

20/6

Gain1

64

Downsample

DF FIR

Digital Filter

Dead Zone

(double)

Data Type Conversion

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Constant2

.5

Constant

Buffer

|u|

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Enable

1

Insingle single

single

single

single (c) [64x1]

single

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Figure-25 Real time Scope on Audio Signal

Automatic Code Generation and Control Now the good part! The real-time code to implement the previous block diagrams, download it, and run it, is a mouse click away! A key feature of the Simulink environment is an (optional) fully integrated code generation engine option called the Real Time Workshop. The process that generates the C code can be modified to support a variety of target hardware. A pre-packaged target exists for the Lyr SignalMaster making it remarkably easy to get up and running. Not a single line of code was manually written.

If that were not impressive enough, the block diagram now becomes the user interface to control the radio! The switches and sliders on the block diagram change parameters (T/R, frequency, USB/LSB) on the fly while the code is executing in the hardware. Plus, the displays (e.g. numerical in Figure 22) update as well. You can even drop in “scopes” as in the top level of Figure 16, and these update while the code is running as well! Frankly, it has to be seen to be appreciated.

Beyond this, parameters ( e.g.constants) can also be changed while the code is running to adjust reverb level, AGC time constant, signal limiting etc.

Ok, How Does it Work ? Reports are universally positive with regard to the signal quality of the radio. In spite of the fact that the receiver has no tuned pre-selector, it overloads only on the strongest local signals. For certain, quantitative measurements need to be made, but there is no question that the radio works well under real world conditions.

Further Work This design is a Work In Progress. Now that the basic scheme is functioning, additions will be fairly easy. Notice from Figure 16 that only 26% of the processor horsepower is being used for the current code. This implies that 3x more processing is available. On the downside, there has been a pesky intermittent failure which has been found to be related to temperature. New hardware has just arrived and will hopefully cure this ill. Stay tuned, Dick, w1qg September 21, 2003

Useful Links

http://mathworks.com

http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=dsp_software_tools

http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=system_generator

http://www.signal-lsp.com/

http://home.comcast.net/~w1qg/homebrew.pdf