A “BTeV” Hybrid Pixel Telescope for MTest David Christian May 4, 2007.
BTeV Pixel Detector Optical link receiver chip Data In and Out project.
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Transcript of BTeV Pixel Detector Optical link receiver chip Data In and Out project.
![Page 1: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/1.jpg)
BTeV Pixel DetectorBTeV Pixel Detector
Optical link receiver chip
Data In and Out project
![Page 2: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/2.jpg)
Data In Out
• Is the interface between the Pixel Detector and the pair DAQ system/Trigger processor.
• Ships pixel hits generated by the FPIX chips at high speed (~16Gb/s/plane).
• Accepts Initialization, Control and timing information for the FPIX chips.
• Provides clean clocks for FPIX and Tx chip.
• Optical links will be used for input and output links
![Page 3: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/3.jpg)
Data In Out requirements:
• Must fit in a tiny space at the corners of the Pixel planes.
• Radiation hardness: 1 Mrad
• Low Power budget: 1 W/corner
• Low material budget: no ferromagnetics.
• Everything must operate in the vacuum.
• EMI noise resistant.
![Page 4: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/4.jpg)
Data In Out block diagram
Token_in #1
Data bus#1
Token_out#1
Token_in #2
Data bus#2
Token_out#2
Tx serializerand VCSELdriver
8
8
16?
VCSELFiber Pigtail
Dataconcentrator
chip #1
Data Bus #1
Data Bus #2
PINdiode
Fiber Pigtail
106MHz + control data
Receiverchip
53 MHz Marter Clock
PIXELCHIP
shift_in#1 shift_in#1 shift_in#1
shift_in#2
shift_in#2
Token#1 Token#1 Token#1 Token #2
53 MHz MarterClock
PIXELCHIP
PIXELCHIP
PIXELCHIP
BCO + control and initializationsignals
Token #2
Token#1
Data Concentrator Control
![Page 5: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/5.jpg)
Optical link receiver chip goals:
• Initialize FPIX chips
• On line control FPIX chips
• Generate appropriate timing for FPIX
• Some on line control to the Data Concentrator chip
• Supply clean clocks
![Page 6: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/6.jpg)
Optical link characteristics:
• VCSEL: Ithmin=5mA, Opt. Power: 1mW (min).
• PIN: responsivity 0.3 A/W.
• Optical Receiver: Current to voltage front-end amplifier.
• Cost: > $150/fiber:
– VCSEL: $35
– PIN: $35
– Rad hard fiber: $3.5/m total(10m): $35
– Standard fiber: $0.15/m total(150m): $22.5
– Connector/Assembly: MT12 $80/pair, ~$15/fiber.
– Total cost per extra fiber in the Pixel Detector (~200 planes): $30K. Moral: minimize the number of fibers.
![Page 7: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/7.jpg)
Input Data characteristics:
• Three clocks:– Readout clock: 53 MHz, external. Needs jitter<100-150ps
– BCO clock: 7.56 MHz, external.
– FPIX Initialization clock (ShiftIn): few MHz needed.
• Initialization and Control data speed: few MHz needed.• Initialization and Control data/clock are not concurrent.• Conclusions:
– Data can be serialized
– 53MHz clock and ShiftIn can share the same channel.
– Both clocks and data can share the same channel
![Page 8: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/8.jpg)
Data and clock onto a single fiber (1)
• Single fiber for clock and data.
• Guarantied transition every clock cycle.
• DC balanced.• Self clocking.
0 0 0 1 0 0 0 1 1 0 0
132ns 132ns
132ns 132ns
0 0 0 1 0 0 0 1 1 0 0
• Figure: (upper) Bi-Phase mark encoding (lower) Manchester encoding
![Page 9: BTeV Pixel Detector Optical link receiver chip Data In and Out project.](https://reader036.fdocuments.in/reader036/viewer/2022082612/56649f1c5503460f94c323e2/html5/thumbnails/9.jpg)
Data Frame:
Start CONTROL DATA Start CONTROL DATA
• Start: frame synchronization
• Command: internal acction on FFs and logic.
• Data: Init. Data for Fpix chips.
Start 1 bitCommand Up to 12 bitsData 1 bit
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Optical Receiver Block Diagram
8-bits Shift RegisterSerial In
8-bits parallel
Command Decoder
FF
FF.......
53MHz ck
?
?>10 CMOS
LVDS
LVDS
Diff PECL
PLL
LVDS
BCO clock
DAC Charge Inj.
Clockextractor
106 MHz biphase signal?
Reset
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Optical Receiver Command List•
Command Value1 Data Reset2 Data Reset Low3 Program Reset4 Program Reset Low5 BCO_ck_en6 BCO_ck_dis7 ShiftIn_en#18 ShiftIn_en#29 Load/Kill_set10 Load/Kill_reset11 Set_ScanPath#012 Set_ScanPath#1
Command Value13 Set_ScanPath#214 Set_ScanPath#315 Set_ScanPath#416 Set_ScanPath#517 Set_ScanPath#618 Set_ScanPath#719 Trigg/Acc_high20 Trigg/Acc_low21 Token_eneble22 Report_Status23 Receiver reset
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Optical Receiver chip specifications:
• Input signals: PiN signal is AC coupled to comparator. Input power about 1 mW. PiN responsivity > 0.3A/W.
• 53 MHz clock jitter: 100-150ps
• Output signals: CMOS and LVDS to the FPIX chip
• Noise: as a function of BER. For instance: 10^-12 for the channel after irradiation => S/N > 15. We probably need S/N > 20 at the receiver.
• Radiation: 10^13 n/cm² plus 1Mrad maximum estimated.
• Physical size: must fit in 7 cm². The area is not rectangular but with an ugly shape. Unless the mechanical specification of the Pixel Plane changes.
• Temperature: -20C to 30C ?
• Vacuum:
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Some questions:
• Will the receiver input need a PLL?
• Can IC tap delays be as accurate as required for the 106 MHz data case over time, temperature variations & accumulated radiation effects?
• How is a frame error detected remotely? Is it really necessary to detect frame errors. Won’t the system let you know of some error if framing is lost.
• Do startup problems arise (e.g., due to capacitor charge up times) if the receiver’s input signal is turned off for a brief period? Is it better to have the receiver check for a unique 14-bit data pattern (e.g., all ones) for proper framing detection?
• How does the slow control system get control data back from Denes’ ICs if that is the path for read-back of control/downloading information?