Dr. Bore Gowda S BECE Department Manipal Institute of TechnologyManipal-576104

IntroductionWhat is computer ?Programmable electronic device that can store, retrieve, and process data.orA computer is a machine that manipulates data according to a list of instructions. Classification of Computers (power and price) Personal computersMainframesSupercomputersDedicated controllers Embedded controllers

Evolution of ComputersFirst generation (1939-1954) - vacuum tubeSecond generation (1954-1959) transistorThird generation (1959-1971) ICFourth generation (1971-present) microprocessor

Computers organizationWhat is Microprocessor?It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and provides results as output. The P is the brain of the microcomputerIt is a single chip which is capable of processing datacontrolling all of the components which make up the microcomputer systemP used to sequence executions of instructions that is in memoryP Fetch , Decode , and Execute the instructionThe internal architecture of the microprocessor is complex.

Intel 80x86 Processor Evolutions

psYearTransistorcountClock(MHz)Internal data busExternalData busAddressbusMemory4004197122500.1084-bit4-bit-----8080197460002-38-bit8-bit16-bit64KB8085197665003-88-bit8-bit16-bit64KB80861978290005-1016-bit16-bit20-bit1MB80881979290005-816-bit8-bit20-bit1MB8028619821340008-1232-bit16-bit24-bit16MB80386198527500016-3332-bit32-bit32-bit4GB8048619891.2million25-10032-bit32-bit32-bit4GBPentium19933.1million60-23332-bit64-bit32-bit4GBPentium Pro19955.5million150-20032-bit64-bit36-bit4GBPentium II19977.5million233-40032-bitPentium III199928.1million55032-bit

Micro Processor UnitMicroprocessor Unit (MPU) typically containsRegisters: Temporary storage locations for program instruction or data.The Arithmetic Logic unit (ALU): This part of the MPU performs both arithmetic and logical operationsTiming and Control Circuits: that keep all of the other parts of system (Regs, ALU, memory & I/O) working together in the right time sequence

What are microprocessor-based systems?Microprocessor-based systems are electrical systems consisting of microprocessors, memories, I/O units, and other peripherals.Microprocessors are the brains of the systemsMicroprocessors access memories and other units through busesThe operations of microprocessors are controlled by instructions stored in memories

Microprocessor-Based System with Buses

Introduction to 8086Released by Intel in 1978Produced from 1978 to 1990sA 16-bit microprocessor chip.Max. CPU clock rate :5MHz to 10MHzPackage: 40 pin DIP The 8086 gave rise to the x86 architecture of Intel's future processors.Common manufacturer(s): Intel, AMD, NEC, Fujitsu, Harris (Intersil), OKI, Siemens AG, Texas Instruments, Mitsubishi. 16-bit Arithmetic Logic Unit 16-bit data bus 20-bit address bus - 220 = 1,048,576 = 1 MegaIt requires single phase clock with 33% duty cycle to provide internal timing.

8086 ArchitectureThe 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU fetches instructions, reads and writes data, and computes the 20-bit address. The EU decodes and executes the instructions using the 16-bit ALU.

8086 ArchitectureBIUEU

123456

The BIU fetches instructions using the CS and IP, written CS:IP, to construct the 20-bit address. Data is fetched using a segment register (usually the DS) An effective address (EA) computed by the EU depending on the addressing mode.

Components in BIU Segment registerThe instruction pointer Address generation adderBus control logic Instruction queueBIU Operation

EU Operation1. Fetch an instruction from instruction queue2. According to the instruction, EU control logic generates control signals. (This process is also referred to as instruction decoding)3. Depending on the control signal, EU performs one of the following operations: An arithmetic operation A logic operation Storing a datum into a register Moving a datum from a register Changing flag registerComponents in EUArithmetic logic unit(ALU)Status and control flagsGeneral-purpose registersTemporary-operand registers

Instruction Queue and PipeliningWhile the EU is decoding an instruction or executing an instruction which does not require use of the buses, the BIU fetches up to six instruction bytes for the following instructions. The BIU stores these prefetched bytes in a first-infirst-out register set called a queue.This prefetch-and-queue scheme greatly speeds up processing. Except in the cases of JMP and CALL instructions, where the queue must be dumped and then reloaded starting from a new address.Fetching the next instruction while the current instruction executes is called pipelining.

8086 Programming Model 16-bit Registers

Flag Register Control Flags Status FlagsIF:Interrupt enable flagDF:Direction flagTF:Trap flagCF:Carry flagPF:Parity flagAF:Auxiliary carry flagZF:Zero flagSF:Sign flagOF:Overflow flagFlag register contains information reflecting the current status of a microprocessor. It also contains information which controls the operation of the microprocessor.Called as Program Status Word (PSW)

1514131211109876543210xxxxOFDFIFTFSFZFxAFxPFxCF

Memory Address Space and Data Organization8086 has 20 bit address bus, and it supports 220 = 1,048,576 i.e. 1 Mbytes of external memory. The memory of an 8086 is organized as 8-bit words, not as 16-bit words.An 8-bit data is stored in a locationA word i.e. 16-bit data is stored in two locations,Lower byte is stored in lower address memory locationHigher byte is stored in higher address location

Segment Registers and Memory Segmentation in 8086The addresses of the active segments are stored in the four internal segment registers: CS, SS, DS, ES

Segment Registers and Memory Segmentation in 8086In 8086 1 MB of physical memory is divided into 16 blocks of 64KB, out of these the 8086 defines four active 64KB memory blocks or segments.A segment represents an independently addressable unit of memory consisting of 64K consecutive byte wide storage locations. Each segment is assigned a base address that identifies its starting point.Only four segments can be active at a time: Code segment to store instructions code of a programStack segment to store stack of data using PUSH/POPData segment to store data bytes/wordsExtra segment additional segment for storing data4 LSBs of base address should be always 0H

Segment Registers and Memory Segmentation in 8086DS: E000 CS: B300SS: 7000 ES: 5D27

User accessible segments can be set up to be contiguous, adjacent, or even overlapping.Segment Registers and Memory Segmentation in 8086

Advantages of memory segmentation Allow the memory capacity to be 1Mb even though the addresses associated with the individual instructions are only 16 bits wide.Facilitate the use of separate memory areas for the program, its data and the stack.Permit a program and/or its data to be put into different areas of memory each time the program is executed.Multitasking becomes easy.Segment Registers and Memory Segmentation in 8086

Instruction Pointer (IP)The instruction pointer (IP) identifies the location of the next word of instruction code to be fetched from the current code segment of memory.The offset in IP is combined with the current value in CS to generate the address of the instruction code.During normal operation, the 8088 fetches instructions from the code segment of memory, stores them in its instruction queue, and executes them one after the other.

General Purpose RegistersData Registers

Data registers are used for temporary storage of frequently used intermediate results.The contents of the data registers can be read, loaded, or modified through software.Each register can be accessed either as a whole (16 bits) for word data or as 8-bit data for byte-wide operation.

General Purpose Registers

General Purpose RegistersPointer and Index RegistersThese four registers must always be used for 16-bit operations

General Purpose RegistersPointer Registers

The pointer registers are used to store offset addresses of memory location relative to the stack segment register.Combining SP with the value in in SS (SS:SP) results in a 20-bit address that points to the top of the stack (TOS). BP is used to access data within the stack segment of memory.Index Registers

The index register are used to hold offset addresses for instructions that access data in the data segment.The source index register (SI) is used for a source operand, and the destination index (DI) is used for a destination operand.

Segment Register DefaultsGenerating Memory Addresses / Physical address

Generating Memory Addresses / Physical address8086 has 20 address pins, so each memory location connected will have 20-address, i.e. from 00000h to FFFFFh. The 20-bit actual address of memory locations is called physical address (PA). Memory address / Physical address is obtained by adding the shifted value of base address in segment register to Effective Address(EA).= Segment Registers X 10H + EAwhere EA = offset address + displacement(if any)

If the content of code segment register is 2500h and the content of IP is 0002H. What is the physical address of the instruction?

Solution:

[CS]=2500h---segment register[IP]=0002h ---offset value

EA= offset value + displacementEA=0002h+0 = 0002h

PA=segment register X 10h + EAPA=2500h X 10h + 0002h PA=25000h+0002h=25002hGenerating Memory Addresses / Physical address

Generating Memory Addresses / Physical addressCalculate the memory address of the data in the instruction MOV AL, [5923h]. Assume that [ds]=7000h.

PA= 7000h X 10h + 5923h = 70000h + 5923h = 75923h

If MOV DL, 0Ah[SI], What is the address of data in the memory? Assume that [ds]=8500h, [si]=1234h

EA= SI + 0Ah=1234h + 0Ah = 123EhPA= DS X 10h + EA = 8500h X 10h + 123Eh = 85000h + 123Eh = 8623Eh

Generating Memory Addresses / Physical addressCalculate the PA of the data in the instruction MOV AL, [SI][DI]10. Assume that [ds]=7000h, [SI]=0500h, [DI]=0012h.

EA= SI + DI + 0Ah=0500h + 0012h + 0Ah = 051ChPA= DS X 10h + EA = 7000h X 10h + 051Ch = 70000h + 051Ch = 7051Ch

If ADD DL, [BP], What is the address of data in the memory? Assume that [SS]=3000h, [BP]=1234h

EA= BP + 0=1234h + 0 = 1234hPA= SS X 10h + EA = 3000h X 10h + 1234h = 30000h + 1234h = 31234h

Addressing Modes When a Microprocessor executes an instruction, it needs to know where to get data and where to store results. Such information is specified in the operand fields of the instruction.An instruction acts on any number of operands. The way an instruction accesses its operands is called its Addressing modesOperand is data on which microprocessor operatesOperands : in Registers, Memory, I/O ports, and within InstructionOperands typesImplicitExplicitBoth Implicit and Explicit

Classification of Addressing ModesImplicit addressing modeImmediate addressing modeRegister addressing modeMemory addressing modesDirect addressing modeIndirect addressing modesRegister indirect addressingIndexed addressingRegister RelativeBased indexed addressingRelative Based indexed addressing I/O port addressingFixed port addressingVariable port addressing

Addressing ModesImplicit addressingThe data value/data address is implicitly associated with the instruction. In the instruction neither the source nor the destination is specified.Examples: DAA, AAA, STC, AAM

Immediate addressingOperand is stored as part of the instructionAppears in the form of successive byte or word Resides in the code segment not in the data segmentfaster to execute an instructionExamples:ADD AL, 25HSUB AX, 1200DMOV SI, 25HAND CH, 01110010B

Addressing ModesRegister addressing mode

8-bit/16-bit data required for execution is stored in 8-bit/16-bit registersThe names of registers are specified in the instructionAll the registers except IP may be used in this mode

Examples: MOV AL, BHADD AX, BXMOV SI, DXAND BH, CL

Addressing ModesMemory addressing modesMemory (RAM) is the main component of a computer to store temporary data and machine instructions. In a program, programmers many times need to read from and write into memory locations.8-bit/16-bit data required for executing the instruction is present in the memory location.

Direct addressing16-bit offset address of the memory location is specified directly in the instruction as a part of it

Examples:MOV AL, [1500H] ADD AL, ES:[3400H]

Addressing ModesMemory addressing modes (Contd)

Indirect addressing modeRegister indirect addressing mode

Offset address of memory location is specified in the register [BX] or [SI] or [DI]The default segment is either DS or ES

Offset Address = [BX] / [SI] / [DI]

Examples: MOV CX, [SI]ADD AH, [BX]

Memory addressing modes (Contd)

Indexed addressing mode

Offset of the operand is stored in one of the index registersDS or ES are the default segments for index registers SI and DI respectively

Effective Address = [SI] / [DI]

Examples: MOV DL, [SI]ADD BH, [DI]

Addressing Modes

Addressing ModesMemory addressing modes (Contd)

Register Relative addressing mode

Data is available at an effective address formed by adding an 8-bit or 16-bit displacement with content of any registers

Effective Address = [SI] / [DI] / [BX] / [BP] + 8/16-bit displacement

Examples:ADD DL, 99h[DI] orADD DL, [99h+DI]MOV AH, ES:6500h[SI]

Addressing ModesMemory addressing modes (Contd)

Based Indexd addressing mode

Effective address of the memory location is obtained by adding base register content i.e. [BX] or [BP] to the index register i.e. [SI] or [DI]

Effective Address = [BX] / [BP] + [SI] / [DI]

Examples: MOV DL, [SI][BX] or MOV DL, [SI+BX]

Addressing ModesMemory addressing modes (Contd)

Relative Based Indexed addressing modeEffective address of the memory location is obtained by adding base register content i.e. [BX] or [BP], index register i.e. [SI] or [DI] along with 8/16-bit displacement

Effective Address = [BX] / [BP] + [SI] / [DI] + 8/16-bit displacement

Examples: MOV DL, 12h[SI][BX] or MOV DL, [SI+BX+12h]

Addressing ModesI/O port addressing8086 can be interfaced to 8/16-bit I/O devices using either I/O mapped I/O or memory-mapped I/O. I/O mapped I/O uses the instructions IN and OUT 8086 can transfer 8/16-bit data to or from a peripheral deviceAll I/O transfer between the 8086 and the peripheral devices take place via AL for 8-bit ports and AX for 16-bit ports. The I/O port addressing can be done either directly or indirectly as follows:

Direct port addressingIndirect port addressing

Addressing ModesI/O port addressingDirect port addressing/Fixed port addressingIn this mode 8-bit port address is part of an instructionIt is also called as fixed port addressing, because the port address is constant.IN AL,75h or IN AX, 78h OUT 23h, AL or OUT FAh, AX

Indirect port addressing/ Variable port addressingIn this port addressing, the 16-bit port address is specified in DX registerIt is also called as variable port addressing, because the program instructions can able to change port address in DX registerIN AL, DX or IN AX, DX OUT DX, AL or OUT DX, AX

Instruction Format General Format of Instructions Label: Opcode Operand1, Operand2 ; Comment Label: It is optional. It provides a symbolic address that can be used in branch instructions Opcode: It specifies the type of instructions Operands: Instructions of 80x86 family can have one, two, or zero operand. If the instruction has two operands, they must be separated by comma Comments: Only for programmers reference

Based on the type of the operation performed, the 8086 instructions are classified into following groupsData transfer instructionsArithmetic instructionsBranch instructionsLogical instructionsShift and Rotate instructionsString instructionsProcessor control instructionsSubroutine and Interrupt Instructions Instruction Set of 8086

MOV:Move to/from register/memoryXCHG:Exchange byte or wordLEA:Load effective addressLDS:Load pointer using data segmentLES:Load pointer using extra segmentXLAT:Translate bytePUSH:Push word onto stackPUSHF:Push flags onto stackPOP:Pop word off stackPOPF:Pop flags off stackIN:Input byte or word from portOUT:Output byte or word to portSAHF:Store AH into flagsLAHF:Load AH from flagsData transfer instructions

Passing parameters to proceduresTypes: In registersIn memory locationsWith pointers possessed in registersWith the stack

Passing parameters to proceduresTypes: Using registersUsing memory locationsUsing pointersUsing stack

Passing parameters using RegistersProgram to convert the given 2-digit Hex number to ASCII.model small.stack 20.dataHex_Num DB 3FhAsc DB ?, ?.codeStart:MOV AX, @DATAMOV DS, AXMOV AL, Hex_NumCALL CONVMOV ASC, ALMOV AL, Hex_NumMOV CL, 4ROR AL, CLCALL CONVMOV ASC+1, ALINT 3CONV PROC NEARAND AL, OFHCMP AL, 0AHJC ADD30ADD AL, 07ADD30:ADD AL, 30HRETCONVENDPEND Start

Passing parameters using Memory locationProgram to check whether the given byte is bitwise palindrome or not.model small.stack 20.dataNum DB 3FhRes DW ?.codeStart:MOV AX, @DATAMOV DS, AXCALL CheckINT 3

CheckPROC NEARMOV CX, 8MOV AL, NumMOV BL, 0 UP:ROR AL, 1RLC BL, 1LOOP UPMOV Res, 5555HCMP BL, NUMJE ExitMOV Res, 0AAAAH Exit:RETCheckENDPEND Start

Passing parameters using PointersProgram to convert 2-digit BCD number to Hex .model small.stack 20.dataBCD_Num DB 3FhHex_Num DW ?.codeStart:MOV AX, @DATAMOV DS, AXLEA SI, BCD_NumLEA DI, Hex_NumCALL BCD_to_HEXINT 3

BCD_to_HEX PROC NEARMOV AL, [SI]MOV BL, ALAND BL, 0FHMOV CL, 4ROR AL, CLAND AL, 0FHMOV DL, 0AHMUL DLADD AL, BLMOV [DI], AL RETCheckENDPEND Start

Passing parameters using stackProgram to find square of 8-bit unsigned number.model small.stack 20.dataNum DB 3FhRes DW ?.codeStart:MOV AX, @DATAMOV DS, AXMOV BL, NumMOV BH, 0PUSH BXCALL SquarePOP BXMOV Res, BXINT 3

SquarePROC NEARPOP AXMUL ALPUSH AX RETSquareENDPEND Start

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