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Transcript of Backplane hsd meeting_may_8th_2012_sharable
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Welcome for HSD Success in the Multigigabit/s Era
Dr. Hany Fahmy, Master High-Speed-Digital Application Expert
Agilent EEsof EDA
April 25th , 2012
1
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High-Quality Assurance of Success
• EEsof rides the wave of HSD by wearing the shoes of the HSD
Designers
• Don’t provide “JUST-TOOLS” but Provide “DESIGN-WORKFLOW”
• Understands the “Pain” our Customers in designing Multigigabit
Technology
• Strive to Adapt the needs of our Customers through “Continuous
Improvement” of our Design-Flow
May 8, 2012
Confidentiality Label
2
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Design and Analysis of ATCA 14-Slot Dual
Star 10G ETHERNET Backplane
10GBps per lane (10x10 100GBps)
Towards 25GBps per lane (4x25 100GBps)
May 8, 2012
Confidentiality Label
3
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Agenda
08.05.2012 4
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
4) Simulation Setup for the Backplane
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Simulation Environment: Blade
Lanes routed TOP-2-Bottom &
TOP-2-Inner
08.05.2012 5
TOP-2-Bottom routing channel
TOP-2-Inner (L10/L12) routing channel
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Building blocks of the Blade
IC Package: coupled model w BGA Balls
08.05.2012
6
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Stackup Parameters for the Blade
May 8, 2012
Confidentiality Label
7
2.4 mm ± 10 %
Layer
Num.Name
Thickness
(mil)
Dielectric
Constant
(Er)
--- 0.7 4.2
1 TOP Plated Copper Foil 1.6
Prepreg 2.8 4.1
2 L2_GND Copper foil 0.6
Core 4 4
3 L3 Copper foil 0.6
Prepreg 10 4.3
4 L4_GND Copper foil 0.6
Core 4 4
5 L5 Copper foil 0.6
Prepreg 10 4.3
6 L6_PWR Copper foil 1.2
Core 4 4
7 L7 Copper foil 1.2
※ Prepreg 10 4.3
8 L8 Copper foil 1.2
Core 4 4
9 L9_PWR/GND Copper foil 1.2
Prepreg 10 4.3
10 L10 Copper foil 0.6
Core 4 4
11 L11_GND Copper foil 0.6
Prepreg 10 4.3
12 L12 Copper foil 0.6
Core 4 4
13 L13_GND Copper foil 0.6
Prepreg 2.8 4.1
14 BOT Plated Copper Foil 1.6
--- 0.7
92.4
93.8 (
2.383 (
Board Thickness (mil)
Total Thickness (mil)
Total Thickness (mm)
SolderMask ---
0.5 oz
1080
0.5oz
Core
0.5oz
Prepreg
0.5oz
Core
0.5oz
Prepreg
1.0oz
Core
1.0oz
Prepreg
1.0oz
Core
1.0oz
Prepreg
0.5oz
Core
0.5oz
Prepreg
0.5oz
Core
0.5oz
1080
0.5 oz
SolderMask ---
PCB Thickness:
Material
RD name: Sam Cheng #1254
Manufacturer: 博智
Model Name: MIC-5332
請板廠依實際
需要微調各疊
層厚度
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STUDYING THE TARGET
IMPEDANCE ROUTING OF THE
BLADE
May 8, 2012
Confidentiality Label
8
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BACKPLANE DESIGN WORKFLOW
STACKUP DEVELOPMENT
May 8, 2012
Confidentiality Label
9
STACKUP
DEVELOPMENT
PCB MATERIAL
PROPERTIES
2D MOM
MET
IMPEDANCE
TARGET?
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Realizing the Stackup in Multi-layer Library in ADS
May 8, 2012
Confidentiality Label
10
Deck: Impedance_compliance_tests-1
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Impedance Analysis
Top Layer Routing on Blade (IC-2-Cap)
4.5/5/4.5 75 Ω (85 Ω – 12%)
08.05.2012 11
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08.05.2012 12
Impedance Analysis
Top Layer Routing on Blade (IC-2-Cap)
3.5/10/3.5 90 Ω (100 Ω – 10%)
08.05.2012 12
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Impedance Analysis
Inner Layer Routing on Blade (Cap-2-ZD Conn)
7/5/7 75 Ω (85 Ω – 12%)
08.05.2012 13
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08.05.2012 14
Impedance Analysis
Inner Layer Routing on Blade (Cap-2-ZD Conn)
5.5/10/5.5 90 Ω (100 Ω – 10%)
08.05.2012 14
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Blade Routing (Top-2-Inner Layer 10)
May 8, 2012
Confidentiality Label
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Building blocks of the Blade
Deck: Blade_TOP_2_INNER_FINAL
08.05.2012 16
IC-pad:
21-mils
Mismatch-
TL: 50-mils
Mismatch-
TL: 50-mils
Cap-pads: 28-mils IC-2-Cap-TL:
265-mils
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Building blocks of the Blade
Cap-2-Inner Layer (L10) 3D-Via-Model
08.05.2012 17
TOP-
VIEW
Expanded
Inner-VIEW
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BLADE-VIA Diff-S-CHARACTERISTICS
May 8, 2012
Confidentiality Label
18
Good IL/RL up to 10GHz with
worst IL of ~ -2dB
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TDR Analysis of the Blade-VIA
May 8, 2012
Confidentiality Label
19
The Via drops down the impedance to 82-ohms by 18-ohms
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DEMO FOR THE BLADE-VIA MODELING IN MOM
May 8, 2012
Confidentiality Label
20
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Building blocks of the Blade
Bottom layer or Inner-layer routing
08.05.2012 21
Cap-2-ZD Connector-pad TL
on
Bottom or Inner layers: 1250-
mils
Break-in connector-pad: 975-mils
Mismatch-TL: 50-mils
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Building blocks of the Blade
Bottom-2-Top or
Inner-2-Top ZD Connector PIN-FIELD
08.05.2012 22
BOTTOM-2-TOP VIA FOR
CONNECTOR
INNER-2-TOP VIA FOR
CONNECTOR
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DEMO FOR THE BLADE DECK CONSTRUCTION
May 8, 2012
Confidentiality Label
23
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Agenda
08.05.2012 24
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
4) Simulation Setup for the Backplane
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I/O driver Setup
08.05.2012 25
Target Rate is 6.25GB/s
Rise-time=30ps & 20ps
Ron 100-ohms & 90-ohms
De-Emphasis is 5dB with
Tap-interval of 0.4 UI & 0.5 UI
Jitter = 0.01 UI
Test-load
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Reference-eye @ 6.25GB/s
08.05.2012 26
Width = 150ps, height = 1V, Jitter P2P=8ps & Jitter RMS = 1.7ps
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Agenda
08.05.2012 27
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
4) Simulation Setup for the Backplane
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Blade-2-Blade without Via Transitions
85W
08.05.2012 28
2.5” 2.5”
Blade-2-Blade without # 3 & 9
without connector &
without Backplane
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Simulation Results
Blade-2-Blade @ 6.25Gb/s (inner 85 Ω-12%) no Vias
De-Emphasis Tap-Interval = 0.5 UI, Ron=100-ohms
08.05.2012 29
Width = 132ps, height = 521mV, Jitter P2P=27ps & Jitter RMS = 5.3ps
Width = 150ps, height = 1V,
Jitter P2P=8ps & Jitter RMS = 1.6ps
4.5
/5 T
OP
& 7
/5 I
NN
ER
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Blade-2-Blade with Via Transitions
85W
08.05.2012 30
2.5” 2.5”
Blade-2-Blade with # 3 & 9
without connector &
without Backplane
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Simulation Results
Blade-2-Blade @ 6.25GB/s (inner 85 Ω-12%) WITH Vias
De-Emphasis Tap-Interval = 0.5 UI, Ron=100-ohms
08.05.2012 31
Width = 100ps, height = 280mV, Jitter P2P=56ps & Jitter RMS = 11.7ps
Width = 150ps, height = 1V,
Jitter P2P=8ps & Jitter RMS = 1.6ps
4.5
/5 T
OP
& 7
/5 I
NN
ER
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Impact of Blade-Vias
08.05.2012
EKH - EyeKnowHow
32
VIAs: Width = 100ps, height = 282mV, Jitter P2P=56ps & Jitter RMS = 11.7ps
NO-VIAS: Width = 132ps, height = 521mV, Jitter P2P=27ps & Jitter RMS = 5.3ps
VIAS IMPACT
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Blade-2-Blade without Via Transitions
100W
08.05.2012 33
2.5” 2.5”
Blade-2-Blade without # 3 & 9
without connector &
without Backplane
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Simulation Results
Blade-2-Blade @ 6.25Gb/s (inner 100 Ω-10%)
De-Emphasis Tap-Interval = 0.5 UI, Ron=100-ohms
08.05.2012 34
Width = 135ps, height = 740mV, Jitter P2P=25ps & Jitter RMS = 5ps
Width = 150ps, height = 1V,
Jitter P2P=8ps & Jitter RMS = 1.6ps
3.5
/10 T
OP
& 5
.5/1
0 I
NN
ER
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Compare (85Ω-12%) to (100Ω-10%)
WITHOUT THE BLADE VIAS
08.05.2012 35
521mV to 740mV
132ps to 135ps
27ps to 25ps
85W TO 100W
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Blade-2-Blade with Via Transitions
100W
08.05.2012 36
2.5” 2.5”
Blade-2-Blade with # 3 & 9
without connector &
without Backplane
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Simulation Results
Blade-2-Blade @ 6.25GB/s (inner 100 Ω-10%)
De-Emphasis Tap-Interval = 0.5 UI, Ron=100-ohms
08.05.2012 37
Width = 125ps, height = 516mV, Jitter P2P=32ps & Jitter RMS = 6.4ps
Width = 150ps, height = 1V,
Jitter P2P=8ps & Jitter RMS = 1.6ps
3.5
/10 T
OP
& 5
.5/1
0 I
NN
ER
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Compare (85Ω-12%) to (100Ω-10%)
WITH THE BLADE VIAS
08.05.2012 38
Eye-heigth:280mV to 516mV
Eye-width: 100ps to 125ps
Jitter-PP: 56ps to 32ps
85W TO 100W
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Recommendations for Blade Routing
Target impedance of 100-ohms is better than 85-ohms:
• Width increase by ~ 25ps
• Height increase by 240mV
• Jitter PP reduces by ~ 25ps
Via Transition Modeling is VERY CRITICAL
08.05.2012 39
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Recommendations for Blade Routing, Contd.
Via Structure should be optimized
• To target impedance (minimum impedance drop for TDR analysis)
• And include Backdrillling
AC Coupling caps should be optimized (e. g. cutout underneath
for better impedance matching)
Avoid routing near cutouts at connector pin field region
08.05.2012 40
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Agenda
08.05.2012 41
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
4) Simulation Setup for the Backplane
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Backplane Routing
Longest Stub: Layer-3 w
Length=9685-mils
08.05.2012 42
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Backplane Routing
3D Via modeling
08.05.2012 43
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Backplane Routing
layer 3 routing
08.05.2012 44
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Stackup of the Backplane with Material Properties
45
Core & Pre-preg are 8-mils
Dk = 3.8 @ 10GHz
Loss-Tan = 0.008 @ 10GHz
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OPTIMIZATION OF THE VIA-BP
08.05.2012
46
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Signal-Launch 6-mils away from the ref-GND plane
08.05.2012 47
Signal-Launch 6-mils
away from ref-GND
plane on Bottom
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Via-BP structure without the Extra GND plane at
20-mils from top layer
08.05.2012 48
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Diff IL response of the Via-BP without the extra
GND plane
08.05.2012
49
-9dB @ 10GHz
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Adding Supplement-GND plane is also critical to
keep Diff-IL down @ 10GHz
08.05.2012 50
Adding Suppl-GND plane
helps @ 10GHz
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Via-BP structure with the
Supplement-GND planes
08.05.2012 51
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Diff IL response of the Via-BP with the Supplement
GND plane
08.05.2012
52
-5.5dB @ 10GHz
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CURRENT DENSITY OF THE BP-VIA MOM MODEL
May 8, 2012
Confidentiality Label
53
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BP-CHANNEL PERFORMANCE
08.05.2012
54
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Coupled Simulations of the BP channel
08.05.2012
55
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BP-channel Perf Diff-IL
WITHOUT SUPL-GND Plane
08.05.2012
56
-26dB @ 10GHz
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BP-channel Perf Diff-IL
WITH SUPL-GND Plane
08.05.2012
57
-20dB @ 10GHz
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Do we still have 5/7/5 optimum routing
of BP-channel with Via-BP with
Supplement-GND plane?
08.05.2012
58
Sweeping width from 3.5-mils to 5.5-mils
Sweeping Spacing from 5-mils to 11-mils
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DEMO BACKPLANE CHANNEL CONSTRUCTION
Deck: BP_Channel
May 8, 2012
Confidentiality Label
59
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Conclusion
5/7/5 routing is the optimum routing (sweeping over HVM)
Shifting the Stackup so that the signal-launch is 6-mils away
from the Bottom Ref-GND plane is critical to control the
impedance of the launch
Adding Supplement-GND plane away from the signal-Launch
by 10-mils improve the Via-BP by ~ 4dB and the whole BP-
channel by 6dB @ 10GHz.
08.05.2012 60
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Agenda
08.05.2012 61
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
4) Simulation Setup for the Backplane
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Design Focus
• 3D Analysis of the Via-BP as Most-critical Element (minimized
impedance drop to 20-ohms)
• IL & RL Comparison of new-BP Design Compared to
measurements for old-BP
• TDR Analysis of the BP with Connector
• IEEE 802.3ba 2010 Compliance tests of the new BP
• Tx/Rx Equalization Optimization for successful operation at
6.25GBps & 10GBps
• Final Conclusion
62
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Material Properties for FR408HR
08.05.2012
EKH - EyeKnowHow
63
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New Stackup with New Material
64
Core & Pre-preg are 6-mils
Dk = 3.65 @ 10GHz
Loss-Tan = 0.0095 @ 10GHz
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Impedance Compliance for the BP
5/7/5 routing (95-ohms Diff & 54 SE)
65
Disclaimer: recommend that PCB house build a test-coupon & TDR/TDT the
impedance of the test-sample along with S-parameter Data
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How close MOM Estimate to Polar Estimate for
Impedance Calculation?
May 8, 2012
Confidentiality Label
66
54.6 MOM vs. 52.3 Polar 97.6 MOM vs. 95.5 Polar
2-ohms difference in Estimate
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VIA-BP DOMINATES THE
PERFORMANCE OF THE BP
67
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Via-BP structure with the
Supplement-GND planes with FR408HR
68
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Diff IL for the Via-BP up to 15GHz
69
Dip at ‘m2’ 14GHz
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Diff RL for the Via-BP up to 15GHz
70
10GHz < Max reflection < 15GHz
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What is the drop-down-Diff-impedance of the Via-
BP?
71
The via-BP drops the impedance down to 80-ohms
Approximately, it drops the impedance by 20-ohms
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BP-Channel Response w/o CONN:
Longest Channel+ longest Stub
Diff IL with 5/7/5 routing
72
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Comparison with measurements
“L13/14/15/16” compared to Simulated IL
(without the connector)
73
New BP design
without connector
measurements
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Comparison with measurements
“L13/14/15/16” compared to Simulated IL
(with the connector)
74
+6dB Improvement at 10GHz for the new BP Design
compared to measurements
Th
e s
imu
late
d im
pro
ve
me
nt d
ep
en
ds o
n th
e M
od
el q
ua
lity u
se
d.
Be
tte
r co
rre
latio
n to
Me
asu
rem
en
ts is o
bta
ine
d w
ith
Po
st-
layo
ut
Sim
ula
tio
ns
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TDR Analysis BP+Connector
75
Connector H/G-pins
~ 400ps delay
Via-BP
Down by 25-ohms
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Measured TDR of the 6-slots BP
08.05.2012
EKH - EyeKnowHow
76
Almost 70-Ohms dip for
Megatron-6
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COMPLIANCE TESTS OF BP
IEEE STANDARD 802.3BA 2010
77
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Insertion Loss (dB)
78
2 4 6 8 10 12 14 16 180 20
-140
-120
-100
-80
-60
-40
-20
-160
0
freq, GHz
-IL
-IL_m
ax_lo
wer
-IL_m
ax_upper
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Measured IL
79
New-BP is better than old-
BP by +6dB @ 10GHz
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Fitted Attenuation (dB)
80
2 4 6 8 10 12 14 16 180 20
-70
-60
-50
-40
-30
-20
-10
-80
0
freq, GHz
-A-A
_m
ax
-IL
-9dB @ 6GHz
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Measured Fitted Attenuation
08.05.2012
EKH - EyeKnowHow
81
New-BP is better
than old-BP by
+6dB @ 6GHz
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Measured Fitted Attenuation, Contd.
08.05.2012
EKH - EyeKnowHow
82
New-BP is better
than old-BP by
+6dB @ 6GHz
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Insertion Loss Deviation
83
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.51.0 6.0
-3
-2
-1
0
1
2
3
-4
4
freq, GHz
ILD
ILD
min
ILD
max
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Measured ILD
84
Much better performance of the
new-BP for ILD
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Return Loss (Magnitude)
85
1E91E8 1E10
5
10
15
20
25
30
35
40
45
50
55
0
60
freq, Hz
RL
freq[idx_lower::idx_middle], Hz
RLm
in_lo
wer
RLm
in_m
iddle
freq[idx_upper::idx_fmax], Hz
RLm
in_upper
10GBASE-KR Return Loss Plots with Limit Lines
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BACKPLANE DESIGN WORKFLOW
Meeting the IEEE 802.3ba Target
May 8, 2012
Confidentiality Label
86
VIA PARAMETERS
PCB MATERIAL
PROPERTIES
& STACKUP
3D MOM
MET BP
COMPLIANCE?
BP TL ROUTING
2D MOM
MULTI-LAYER
LIBRARY
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EYE-DIAGRAM CHANNEL
RESPONSE BLADE-BP-BLADE
BLADE IS WORST-CASE 85-W
87
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Eye-Diagram @ 5GBps
Blade-BP-Blade
without Tx/Rx Equalization
88
Blade routing is worst-case of 85-W
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Eye-Diagram @ 5GBps
Blade-BP-Blade
with Rx Equalization (FFE 2/4)
89
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Eye-Diagram @ 6.25GBps
Blade-BP-Blade
with Rx Equalization (DFE 6-taps )
90
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OPTIMIZATION OF DRIVER FIR
EQUALIZER SETTING AND
RECEIVER DFE SETTINGS @
6.25GBPS
91
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Jitter PP Optimized setting:
Tx FIR pre-cursor = ‘3’, post=‘5’
92
Worst jitter
pp=30ps
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Eye-width
93
Worst eye-
width = 130ps
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Eye-height
94
Worst height
= 1.58V
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eye-diagram with all FIR EQ settings
95
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OPTIMIZATION OF TX FIR
EQUALIZATION SETTINGS FOR
10GBPS OPERATION
96
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Jitter PP Min
FIR Setting: pre-cursor ‘1’ post ‘5’
97 Jitter 38ps
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Eye-width maximization
98 Width is 62ps
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Eye-height max
99 Height is 240mV
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eye-diagram combined
100
Best FIR setting is
Pre-cursor ‘1’ & post ‘5’
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DEMO SETTING THE TX FIR EQUALIZATION
PARAMETERS
May 8, 2012
Confidentiality Label
101
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Conclusion
• Via-BP was shown to dominate the performance of the BP especially > 5GBps (new-Via-BP causes ONLY 20-ohms to 25-ohms drop in impedance with TDR analysis)
• New Material + stackup + via-BP +6dB improvement in IL @ 10GHz for worst-BP-channel (longest with longest stub) passes all Compliance tests IEEE 802.3ba 2010
• Tx FIR & Rx DFE Equalization helps open the eye for higher data rates of 6.25GBps and above
• successful FIR settings of Tx & DFE settings of Rx was shown @ 6.25GBps & 10GBps
102
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IBIS-AMI MODELING DISCUSSION
May 8, 2012
Confidentiality Label
103
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In Statistical Channel simulation mode, can we use
RX adaptive DFE in simulation and output DFE
taps?
For example, Broadcomm warplite_kr rx AMI
model, there is no Getwave function, but it include
DFE and there is no problem to run DFE channel
simulation. Altera S4/S5 AMI model, under
Statistical channel simulation, it is also OK to
include DFE model.
May 8, 2012
Confidentiality Label
104
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105
Two Kinds of Tx/Rx Plus
a “Hybrid”
Model’s Init_Returns_Impulse flag
is:
False (“Can’t be
modeled as LTI”)
True (“LTI model
via impulse
response”)
Model’s
GetWave_Exists
flag is:
False (“Model is
pure LTI”)
Empty model: not
allowed
Typical case for
Tx and simple
Rx’s (fixed Eq.
and no CDR)
True (“NLTV
model via
waveform
modification”)
Typical case for
Rx (Adaptive Eq.,
CDR)
Buyer beware:
LTI approximation
of NLTV device if
used in stat mode
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Channel Simulator:
Statistical Mode
Tx model’s Init_Returns_Impulse
flag is:
False (“Tx
cannot be
modeled as
LTI”)
True (“Tx can be
modeled as LTI
using
AMI_Init()”)
Rx model’s
Init_Returns_Impulse
flag is:
False (“Rx
cannot be
modeled as LTI”)
True (“Rx can be
modeled as LTI
using AMI_Init()”)
“Case 1”
106
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107
Channel Simulator:
Bit-by-bit mode
Tx model’s GetWave_Exists flag is:
False (“Tx has
no NLTV
character”)
True (“Tx
models NLTV by
modifying
waveform”)
Rx model’s
GetWave_Exists
flag is:
False (“Rx has
no NLTV
character”)
“Case 2” “Case 5”
(Practically never
used)
True (“Rx
models NLTV by
modifying
waveform”)
“Case 3” (Most
common case)
“Case 4”
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Five Cases
108
Mode Bit pattern? Tx Analog &
Channel
Rx
1 Statistical None: stochastic
properties of
infinite bit pattern
LTI LTI LTI
2 Bit-by-bit Any finite bit
pattern
LTI LTI* LTI
3 Bit-by-bit Any finite bit
pattern
LTI LTI* NLTV
4 Bit-by-bit Any finite bit
pattern
NLTV LTI* NLTV
5 Bit-by-bit Any finite bit
pattern
NLTV LTI LTI
*ADS can handle NLTV mid-channel repeaters
using a proprietary extension
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1. Analog and
channel impulse
response
2. “Smart” convolve
with Tx
3. “Smart” convolve
with Rx
Pre-Work for Thru Channel: All 5 Cases
109
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Case 1: Statistical Mode
Tx and Rx modeled by their impulse responses
Eye pattern diagram (density, BER contours, bathtubs)
calculated directly from pre-work:
…using statistical methods that include jitter and crosstalk
handling
110
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Case 3: Bit-by-bit Mode: Tx modeled by impulse
response, Rx modeled by waveform modification
1. Bit pattern:
2. Convolve with composite analog/channel/Tx impulse:
3. Modify waveform using Rx model algorithm:
4. Eye pattern diagram from Rx output waveform
• Details of jitter handling in next slide…
111
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Two Methods of Handling Rx Jitter
112
1) When clock ticks are available:
bit-by-bit and clock ticks available from Rx
GetWave
…waveform segments between [tick, tick+UI]
are used to construct the eye to capture Rx
sample time jitter. Eye is centered at tick+UI/2.
2) When clock ticks are not available, Rx_Clock_PDF is convolved with
eye pattern diagram:
• Statistical mode
• Bit-by-bit mode but no clock ticks
UI
UI
UI
tick 1
tick 2
tick 3 eye center @ tick+UI/2