Baby-Mind SiPM Front End Electronics Yannick FAVREUniversity of Geneva3-09-2015 Etam Noah A. Blondel...
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Baby-Mind SiPM Front End Electronics Yannick FAVRE University of Geneva 3-09-2015 Etam Noah A. Blondel 1
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Transcript of Baby-Mind SiPM Front End Electronics Yannick FAVREUniversity of Geneva3-09-2015 Etam Noah A. Blondel...
Baby-Mind SiPM Front End ElectronicsYannick FAVRE University of Geneva 3-09-2015Etam NoahA. Blondel
1
OUTLINE
• Baby–Mind Detector Electronics Overview• Baby–Mind Readout Chain Overview• Front End Board• FPGA Firmware• Readout & Slow Control Protocol• Status & Conclusion
2
• Baby-Mind = 18 modules with ~3000 SiPM based channels on plastic scintillator bars
• Modular architecture : • 1 Module = 2 planes (XY)• 1 plane = 84 channels + 1 FEB with
• 3x32-ch CITIROC ASIC (3x4-ch unused)• Analog & timing measurement
• 1 channel = • 1 bar + custom optical connector + mini PCB + coaxial cable• SiPM = MPPC S12571-025C 1x1mm²
3
Module
SiPM + mini-PCB + coax.
BABY-MIND ELECTRONICS DETECTOR OVERVIEW
Scintillator bars
Board to Board cabling
FEBbottom
FEBtop
Power supply cabling
Mechanical support
FEBbottom
FEBtop
Optional double side instrumented bars
Integration
BABY-MIND READOUT CHAIN OVERVIEW
4
FEBdata/cmd
VME rack Detector
FEBFEB
FEB
FEBFEB
FEBFEB
...
FEBFEB
FEBFEB
VRB
VRB
VRB
...
ACMTrigger/s
Optical module
Beamline
Data/cmd
PC Data/cmd
TOF
Cherenkov
Trigger/Sync
Beam
Trigger/sync
enable
Control & counting room
ACM : AIDA Clock ModuleVRB : VME Readout Board
FEB : Front End BoardTOF : Time Of Flight
#1#2
#N
#1#2
#N
#1#2
#N
#1
#2
#N
Adapterdata
cmd
Trigger/sync
IN O UT
data/cmd
Trigger/sAdapter
data
cmd
Tri gg er/sy nc
IN
O UT
.. .
data/cmd
Trigger/sAdapter
data
cmd
.. .
IN
SMA+COAXIAL CABLES RJ45 + CAT5/6 CABLES
MICE LEGACY & REUSE (VME Readout Board)
240
Cmd/Trigger/Spill
data
Plastic scintillator bars
LG HG
FEB
1----------------------------28 29----------------------------56 57----------------------------8484 SiPM
Cables/FlexConnector(s)
VRB /Prev. FEB
NEXT FEBC/T/S
RJ45PREVIOUS
data
RJ45NEXT
3 pairs pair
Humidity+ T(°C)
Power24V
Internal LVs(1.2/1.8/2.5/3.3V…)
HV
Connector(s) Connector(s)
CITIROC #1
SMA
LG
HGLG
HG
HV monitor
Analog in stage +12-bits x 8-ch ADC
CITIROC #2CITIROC #0
Board ID
USB3.0
USB3.0 µCCYUSB3012
GbitXceiver
FPGA
GbitXceiver
Digitized outputOR32 trigger32 indiv. triggersAnalog signals
CITIROC
Slow CTRL
Mux
FRONT-END BOARD
5
• 96 coax. connectors (84 used)• 3 CITIROC ASICs 32-ch• 12-bits 8-ch 40Ms/s/ch ADC• Altera ARIA5 FPGA :
• Timing : 2.5ns resolution• Analog : 8µs for 96-ch LGain & HGain• HV, ASIC T° + board T° + RH%
• Readout/Slow control on USB3 and/or Gigabit RJ45 chain
• External propagated Trig/sync. Signal• Power supplies (HV/LV)
FPGA
ASICs
LVs
ADC130
USB
HV
96 coax. (top/bot)
RJ45
24V
FEB prototype
FPGA FIRMWARE
6
LG/HG
FIFO
ADC8-ch
Static/Dynamic/Hit2x96-ch baseline compute
Triggers96-ch Slow or Fast
CH sel,hold Hit CH (LG/HG)
CH Baseline
Fast
Calib. counter
Global Trigger
Sync
TIMING : 2.5ns, no latency
ANALOG : 8us latency for 2x96-ch
ASICs
Attributescounters
READOUT
ADC init
ASIC Slow Control
FPGAregisters
Slow control
FPGAStatus
FIFOTX
FIFO RX
USB
Gigabit
USBinterface
DPRAM
Encoder
Decoder
ADC SM
ThresholdSM
Timing counters
ReadoutSM
FIFO
FIFO
SLOW CONTROL
FPGA direct
registers
Protocol
Protocol
Hit CH
96-ch2.5ns res.
96-ch LG96-ch HGTemp, HV
Trigger/Sync-PREV
Internal Trigger/Sync
MUX DIN-NEXT
CMDOUT-NEXT
CMDIN-PREV
DOUT-PREV
USB µC
Gigabit RJ45
Gigabit RJ45
DATA LINK COMMUNICATION
PHY COM.
FPGA FIRMWARE
Limt Event Num.
SM = state machineFIFO = 1st-IN, 1st OUT memoryDPRAM = Dual Port RAM
Trigger/Sync-NEXTRJ45-NEXT
RJ45-PREV
OR32
apply
- Code : Quartus dev. tool, VHDL behavorial (design reuse) + some FPGA IP specific modules- Simulation : Modelsim test-benches for all modules
ALTERA ARIA5 (BGA896) A7 on proto, A3 or A5 on production
READOUT & SLOW CONTROL - PROTOCOL
7
• Readout & Slow control accessible on USB3 (utile 2.5-3Gb/s) or Gigabit differential links on RJ45 (800Mb/s to 5Gb/s)
• Readout protocol based on MICE legacy with :• 32-bits messages, multiple boards• Synchronization : trigger/sync, standalone free, or master request• Spill header/trailer with attributes (tags, time, board ID…) and containing N
events• Event with attributes (tags, time, event numbers) and containing N hits
• Hit based on channel ID, analog and/or timing data• Can be adapted depending on other projects needs
• Slow control protocol based on:• 32-bits messages with Master Request & Board Answer• Individual board or broadcast, single or multiple frames arguments• Transparent & easy read/write access to external & internal devices (ASIC, FPGA
registers) from a buffered DPRAM into FPGA (send/read/verify/apply slow control config.)
READOUT & SLOW CONTROL – CABLING OPTIONS
8
RJ45 NEXT
USB
FPGA
1st FEB
RJ45 PREV
RJ45 NEXT
USB
FPGA
2nd FEB
RJ45 PREV
...
RJ45 chain + USB gateway
RJ45 NEXT
USB
FPGA
1st FEB
RJ45 PREV
RJ45 NEXT
USB
FPGA
2nd FEB
RJ45 PREV
...RJ45 chain +
external readout
RJ45 NEXT
USB
FPGA
1st FEB
RJ45 PREV
USB standalone (lab, maintenance,
calibration)
To VRB or other readout system
To host PC
- Number of chained FEB depends on events frequency and bandwidth limit => application specific- Ex : 8 chained FEB for Baby-Mind (VRB limitation)
READOUT – USB3 software
9
• C# Win7 (ms visual studio)• Versatile architecture designed for reuse:• Low level classes for protocol communication
handling• Hardware slow control direct building & mapping
through abstraction classes• Direct connection to FPGA/ASIC trough USB3• Simple building & hardware mapping• File handling (HML open/save File)• Ex : myBoard.myAsic[0].addVar(Type, Name, DefaultVal,
Min, Max, BitLocation…)
• GUI direct connection with slow control variables declared from abstraction classes :• Simple building• Automatic coherency check (Min, Max)• Ex : boolean connected to a checkBox, Byte connected to a
textBox …
• Readout Save to file:• 2.5Gb/s to 3Gb/s achieved from USB3• Some problems to be solved at low speed (low
event frequency)
• Linux planned & Labview virtual instrument
Readout & general tab
ASIC0 slow control tab
STATUS & CONCLUSION
10
• Versatile Front-End Board:• 96-channels• Timing = 2.5ns resolution (lower resolution possible with delay registers implementation)• Analog = 12-bits, 8us latency (blind window, ASIC limitation)• Autonomous or ext. trigger synchronization• 3Gb/s USB3 and/or Gigabit RJ45 diff. link • Readout & slow control access – simple but powerful & adaptive protocol
• Software:• USB3 Readout & Slow control, application specific top level using generic architecture (will be
used for 2 others projects under dev. at DPNC, DRS4/NA61, VATA64/HERD)• Current C# Win7, Planned = Linux + Labview Virtual Instrument
• Status: • Hardware:
• 5 FEB produced and ready for tests• 40 boards for January 2016
• FPGA firmware: • 90% developed & fully simulated (modelsim)• Integration with HW ongoing (50% ok), to be ready for autumn
• USB3 win7 application : • 2.5Gb/s readout full bandwidth & slow control ok (3Gb/s planned) • Some problems at low bandwidth on win side (low events frequency) • Need help (real-time & low-level software engineer)
11
Thanks for your attentionQuestions ?
12
BACKUP SLIDES
13
CITIROC BLOC DIAGRAM
Feedback capa.= 1 [arb.]48.2 ADC/p.e.
Feedback capa. = 6 [arb.] 25.6 ADC/p.e.
Feedback capa. = 4 [arb.] 32.2 ADC/p.e.
Feedback capa. = 8 [arb.]19.3 ADC/p.e.
• Regime:• high enough gain to resolve
indivual p.e. peaks whilst avoiding saturation
• Dynamic range (HG):• 12-bit ADC• Baseline ~950• 19.3 ADC/p.e.• 160 p.e.
• > 1600 p.e. with LG.
CITIROC :Varying Pre-amp Feedback capacitance
14
12.5 ns 25 ns 37.5 ns 50 nsCITIROC : shaper time constant
62.5 ns 75 ns 87.5 ns10
ns
20 n
s30
ns
40 n
s50
ns
60 n
sO
R32/
Hol
d de
lay
16
FPGA Architecture
Threshold State Machine
L1-FIFO24-bits x 128
Threshold State Machine
L1-FIFO24-bits x 128
L0-FIFO12-bits x 4
L0-FIFO12-bits x 4
L0-FIFO(hit time)
14-bits x 4
Trigger #N
FPGA
Counter12-bits(max=10µs)
RESET
WR
DIN
RD
DOUT
Period counter19-bits(max=1.3ms)
L0-FIFO(trigger period)
21-bits x 4WR
DIN
RD
DOUT
1 trigger period L0-FIFO19-b coun ter + 2-b tag
L2-FIFO32-bits x TBD
WR
DIN
RD
DOUT
L1State Machine
Start
Trigger tag counter28-bits
28-bits TAG
400MHz clock domain 100MHz clock domain from ADC DCO 100MHz clock domain
Tag counter2-bits
UP
UP
++
TAG
+
+
TAG
1:hold
2.1/2.32:mux
Sync
ASIC reset PA
3.1/3.32:read (12-bits LG+HG x3)
OR96 Trigger
ASIC SPI (read)5MHz max/ch
ASIC Hold
ADC (12-bits)
4:reset
ADC State Machine
Threshold State Machine
WR
DIN
2-bits TAG (LSB)
for32-ch
96 trigger L0-FIFOs12-b coun ter + 2-b tag
Global TRIG
Trig. time counter20-bits
(max=10.5s, res=10us)RESET
Rel. Trigger time
CAL
ACQ
Spill time counter28-bits
(max=745.6h, res=10ms)
Spill tag counter16-bits
Global SPILL
EXT SP ILL
TRIGGER
TimeoutT=2ms
FREE
USB3.0µC GPIF
CMD_IN
read
RESET
- Reset register (tag counter, time counter) from slow control command
Timeout
LATCH
UP
Dead time search
TRIG-SYNC
TIMEOUT-SYNC1st TRIG after timeout
RESET
RESET
RESET
TIMEOUTSYNC
LATCH
RESET
LIMIT
LIMIT - Limit the nb of event at 1 per global trigger period from s low contro l parameter- channel enable from slow control parameter
ENABLE
ENABLE
ENABLE
3.1/3.32:read HIT channel
- Threshold computation mode (STATIC, DYNAMIC, HIT)THD MODE
- only 10 ADC hits and 10 time hits are pushed into the L2-FIFOLIMIT10
CH + HIT
L1-FIFO24-bits x 128
RAM : 32-ch x 12-bits per TSM
- Threshold us ed to fi lter ADC values in STATIC THD MODETHRESHOLD
WR DIN
Compute/Compare/Baseline RD DOUT
12-b ADC + 7-b CH + 3-b ID (HG, LG, Bas eline, Other) + 2-b tag
LIMIT10
RESET
EXT/INT. GEN
SLOW/FAST
MUX TriggerSLOW
FAST
- selection between slow or fas t ASIC trigger lineSLOW/FAST
HR/T° state machine
N channels
HR/T° device SPI
EXT DELAY
DELAY
- delay may be applied in order to delay s ignal assertion after synchronization input signal DELAY
Error
Error
Error
Error
3xLG+3xHG = 6
3xLG+3xHG = 6
16
16
* ADC to HV & Temp. FIFO n ot shown
L2-RX-FIFO32-bits x 32
DIN
DOUTL2-TX-FIFO
32-bits x 64DOUT
DIN
DOUT
Prev NextGigabit link
wr
load
load
ASIC config SPI
rdrd
Decoder
DPRAMConfig.
ASIC SPI
FPGA config.
registers
FPGA status.
registers
Encoder
start
DIN
CMD_OUT
REQUEST/STANDALONE
Error
Delay+MUX
ENABLEDELAY
USB I/F
write
SPI & CLK
ADC
ADC init
17
Protocol
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTIONAL : Command Request Argument (multiple args)
Command Request Header
0 (no args)
Cmd Req head ID Board ID Cmd IDArgument (single arg)
Argument Frame Number (multiple args)Sub Cmd IDSub Cmd ID Argument (single arg)
OPTIONAL : Command Answer Argument (multiple args)
Cmd Ans Arg ID Frame index [0-4095]
Command Answer Header
Argument
Cmd Ans Arg ID Board ID Cmd ID
0 (no args, ack)Argument (single arg)
Sub Cmd ID Argument Frame Number (multiple args)Sub Cmd ID Argument (single arg)
Command Answer Trailer (multiple args)
Cmd Ans Trail ID Board ID Cmd ID CRC16
Cmd Req Arg ID
Command Request Trailer (multiple args)
Cmd Req Trail ID Board ID Cmd ID CRC16
ArgumentFrame index [0-4095]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 001
Board IDBoard ID
Spill trailer 2 ID
Event trailer #1
Event trailer 1 ID Trigger tagEvent trailer 2 ID Trigger time
Spill trailer
Spill trailer 1 ID Spill tag
Spill time
Hit counts within evt
Spill trailer 1 ID Humidity
Hit amplitude ID Channel ID Hit ID Amplitude ID Amplitude measurement
…Event Data : Hit #n
Hit time ID Channel ID Hit ID Hit time
Spill header
Spill header ID Spill tagBoard ID
Temperature
Event header #1
Event header ID Trigger tag
Event Data : Hit #1
Hit time ID Channel ID Hit ID Hit time
Hit Amplitude ID Channel ID Hit ID Amplitude ID Amplitude measurement
Readout
Slow Control
