B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 1

BTeV Front End Readout&

Links

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 2

BTeV Front End Systems Summary

System Channels FEBs FEB Components

Muon 69120 32ch overthreshold ASDQs, DACs, ADCs

RICH 349146 163ch overthreshold IDE, DACs, ADCs

EM Cal 23712 32ch @ 11 bits each QIE, FADC, DACs, ADCs Straws 118464 32ch @ 6 bits each ADSQs, TDCs, DACs, ADCs

Pixel

Strips

Six BTeV detector sub systems:

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 3

Front-End Readout Architecture

Analo

g De

tect

or Si

gnal

Front End Boards

Data Combiner

Board

Hi Speed SerialData Link to L1Buffer or Trigger

Control/Timing and Monitor

Link

Short Cable

• Front-End Boards (FEBs) digitize multiple analog detector signals

• Data Combiner Boards sparsify, combine, and format the data into data blocks for each BXNG.

• Data blocks are sent via high speed serial link with BXNG time stamp.

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 4

Muon System Example

• Digitized detector data is overthreshold (ASDQ)

• Each FEB is 32 channels. 32 channels equals 1 plank.

• 69120 System Channels Total

• 2160 FEBs

• 13 FEBs for each DCB. 13 FEBs equals 1 octant.

• 167 DCBs

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 5

Muon System Example

32 ChannelAnalog FEBs13 FEBs per Octant

416 Channel Data CombinerBoards (DCBs) connecing 13 FEBs1 DCB Per Octant

Octant 0

Octant 1

Octant 2

BTeV Muon System Readout

Architecture

2Gbps OpticalData Link to TriggerSystem

Control/Timing andMonitor Links

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 6

Data Combiner Board (Muon DCB Shown)

PR

OM

8B/1

0BEn

code

r

Monitor TX

Gbps Data TXDC to

DC

VXOX8

Plank 8

Plank 9Plank 10

Plank 11Plank 12

Serializer FPGAs

PRO

M

TMC FPGA2

Control & Clk RX

Plank 0Plank 1

Plank 2Plank 3

Plank 4

Pin-Diode andFiber Connectorfor Control Link.

2 Gbps VCSELand Fiber Connectorfor Data Link

80 Pin Connector

53MHz SystemClock RecoveryComponentsPower input

Level Translator

TestConnectors

Plank 5 Plank 7Plank 6

VCSEL and FiberConnector for Monitoring Link.

• System clock recovery

• Receive/decode control commands

• Combine/format data from 13 FEBs (TMC2 FPGA)

• Return Monitoring Data

• Different sized boards for different systems

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 7

TMC2 FPGA

Timing, Controland

Monitoring

Data Combining

Data

Form

attin

g

416 Channelsof FEB DataEvery BXNG

Formatted DataBlocks to High SpeedSerializer

Serialized MonitorData to Monitor LinkSerialized ControlData with 53Mhz SystemClock Embedded

Return Data from FEB Components

Control Data from FEB Components

TMC FPGA2Muon DCB

• TMC2 = Timing, Monitoring, Control, and Combining

• Different size and slightly different firmware for each system

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 8

Optical Links

Muon DCB 8B/10B Encoder and serializer @ ~2Gbps

VCSEL and Fiber Connectorfor 2Gbps Data Link

VCSEL and Fiber Connectorfor Slow Speed Monitor LinkPIN Diode and Fiber Connectorfor Timing/Monitoring Link

• Optical links will be standard across all systems

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 9

Summary of Other Systems

• RICH: DCB combines 6 FEBs. Each FEB is 163 channels.

• Straws: DCB combines 8 FEBs. Each FEB is 32 channels.

• EM Calorimeter: DCB and FEB are combined into a single board. Each DCB/FEB is 32 channels.

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 10

FEB/DCB Functional Summary

• Front End Boards (FEBs) digitize detector data every beam crossing (132ns) and send all data to a Data Combiner Board (DCB).

• DCBs connect multiple FEBs. They receive the digitized detector data, combine all data (sparsified) from the same BXNG and send it as a data block to the L1 Buffer (or trigger) via a 2Gbps optical serial link.

• DCBs receive timing and control commands from a control/timing link, control FEB components, and return monitoring information back to the BTeV Timing/Control and Monitoring System.

B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 11

Key Advantages

• Greatly reduce cable mass by combining data from many detector channels close to the detector into a single high speed optical data link.

• Architecture allows for “simple” FEBs resulting in higher reliability in difficult to access areas.

• Standard optical components (data link, control/timing link, and monitoring link) allow for interchangeable parts across systems and less development/debug time.

• TMC2 FPGA is functionally similar across each system allowing for common firmware resulting in less development/debug time.