B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 Large gate periphery InGaAs/InAlAs pHEMT:...

B. BOUDJELIDA2nd SKADS Workshop 10-11 October 2007

Large gate periphery InGaAs/InAlAs Large gate periphery InGaAs/InAlAs

pHEMT: Measurement and Modelling pHEMT: Measurement and Modelling

for LNA fabricationfor LNA fabrication

B. Boudjelida, A. Sobih, A. Bouloukou, S. Boulay, J. Sexton, T. Tauqueer, J. Sly and M. Missous

School of Electrical and Electronic Engineering

University of Manchester


OUTLINEOUTLINE

• GOALS

• Low Fmin

• Low Rn

• ACTIVE DEVICES

• INTRINSIC PROPERTIES

• MODELLING

• RESULTS

• LNA SIMULATIONS

• QUICK ADC UPDATE

• CONCLUSIONS


Workflow at University of Workflow at University of

ManchesterManchester

Material growth Process set-up and fabrication

DC & RF measurements

Parameter extraction & device modelling

Material assessment

LNA circuit design LNA layout design (process integration)

LNA

Fabrication!

Process set-up

LNA building blocks library

LNA testing


GOALSGOALSLow Fmin and Low RnLow Fmin and Low Rn

)1(1

422

2

0min

ss

soptn

Z

RFF

Four noise parameters Fmin: the minimum noise factor expected when Γs = Γopt,

Rn: the equivalent noise resistance,Gopt and Bopt: the real and imaginary parts of the optimal source admittance

Yopt, for which

opt

optopt YZ

YZ

0

0

1

1

For Broad band low noise amplification Need both low Fmin AND low Rn


GOALSGOALSLow Fmin and Low RnLow Fmin and Low Rn

Variation of Noise Resistance Rn with frequency and temperature.

Variation of Fmin with frequency and temperature.

Very difficult to achieve low Rn with submicron devices below 2GHz [*] M.R. Murti et al. IEE Transactions MTT 48(12), 2579, (2000).

300 K

200 K

18 K

300 K

200 K

18 K

(NGST 0.1 x 80 um InGaAs-InAlAs Phemt [*])


ACTIVE DEVICESACTIVE DEVICESIncreased gate metallisation thicknessIncreased gate metallisation thickness

Gate thickness h (nm) Rg (Ohm) NFmin @ 2GHz (dB)

150 21 1.2

500 2.7 0.6Comparison between VMBE#1841 transistors made with different gate metallisations

(1x200μm devices, Rg extracted, NFmin calculated for k=3.6)

23 NhLW

Rg

m

g

The gate metallisation resistance key contributor to gate resistance

For a fixed gate length: increasing gate thickness (h) reduces Rg

Why reduce it?

)((1log10min gsm

T

RRgf

fkF

Key parasitic contributor

δ

Ti/Au

AuGe/Au

AuGe/Au

h

[1]: G. Vasilescu, Electronic noise and interfering signals, Springer-Verlag Berlin Heindelberg New York, 2005

g

m

hL3 [1]


ACTIVE DEVICESACTIVE DEVICESLatest results on RLatest results on Rgg and R and Rnn

Normal trend for 2-finger devices shows an increase in Rg with increasing gate size

Rg and Rn extracted from linear and non-linear models, respectively.

Rn decreases with increasing gate size2-finger topology

Use of multi gate finger topology:

• Reduces Rg to about 2 Ohms

• Makes Rg insensitive to gate size

Use of large multi gate finger devices is the key to:

• Maintaining a low Rg

• Reducing Rn

The effect of topology on Rg and Rn XMBE#106

multi-finger topology


ACTIVE DEVICESACTIVE DEVICESNon Linear ModellingNon Linear Modelling

DC Characteristics Fit the Data very well

Kink effects not included in the model

RF Data (4x200 μm)

EE-HEMT model generated from IC-Cap measurements

Transferred to ADS and fitted to measured data


LNA SIMULATIONSLNA SIMULATIONS

The use of large inductors (generally used for input matching) on MMIC:

• Large space on chip

• Generate significant series resistance which greatly increases the noise figure

Avoiding large inductors ??

No input matching?

Off-chip components?



Single stage LNA (800 um gate width) with no input matching



Single stage LNA (800 um gate width) with no input matching

@ 1.4 GHz

•NF < 0.6dB



Single stage LNA (800 µm gate width) with off-chip components.



Single stage LNA (800 µm gate width) with off-chip components.

@ 1.4 GHz

•NF < 0.45dB


ADC SummaryADC Summary

Comparator Design Transistor Type (mm2)

Power (mW)

Power Saving (%)

1st Generation 55 1,730 -

2nd Generation55 (≠circuit) 1,200 30

1.55 502 71

3rd Generation (folding)1.55 350 80

• AIM: Design and fabrication of a 4bit 4GS/s ADC consuming 100 mW

• Current state-of-the-art : 0.18µm CMOS 4-bit 4GS/s - 220mW [1]

• FULL ADC Results to follow shortly.

[1] S. Park, Y. Palaskas, and M. P. Flynn, "A 4GS/s 4b flash ADC in 0.18m CMOS,“

IEEE Symp. On Circuits and Systems, pp 2330 – 2339, Feb 2006


ADC Basic Building BlocksADC Basic Building BlocksCurrent workCurrent work

• Basic Building blocks for the ADC designed using ADS

• Coplanar waveguide design

• Differential Amplifier

• Ex-Or/OR/AND

• Latch

• 12-Mask procedure

• HBT (9 masks)

• NiCr Resistors (~100 ohms/sq)

• 3 metal layers

• Polyimide dielectric

EX-OR Complete MMIC


CONCLUSIONSCONCLUSIONS

• Large periphery transistors are needed for low noise resistance Rn and wide band operation especially at low frequencies (< 2GHz).

• A wide range of large periphery multi-finger InGaAs/InAlAs pHEMTs have been fabricated (up to 1.2mm gate width).

• Accurate Linear and Nonlinear models have been obtained for these devices.

•Simulated LNA based on this design yield less than 0.45dB Noise figure at 1.4GHz even at 1µm gate length!

•4 bit 4GS/s ADC designed, simulated and basic building blocks fabricated.

• LNA and ADC are being fabricated now.

B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 Large gate periphery InGaAs/InAlAs pHEMT:...

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