Andrew Faulkner1 SKADS and SKA 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner.

Andrew Faulkner 1SKADS and SKA4th SKADS Workshop, Lisbon

SKADS and SKASKADS and SKA

Andrew Faulkner


Aperture ArraysAperture Arrays

are Important to the

SKA PerformanceSKA Performance


SKA Science RequirementsSKA Science RequirementsKSP ID

KSP Description Frequency Range GHz

FoV Sens-itivity

Survey Speed

Resn. Base-line

Dyn. Range

Poln.

0.1 0.3 1.0 3.0 10 30 deg2 m2/K deg2m 4K - 2 mas Km L M H L M H

1 The Dark Ages

1a* EoR >~3x107 1 L H

1b First Metals 0.003 15,000 50 125 L L

1c First Galaxies & BHs 20,000 10 4500 H H

2 Galaxy Evolution, Cosmology & Dark Energy

2a* Dark Energy 6x109 5 L L

2b* Galaxy Evolution 1x109 10 L L

2c Local Cosmic Web 2x107 0.5 L L

3 Cosmic Magnetism

3a* Rotation Measure Sky 2x108 10-30 M H

3b Cosmic Web 1x108 5 M H

4 GR using Pulsars & Black Holes

Search 1x108 ~5 - L

4a* Gravitational Waves - >15,000 1 200 M H

4b BH Spin 1 10,000 - M H

4c* Theories of Gravity >15,000 1 200 M H

5 Cradle of Life

5a* Protoplanetary Disks <10-5 10,000 2 1000 L L

5b Prebiotic Molecules 0.5-1 10,000 100 60 L L

5c SETI 1

6 Exploration of the Unknown

Large Large

AA

AAAA

AA

AA

AA


15/11/07 (v2.3) First Stage Full SKA

Parameter Phase 1 Mid-band – inc.dense AA

Phase 2 scenarios Low & mid-bands – all inc. AAs to 500MHz

Phase 3 High band

WBF only WBF+PAF* WBF only WBF+PAF* WBF+dense AA

Frequency Low Low (GHz) Range: High

500 MHz 10 GHz

500 MHz 10 GHz

70 MHz 10 GHz

70 MHz 10 GHz

70 MHz 10 GHz

10 GHz 35 GHz

Survey speed (m4K-2deg2)

70 - 200 MHz

200 - 500 MHz 0.7 GHz

1.4 GHz 3 GHz

10 GHz

25 GHz 35 GHz

1 x 107 1 x 107

2 x 106 5 x 105 2 x 104

1 x 107 3 x 107

3 x 107 1 x 105 5 x 103

3 x 109

2 x 1010

3 x 108

6 x 107

1 x 107

5 x 105

3 x 109

2 x 1010

1 x 109

1 x 109

5 x 106

2 x 105

3 x 109

2 x 1010

2 x 1010

4 x 107

1 x 107

4 x 105

4.6 x 104

2.4 x 104

Min. sensitivity at 45o Aeff/Tsys (m

2K-1)

70 - 200 MHz 200 - 500 MHz

700 MHz

1.4 GHz 3 GHz

10 GHz

25 GHz 35 GHz

200 2 000

2 000 2 000 1 300

200 1 100

1 100 1 100

700

4 000 10 000

12 000

12 000 12 000 8 000

4 000 10 000

7 000

7 000 7 000 5 000

4 000 10 000 10 000

10 000 10 000 7 000

5 000

5 000 5 000

Configuration:

core: < 1 km inner: < 5 km mid†: < 180 km

outer: <~3000 km

50 % 75 %

100 %

50 % 75 %

100 %

20 % 50 % 75 % 100 %

20 % 50 % 75 % 100 %

20 % 50 % 75 % 100 %

20 % 50 % 75 % 100 %

WFoV for Surveys: Spectral imaging / time domain

max baseline km channels #

sample rate ms

5 16 384

0.1

5 16 384

0.1

10 32 768

0.1

10 32 768

0.1

10 32 768

0.1

20 32 768

0.1

AA in all scenarios<500MHz

WBF+Dense AA

SKA Memo 100SKA Memo 100


..

Sparse AA

Dense AA

..

Mass Storage

TimeTimeStandardStandard

Central Processing Facility - CPF

User interfacevia Internet

...

To 250 AA Stations

...

DSP

...

DSP

To 2400 Dishes

...

12-15m Dishes

Correlator – A

A &

Dish

16 Tb/s

80 Gb/s

Control Processors

& User interface

Post Processor

SKA StructureSKA Structure

DigitalSignalProcessing

Data

Time

Control

70-450 MHzWide FoV

0.3-1.0 GHzWide FoV

0.8-10 GHz


Demonstrator: EMBRACEDemonstrator: EMBRACE


I/FBoard

Signal Conditioning RackSignal Conditioning Rack

LNA

Gain & Drive

Reg

Cat-7

Clock distribution

PSU AD

C

Memory

Analog Cond. Digital acquisition

Power supplies

Mid-Plane

Distribu-tion

PSU AD

C

Memory

Processing RackProcessing Rack

CyclopsProcessor

FP

GA

I/FBoard Cyclops

Processor

FP

GA

Power supplies

Beamforming processing

Backplane

10Gb links

HSS links

Bunker wall

FPGADigitalPre-

processor

FPGADigitalPre-

processor

Coax

ExternalExternalAnalogue onlyAnalogue only

AntennaArray

Control

System

I/FBoard

I/FBoard

Cooling Systems

Demonstrator: 2-PADDemonstrator: 2-PAD


Demonstrator BESTDemonstrator BEST


ChallengesChallenges

Cost:

• Processing ability, power

requirements and cost

• Digitisation implementation

• Internal & external

communication data cost

• Ability to perform back-end

processing

Technical:

• Reducing Tsys

• Limiting self-induced RFI

• Mass manufacturing

• Reducing systematics: …Dynamic Range!

• Calibration methodology

• Environmental: heat, bugs,

lightening etc


Deliverables Deliverables (just DS3 and 4!)(just DS3 and 4!)


Deliverables Deliverables (just DS3 and 4!)(just DS3 and 4!)

DS3-T11. Report on COTS technology for data links2. Report on component-based technology for data links3. Prototype phase transfer links over various span lengths4. Report on performance of phase transfer system over real

installed fibre links5. Report on prototype data links over short and long spans6. Detailed cost models for COTS and component-based

data applicable to various network and processing architectures

DS3-T21. Processing architectural design documents 2. Software design documents 3. Cost and power usage evaluations for the various

processing architectures 4. Cost evaluations for the software architecture 5. Technology assessment and road mapping overview

reports

DS3-T3

1. Initial report on conceptual issues concerning the SKA network, data flow and processing

2. Delivery of functional simulator

3. Report on analysis of performance of the SKA using the simulator

DS3-T6

1. Spec. of a prototype control and data processing system

2. Specification and implementation of constructs, interfaces and components

3. Platform specific composition/deployment of control and data processing software for several alternative hardware platforms

4. assessment of the readiness for scalabilit with MDA

5. rec. guideline for scalable design and implementation

DS4-T11. Establish benchmark LNA simulations to provide

performance feedback for device process development

2. RF on wafer (RFOW) measurements on device wafers fabricated

3. Design, fabrication and testing of SiGe band pass filter using PIC Technology

4. LNA design techniques simulation study5. ADC Design rule established and recommend ADC

architectures6. ADC building blocks design, fabrication and performance 7. Design, manufacture and test of hybrid LNA using novel

discrete devices developed in programme (two iterations)

8. Fabricate and test Integrated ADC circuits9. Fabricate and test of advanced integrated interconnect

technologies with Si and GaAs technologies. 10. Fabricate and test further LNA technologies – iterations 2

and 3 11. Fabricate and test further ADC technologies - iterations 2

and 312. Final report on different semiconductor technologies

DS4-T21. Wide band, high dynamic range A/D blocks

2. Digital Down Converters

3. Sizing of the digital word at different levels of system

4. Low cost Poly-Phase filter banks

5. Data distribution and synchronization

6. A quasi-perfect reconstruction equi-spaced filter bank

DS4-T31. Develop RFI mitigation strategies for the phased-array

concept of SKA, at a station level and for the instrument as a whole;

2. Assess the influence of these methods on data quality;

3. Assess the cost effectiveness of these methods for the RFI environment of the selected SKA site;

4. Demonstrate practical RFI mitigation techniques for the EMBRACE and BEST SKADS demonstrators

DS4-T4

1. Wide band integrated antenna, dual polarization

2. Low cost antenna technology

3. Low cost packaging solutions

4. Low cost analogue photonic link

5. Reports on all of the above deliverables

6. Publications and PhD thesis

DS4-T5

1. Analogue beamformer in GaAs for EMBRACE.

2. Prototype of a lower cost analogue beam-former in Silicon (not in time for EMBRACE.)

3. Prototype digital beamformer for 2-PAD.

4. Architecture design for the whole digital beam-forming system for 2-PAD.

5. A final report on the trade-offs and cost-effectiveness of analogue and digital beam-forming systems.

DS4-T6

1. Dual polarization all-digital tile

2. Design documentation package for all-digital tile

3. Test environment for prototype all-digital tile.

4. Evaluation report of tile performance.

5. Tile cost estimates projected for SKA volumes and timescales.

6. Reliability analysis report.All to b

e complete

d

All to b

e complete

d


Technology Readiness LevelsTechnology Readiness Levels


Technology Readiness LevelsTechnology Readiness Levels

Ref: NASA http://en.wikipedia.org/wiki/Technology_Readiness_Level

SKA in operation

SKA Phase 1

Target for AAVP

PrepSKA & SKADS

SKADS

Mostly pre-SKADS workBasic TechnologyResearch

Research to ProveFeasibility

TechnologyDevelopment

TechnologyDemonstration

System/SubsystemDevelopment

Full System Test& Operations


System GroupSystem Group

Purpose:Focussed advisory group to DS8 to prepare final SKADS report

Timing: Continue work from Design and Cost team

Deliverable: Core report and ‘arguments’ for SKADSend March 2009

Starting: Autumn 2008

Discussion: With DS8 team


System Group - MembersSystem Group - Members

Andrew Faulkner (Chair) Peter Wilkinson

Steve Torchinsky Arnold van Ardenne

Andre van Es Paul Alexander

Dion Kant Stelio Montebugnoli

Mike Jones Steve Rawlings

Rosie Bolton Jan Geralt bij de Vaate


DS8 Deliverables…DS8 Deliverables…

1. Scientific and technical specification for the SKA (T0+47);

2. Overall System Design (T0+48);

3. Costing and budget assessment paying attention to the civil works required for the overall array to be included in the Preliminary SKA plan(T0 to T0+48);

4. Preliminary SKA plan including a study of funding sources (T0+48);

5. Square Kilometre Array “White Paper” to be submitted to the International SKA Steering Committee, to the EC and to the national funding agencies which contributed to SKADS (T0+48).

Now the responsibity ofPrepSKA WP6

SKADS “Final Deliverable”

This has been embodied inSKA Memo #100. This memo or its

derivative is the deliverableWe are working on the SKA AA scenario from SKA memo #100

The cost modelling is in the System Group remit. We cannot work on

budget or civil works

Andrew Faulkner1 SKADS and SKA 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner.

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