Autonomous Memory Operating Envelope · switch, not enough current flows through the base-emitter...

Radiant Technologies, Inc.Autonomous Memory

Exploring the Autonomous

Memory Operating Envelope

Radiant Technologies, Inc.

March 16, 2015


Autonomous

Au-to-no-mous: Merriam-Webster Dictionary (on-line)

a. Existing independently of the whole.

b. Reacting independently of the whole.

An autonomous non-volatile memory operates by itself

or

is part of a larger system but still operates independently

from that system.


Summary

The autonomous memory circuit is incredibly

flexible and can be tuned to operate reliably in a

wide range of applications and harsh environments.

The purpose of this presentation is to explore the

operating envelope of ferroelectric autonomous

memory set by adjusting component values and to

understand the design rules necessary to avoid

failure modes in your application.


Summary

This presentation will use Radiant’s Single Bit Memory

Display Board as the basis for studying the autonomous

memory operating envelope.

See

SBM Board Instructions.pdf

for an introduction to the board and its basic operation.


Contents

• Review of the Single Bit Memory (SBM) Display Board function and

circuits

• Explanation of the ferroelectric capacitor in a circuit

• Examination of the effect each component in the memory circuit has on

its operation

• Analysis of failure modes.

• Reliability definitions

• Conclusion


SBM Display Board The SBM Display Board consists of an autonomous memory constructed with

discrete bipolar components, a battery pack, a ramp generator, a datum display

circuit, and input switches. Write with pushbuttons. Read with LEDs!

The SBM to the left is powered by a 9-volt

battery. It is designed to operate with Type

AB ferroelectric capacitors. AB capacitors are

specified for operation up to 9 volts.

Type AD capacitors are specified to operate at

TTL-compatible 4.2 volts. A second version

of the SBM Display Board has a 4.5-volt

battery pack that accepts three 1.5-volt AAA

batteries.

Ferroelectric capacitors can be constructed to

work at voltages ranging from 1V to >1000V

so autonomous memory circuits also have that

range for their power source!


SBM Display Board The functional diagram of the SBM

Display Board has five parts:

1. Discrete autonomous memory

2. Battery pack,

3. Ramp generator,

3. Datum display circuit, and

4. Input switches.

Battery

Ramp Generator

Autonomous

Memory Circuit

LED

Display

I

n

p

u

t

Removable

Memory Bit

Battery

Ramp Gen

Input

Display Memory


SBM Display Board Battery

Ramp

Generator

Input Autonomous

Memory

Display


Discrete Components

• The autonomous memory circuit on the SBM Display Board is built with

discrete bipolar transistors.

• Autonomous memory can be constructed from any technology, even relays.

• Bipolar components were used in the SBM Display Board because most

engineers understand how they work and the components can be probed without

fear of damage from static discharge.

• The SBM Display Board allows users to probe inside the circuit during read and

write operations and to swap components to study the circuit’s operating

envelope.


• Some of the components on the

board are leaded and placed in

through-holes to allow easy

removal.

• Five probe attach points are

positioned on the board to

allow oscilloscope connections.

Always use 10M input

impedance so as not to disturb

board operation.

SBM Display Board

4.5V version of the SBM Display Board


Ferroelectric Capacitor The key to understanding stand-alone non-volatile memory using a

ferroelectric capacitor is its hysteresis loop.

Vout

How does it act in a

circuit with a resistor?

-50

-40

-30

-20

-10

0

10

20

30

40

50

-4 -3 -2 -1 0 1 2 3 4

Po

lari

za

tio

n (

µC

/cm

2)

Vo ltage

DOWN

Memory State

Up Memory

State


Switching vs Non-Switching

0

10

20

30

40

50

60

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

nC

Vo l ts

Half Lo o p UP: Po lar izat io n (µC/cm2)

Half Lo o p DOWN: Po lar izat io n (µC/c m2)

The single loop in the previous slide went full circle starting from the

DOWN state. The plot below shows what happens if half-loops are

executed from the DOWN state and the UP state.

The two half loops in this

graph create the two traces

on the next slide that occur

when a resistor is put in

series with the ferroelectric

capacitor. The colors match

the states.

DOWN

UP


0

1

2

3

4

5

6

7

8

9

1 0

0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0

RC

V

ou

t

T i m e ( m s )

R C A B 4 0 1 1 5 M o h m 9 V R C A B 4 0 1 1 5 M o h m 9 V

A Real RCFE

C = 400 µm2 2600Å-thick 20/80 PZT

R = 15M

Measured

Defined as the “Shelf Voltage”.

DOWN

UP


Both circuits with and without a transistor have exactly the same shape to

their response.

The transistor added to the circuit on the right makes its circuit slower

than the RCFE circuit without the transistor on the left.

This characteristic is true for whatever technology is used for T1 as long

as the conductivity of T1 is controlled by the current or voltage on its

input.

Vout

Vpwr Vpwr

CFE

T1

Vout

Add a Transistor


What does the Transistor Do? First apply equal Vpwr to both circuits. Stop time for each circuit at the same Vout .

Then:

1) Current through the Resistor of both circuits will be the same.

a) I = (Vpwr-Vout)/R

2) All of the current in the RCFE circuit goes into the capacitor.

3) Most of the current in the transistor circuit goes through the transistor.

Much less goes through the capacitor.

The ferroelectric

capacitor in the

transistor circuit

must charge more

slowly!

R

Vout Vout = Vout

Vpwr = Vpwr Vpwr

CFE

T1

Vout

Vpwr

R


0

1

2

3

4

5

6

7

8

9

0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 6 . 0 6 . 5 7 . 0

RC

X

Vo

ut

T i m e ( m s )


R C X A B 4 0 1 1 5 M o h m 9 V R C X A B 4 0 1 1 5 M o h m 9 V

RCFE vs RCFEX C = 400 µm2 2600Å-thick 20/80 PZT

R = 15M

β = 2

Measured Blue dashed = RCFE. Red solid = RCFE with transistor.

Vthreshold for the transistor causes this gap.

)1()1( FERCgain

t

eVpwrVout

(1+β) = 3


Autonomous Latch

The Autonomous Latch combines the Resistor/FeCap/Transistor circuit with an

additional feedback transistor to latch the circuit one way or the other when Vpwr

is applied.

Only Vpwr controls the read operation. There are no clocks or control lines to the

memory circuit.

CFE

T1

Vpwr

Input

T2

RSense

A

Input Enable

Output

RB

RB


Autonomous Latch Write

If T1 is on, then T2 must be on which forces T1 on. Output is low.

If T1 is off, T2 is off which forces T1 off. Output is high.

If Input Enable is actuated, Input forces T1 to be on or off, setting the state which remains

after Input is disabled until 1) power is removed or 2) Input is enabled to set a new state.

CFE

T1

Vpwr

Input

T2

RSense

A

Input Enable

Output

RB

RB


Autonomous Latch Read

CFE, Rsense, and the rate at which Vpwr rises are set such that if CFE is UP and does not

switch, not enough current flows through the base-emitter circuit of T1 to turn it on. T1/T2

remain off.

If CFE switches, much more current flows through the base-emitter of T1, causing it to turn

on which then forces T2 to turn on. T1/T2 form a half-latch that remains on.

CFE

T1

Vpwr

Input

T2

RSense

A

Input Enable

Output

RB

RB

The state of CFE is read

every time Vpwr is

applied to the circuit. As

Vpwr rises, all of the

charge from CFE must

pass through the base-

emitter circuit of T1.


Sense Capacitor

If a CSense is added to the bottom of the CFE, it captures all of the ferroelectric charge and

generates a voltage on the base-emitter circuit of T1. T1 cannot turn on until that voltage

passes the transistor VThreshold.

CSense is sized so that non-switching ferroelectric charge across CSense cannot turn on T1 but

switching ferroelectric charge can.

CFE

T1

Vpwr

Input

T2

CSense

RSense

A

Input Enable

Output

RB

RB

If Vsense < 0.7V, T1 remains off. T2 remains off. Output Vpwr If Vsense 0.7V, T1 turns on. The base-emitter circuit of T2 is pulled low. T2 turns on, latching T1 on . Output ground.


No Floating Nodes

If T1/T2 are on, the base-emitter circuit of T1 is actively driven.

If T1/T2 are both off, the base-emitter circuit of T1 floats.

RD is added to force that node to ground if T1/T2 are off to prevent disturbs.

CFE

T1

Vpwr

Input

T2

CSense

RSense

A

Input Enable

Output

RB

RB

RD


Automatic Rewrite Operation

Once the latch has been forced into the desired state, CFE will automatically be rewritten into

the proper direction UP or DOWN so that when Vpwr is removed and reapplied later, the

latch will come up into its last assigned state!

HIGH

T1 and T2 are OFF!

CFE is held UP by the latch!

CFE

T1

Vpwr

Input

T2

CSense

RSense

A

Input Enable

RB

RB

RD


Automatic Rewrite Operation

T1 and T2 are ON!

CFE is held DOWN by the latch!

LOW CFE

T1

Vpwr

Input

T2

CSense

RSense

A

Input Enable

RB

RB

RD

For the DOWN state, the ferroelectric capacitor is re-written through T1!


Latch Summary The latching autonomous memory circuit:

a) Will read the memory state of its ferroelectric

capacitor when the circuit powers up.

b) Will automatically re-write the original ferroelectric

capacitor memory state.

c) Will allow a new state to be set by an external input

and will force the ferroelectric capacitor to memorize

the new state.

d) Will retain the memorized state without power.


Failure Modes

Failures can occur during the four phases of memory operation

Failure during read on power-up.

Disturb while powered.

Unintended write during power-down.

Disturbs during un-powered retention.


Read Failure

Three failures can occur during power up.

Partial power

- Power is interrupted during power up so the capacitor is

partially read or the re-write is not complete. Wrong datum is

now stored.

Power ramps too fast.

- Circuit always latches low.

Power ramps too slow.

- Circuit always latches high.


Read Failure Power Quality

• If, during power-up, Vpwr only rises part of the way to the design value

for the circuit, CFE might be partially switched but not enough to latch

the circuit. This failure can occur only when the capacitor is DOWN. It

has no effect if the ferroelectric capacitor is UP.

• If, during power-up, Vpwr suddenly fails before the CFE is re-written,

the wrong datum will be stored in CFE. This failure can only occur to

the DOWN state. The re-write is driven through two transistors so it is

very fast. The time window for failure is extremely narrow.

• If, during power-up, Vpwr rises far above the designated value for the

circuit, it may drag the low state of CSense higher than VThreshold for T1

according to the series-capacitor voltage-divider equation, latching a

DOWN state. This failure can only occur to the UP state.


Power Quality - Solution

• The power to the autonomous latch must meet the following conditions:

Power is applied to the autonomous latch only once it reaches the

necessary level to fully power the latch.

Power is clamped to a value no higher than the specified operating

voltage for the latch.

Power is only applied to the latch when it is guaranteed not to turn

off before the DOWN state has been re-written.

- An energy storage device may be charged from power and used to

power-up the latch.


Read Failure Power Ramp Rate Too Fast

• Powering up in the UP state, CFE should generate only a small amount

of charge across RSense. This should latch a High state on the circuit

Output.

• If Vpwr rises too fast during power-up, the current draw of a non-

switching CFE state through Rsense becomes high enough to cause a

voltage drop across Rsense and trip T2. T2 trips T1 and the circuit

mistakenly latches its Output Low (DOWN state).


Power Ramp Rate Too Fast - Solution

• Slow down the ramp-rate of Vpwr during power up.

OR

• Decrease the value of Rsense.

Ferroelectric capacitors are very fast. The autonomous memory circuit

can be tuned to operate at any speed by adjusting the Vpwr ramp rate

compared to the value of RSense..

-Slower ramp rate means higher value of Rsense and less power

consumption by the circuit in the Low Output state.


Read Failure Power Ramp Rate Too Slow

• RD discharges the sense node between CFE and CSense to prevent that

node from floating if T1/T2 are off.

• RD will discharge CSense if CSense has a voltage across it.

• If Vpwr rises too slow, RD will discharge CSense faster than CFE can

deliver charge to the sense capacitor so Vthreshold is never reached before

Vpwr settles at its maximum value.

• The circuit will always latch UP even if CFE was originally in the

switching state (DOWN).


Power Ramp Rate Too Slow - Solution

• Vpwr must rise fast enough that the rate at which RD discharges CSense

does not interfere with the generation of the proper Vsense on the control

node of T1.

OR

• RD is increased to slow its discharge rate

OR

• RD is replaced by a time-delay latch.

Note that CSense counts individual electrons coming from CFE and can be

overpowered by any active device put in place of RD. Only passive

devices can replace RD.. Active devices must be on a time delay.


Failure while Powered

Two failures can occur while the circuit is powered.

Too large of an electrical load on Output.

A glitch on Input Enable connects the Input to the base-emitter

circuit of T1, causing an unintended write to CFE.


Failure while Powered Driving a Load

• Too large of an electrical load on Output while it is High (UP) can cause

enough voltage drop across Rsense.

• If the voltage drop across Rsense gets large enough, T2 can be triggered,

causing the circuit to latch with the Output low and writing that new

state into CFE.


Driving a Load - Solution

• Always put a buffer on the Output of the autonomous latch having a

high input impedance but capable of driving heavy loads.

Or

• Replace Rsense with a complex circuit that performs the same sensing

function during power up but can drive heavy loads.


Failure while Powered Input Glitch

• A glitch on Input Enable can connect the Input node to the sense node

of T1 between CFE and CSense, causing an unintended write operation.

• Ferroelectric capacitors are extremely fast, more than likely faster than

the circuits controlling the autonomous latch, so even the shortest glitch

on the Input can change the stored state of the latch.


Input Glitch - Solution

• Ensure that there are no glitches or unintended transitory voltages on

Input Enable

AND

• Tie Input Enable to ground with a resistor to prevent inductive voltage

spikes during power up from connecting the Input to the sense node of

the latch until the logic states of external circuits are stable.

Or

• Use combinatorial signals to Enable the Input so that a single signal

cannot do it alone with a single glitch.


Failure during Power-Down

One failure can occur during power.

When power to the autonomous latch decreases towards ground

during power-down, a UP state could be inadvertently written to a

stored DOWN state. This failure mode cannot happen the other

way.


Failure during Power-Down Unintended Re-write

• When power to the autonomous latch decreases towards ground during

power-down, T2 will eventually turn off causing T1 to turn off.

• In the DOWN state, Output should be low but when T1 and T2 turn off,

Output can jump to the value remaining on Vpwr. This voltage is

trapped on Output because all discharge paths to ground from CTimer are

turned off.

• The partial voltage on the Output, if high enough, will switch the

ferroelectric capacitor UP or partially UP, re-writing a new state in CFE

if the stored state is a DOWN.


Unintended Re-write - Solution

• For a bipolar circuit such as in the SBM Display board, both RB values

must be set so that T2 does not turn off until Vpwr reaches a voltage

below the switching voltage for the ferroelectric capacitor being used.

The value 0.8 volts will work for the hysteresis loop below.

-50

-40

-30

-20

-10

0

10

20

30

40

50

-4 -3 -2 -1 0 1 2 3 4

Po

lari

za

tio

n (

µC

/cm

2)

Vo ltage

Input

Input Enable

CFE

T1

Vpwr

T2

CSense

RSense

A

RB

RB

RD



• If the unlatch voltage is set correctly and Vpwr glitches low but not

below the unlatch voltage, the data state of the latch remains

undisturbed until Vpwr returns.

• If Vpwr glitches below the unlatch voltage, a new and valid read

operation will take place as Vpwr comes back up.

Input

Input Enable

CFE

T1

Vpwr

T2

CSense

RSense

A

RB

RB

RD



• If FET circuits are used, the Vth of the FETs must be chosen to set the

unlatch voltage.

CFE

T1

Vpwr

T2

CSense

RSense

A

RB

RD



• A resistor across CTime will discharge

Ctime in a known period of time to

discharge the Output node if it

develops trapped charge.

• If a voltage regulator is chosen to

provide Vpwr, part of its function

should be to discharge its regulated

voltage node in an orderly manner

when power is removed.

For instance, the TI REG103-5 LDO

voltage regulator automatically performs

this function in 70µs. It is called a “soft”

power-down.

RRamp

Vpwr

Vsystem

Ramp Generator

CTime

ROff


Failure during Power-Off Retention Three failures can occur while power is off and the ferroelectric capacitor

is retaining a datum.

A static discharge or other charge source is applied across the

ferroelectric capacitor in the proper direction to change its state.

• The retention is so long that the capacitor imprints. Retention is

not affected and the proper value will be read on the next power

cycle. However, an imprinted capacitor cannot be changed to the

opposite state during a normal write operation.

• Cycling fatigue causes the memory signal to become weak enough

for errors to occur during read operation.

Fatigue and Imprint form a separate category called Capacitor

Reliability. They are discussed separately later in this document.


Static Discharge - Solution

A static discharge or other charge source is applied across the ferroelectric

capacitor in the proper direction to change its state.

Static discharge consists of an electrical charge accumulated on

some item which touches the capacitor.

The energy of the static charge is very low. It is calculated by

multiplying the voltage across the static charge times the amount of

stored charge.

The energy to switch the ferroelectric capacitor must be much

larger than the accumulated anticipated static discharge events.

- Ferroelectric switching energy is its remanent polarization

times its saturation voltage.


Sensitivities The following slides will examine different components in the

autonomous memory circuit of the SBM Display Board and discuss how

to set their values. The first two subjects are the latch itself and its source

of power.

CFE

T1

Vpwr

T2

CSense

RSense

A

RB

RB

RD

RRamp

Vpwr

Vsystem

Ramp Generator

CTime


Ramp Generator The ramp generator circuit on the SBM Display Board consists of a PNP transistor

where the load resistor Rramp in its base-emitter circuit controls a larger current

flow into a timing capacitor and the latch itself.

The equations are:

RRamp

Vpwr

Vsystem

Ramp Generator

CTime

Isupply = [ VSystem - 0.7Vpn – Vzener ] / Rramp

Ramp = dV/dt = ISupply / Ctime

DZener prevents the PNP transistor from

turning on until VSystem has reached an

acceptable level.

DZener


Ramp Generator A simple ramp generator circuit can be used with the SBM Display Board without

error because system power originates from a battery with a push button. It has

fast clean turn-on and turn-off performance. The Zener diode in the ramp

generator turns on sharply with increasing voltage but does not ever fully turn off

with decreasing voltage. Because of the characteristics of Zener diodes, this

circuit can be fooled by glitchy power.

RRamp

Vpwr

Vsystem

Ramp Generator

CTime

If power is glitchy, you must use a more

complex voltage regulator circuit with

voltage threshold detection to ensure power

is good before applying Vpwr.

Contact Radiant for a more detailed

discussion. By adding the appropriate power

protection circuitry, the autonomous bit can

be made bullet proof.

DZener


Ramp Generator A simple ramp generator circuit can be used with the SBM Display Board without

error because system power originates from a battery with a push button. It has

fast clean turn-on and turn-off performance. The Zener diode in the ramp

generator turns on sharply with increasing voltage but does not ever fully turn off

with decreasing voltage. Because of this characteristic of Zener diodes, the simple

ramp generator circuit can be fooled by glitchy power.

RRamp

Vpwr

Vsystem

Ramp Generator

CTime

DZener


External Power

The SBM Display Board can be operated from

an external power supply by removing the

batteries and connecting the external power

supply across the PWR and GND probe posts on

the board.

If you do this, you must supply the proper

power ramp and power discharge.

Bench-top power supplies are glitchy. Using

them for power, you must use a more complex

voltage regulator circuit than the simply ramp

generator. You must provide voltage threshold

detection to ensure power is good before

applying Vpwr.

By adding the appropriate power protection

circuitry, the autonomous bit can be made bullet

proof. Contact Radiant for a more detailed

discussion.


Ramp Rate • Rsense combined with CFE establishes an RC time constant for charging

the ferroelectric capacitor to Vpwr. There are two time constants.

Non-switching

Switching.

0

1

2

3

4

5

6

7

8

9

1 0

0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0

RC

V

ou

t

T i m e ( m s )


Switching RC

time constant

Non-switching

RC time constant


Ramp Rate • During power-up, there are only two conditions that set the latch state:

No voltage develops across Rsense and T2 remains off.

Voltage develops across Rsense and T2 turns on.

Input

Input Enable

CFE

T1

Vpwr

T2

CSense

RSense

A

RB

RB

RD

• Given the two RC time

constants for the two

memory states, there are

four possible categories

for the Vpwr ramp rate:


Ramp Rate • Too fast for the non-switching RC time constant: a voltage develops

across Rsense even for the UP state (non-switching) and T2 turns on,

forcing CFE DOWN and putting out the wrong state (Low).

• Slower than RCnSW but faster than RCSW: direct read of the

ferroelectric capacitor state takes place but the value of CSense does

not matter.

• Slower than both RC time constants so both generate tiny voltage

drops across RSense: The charge generated in CSense determines the

voltage on the base-emitter circuit of T1. If T1 turns on, it causes the

voltage drop across Rsense that latches the circuit Low.

• Too slow for the switching RC time constant: no voltage ever

develops across Rsense, T2 never turns on, and the circuit always

outputs a high state (UP).


Ramp Rate • It is best to have the ramp rate slower than both RC time constants so

CSense can be adjusted to set the detection threshold.

• It is also possible to eliminate CSense and use the RD resistor to detect

the capacitor state as in the FET circuit below.

CFE

T1

Vpwr

T2

RD

RSense

A

RB

• For this circuit to work,

the ramp rate must be tied

to RD but Rsense must be

small enough to disappear

from the circuit timing.


Ramp Rate

• Despite these rules governing the Vpwr ramp rate, there is a wide

window of ramp rates possible for a given set of loads and capacitor

sizes in an autonomous memory, usually more than several orders of

magnitude in time.

• Component values can be chosen to achieve microsecond read times.

• Component values can be chosen to achieve second read times.

• The read time range affects power consumption and capacitor size

and the opportunity for a disturbance during power-up.


FE Capacitor Area • The SBM Display Board is sized to work with ferroelectric PZT

capacitors having an area of 10,000 square microns.

Type AB 0.25µm-thick 20/80 PZT to operate up to 9 volts.

Type AD 0.15µm-thick 3/20/80 PNZT to operate at 4.2 volts.

The state of a 10,000 square micron ferroelectric capacitor cannot be

changed by static discharge that meets the industry standard model.It

requires too much charge to switch.

To make a faster memory using less power, make CFE smaller.

To make a memory that cannot be disturbed by large disturbance

events, use a larger capacitor and run the memory slower.


Memory Speed • The SBM Display Board rise time is ~12 microseconds.

• To go faster,

Make CFE smaller.

Decrease RRamp and/or CRamp.

Decrease CSense in proportion to the reduction in CFE.

Possibly decrease Rsense.

• To go slower,

Make CFE larger.

Increase RRamp and/or CRamp.

Increase CSense in proportion to the increase in CFE.

Possibly increase Rsense.


Memory Speed

The modifications listed on the previous page can be done

individually or together. For instance, memory circuits with

small ferroelectric capacitors can be run slow! Circuits with

large ferroelectric capacitors can be run fast but eventually

run into power consumption, current, or Rsense limits.


Input Loading • The SBM Display Board uses push buttons to program the latch.

• The push buttons can overwhelm the PNP T2 when it is on to pull the

sense node to ground.

Input

Input Enable

CFE

T1

Vpwr

T2

CSense

RSense

A

RB

RB

RD

RInput

• To reduce the power

consumption required of the

input driver when T2 is on,

add RInput.

• Size RInput to share value

with RB for T1 and to limit

power consumption during a

write operation.

Sense Node


Output Loading • The output load of the memory circuit pulls current through Rsense.

• It the load pulls too much current with Output High, it can

inadvertently turn on T2 changing the latch to output Low.

Input

Input Enable

CFE

T1

Vpwr

T2

CSense

RSense

A

RB

RB

RD

RInput

• Either

Set the output load so it

can never trip T2

OR

Put a high-input

impedance buffer

between the memory

Output and the load.

The display on the SBM Display Board offers

at worst a 50k load when Output is high.


Vpwr • Rsense, CFE, and CSense form a voltage divider and the

voltage on the sense node between CFE and CSense

will turn on T1 if high enough.

• If Vpwr settles higher than the design voltage, the

voltage on CSense will rise above the Vthreshold of T1 no

matter the memory state of CFE. The Output in that

case will always go low.

• CSense must always be sized so that the non-switching

charge at a given Vpwr cannot turn on T1.

• The Type AD capacitor from the 4.8V version of the

SBM Display Board will not work in the 9.0V

version for this reason unless CSense is changed.

CFE

T1

Vpwr

CSense

RSense

A

RB


Capacitor Reliability • Reliability for an autonomous memory circuit refers to how long the memory

will operate without making a mistake as a function of

Environment

Temperature

Number of read and write cycles.

• It is possible to construct PZT-based ferroelectric capacitors that will retain

their memory for hundreds of years at 150C, never wear out from reads or

writes, and absorb space level radiation events while still functioning correctly.

The controlling factor is the price you are willing to pay for the capacitor.

• Radiant’s Type AB and Type AD capacitors use platinum electrodes. PZT

capacitors with platinum electrodes have a more limited reliability envelope:

500,000 read and write operations (one every 33 minutes for 30 years) plus 30

years imprint at 85C.

• Radiant can construct PZT capacitors with no fatigue or imprint.


Reliability Definitions • Fatigue: The property of some ferroelectric capacitors whereby they lose some

fraction of their remanent polarization every time they are cycled once. After

enough cycles, the signal is too small to read correctly.

• Fatigue, if it occurs, progresses by cycle no matter how long the period of the

cycle or how fast or slow the cycles occur.

• Fatigue is a function of the combination of the electrode material and the

ferroelectric composition. PZT does not fatigue with some oxide electrodes.

• Fatigue is independent of temperature from room temperature to 150C.

• In autonomous memory, a fatigued capacitor always fails UP.

The Radiant fatigue reliability specification for one of its capacitors is the number

of cycles of a ferroelectric capacitor at which its switching polarization has

decreased to 50% of the gap between the virgin Switched and virgin Unswitched

charges.


Reliability Definitions

• Imprint: The property of a ferroelectric capacitor to shift left or right on its

hysteresis plot with time in a single state.

• When the capacitor hysteresis shifts along the horizontal axis a magnitude equal

to its coercive voltage, the datum in the memory cannot be changed by the

circuit. The last value stored is imprinted. Data is never lost in a ferroelectric

memory. It just eventually does not want to change. This is the opposite of

retention loss.

• Imprint is accelerated by elevated temperature.

• Imprint is a function of the combination of the electrode material and the

ferroelectric composition. PZT does not imprint with some oxide electrodes.


Reliability Specifications

• In general, the remanent polarization state of a ferroelectric capacitor is forever,

at least as long as you and I will live. The capacitors do not discharge or lose

their polarization state. They do not suffer retention loss. They only imprint

after enough time or they cease to be useful if fatigued to a low signal level.

• The recommended operating voltages for Radiant’s capacitors in autonomous

memory circuits are twice their saturation voltage s at room temperature. They

can only fail if the imprint offset voltage grows to equal the value of their

coercive voltage. Using Radiant’s recommended operating voltages, they

cannot fail due to imprint within the imprint specification period.

The Radiant imprint reliability specification for one of its capacitors is the time to

the point where a datum that was written only once into a virgin capacitor cannot

be rewritten to the opposite state at the maximum opertaing temperature.


Optimal Design

• The optimal design for an autonomous memory to provide the longest imprint

lifetime is to select CSense such that charge exactly half-way between the UP and

DOWN states of a virgin capacitor will trigger T1.

• To favor fatigue resistance over imprint resistance, decrease the value of Csense

from the optimal.

• If the CFE does not fatigue or imprint for the intended lifetime of the circuit, use

the 50% rule to provide the largest noise margin and disturbance rejection

during the read operation.


Capacitor Specification • Below are the capacitor parameters that Radiant considers a

specification.

Recommended operating voltage.

The switching (DOWN) and non-switching (UP) charge the

capacitor will generate: this determines the size of CSense and RSense.

The operating temperature range of the specification.

The fatigue limit of the capacitor at the operating temperature.

The imprint time of the capacitor at the operating temperature.


Capacitor Specifications

Specification/Type AD AB

Operating Voltage 4.2 6.8

UP Charge 17µC/cm2 14µC/cm2

DOWN Charge 60µC/cm2 74µC/cm2

Operating Temperature RT 85C RT 85C

Fatigue Limit 500,000 500,000

Imprint Time 10 yrs 10 yrs

Capacitors areas available: 100µm2 10,000µm2

400µm2 40,000µm2

1000µm2 100,000µm2

4000µm2 1,000,000µm2 (1mm2)

Note: 1x108 µm2 = 1cm2


Closing

• Who would suspect that such a simple circuit as the SBM

Display Board with so few components could have such

complex behavior and remember for almost forever!

• It is possible to adjust the autonomous memory circuit on

the SBM Display Board to operate fast or slow, with larger

capacitors or with smaller capacitors, with batteries or with

an external power supply.

• Feel free to tear up your SBM Display Board with

experiments. We have more.

Autonomous Memory Operating Envelope · switch, not enough current flows through the base-emitter...

Documents

Transcript of Autonomous Memory Operating Envelope · switch, not enough current flows through the base-emitter...