12 July 2002 Imma RiuATLAS LArgon calorimeter: ROD Board status and plans 1

ATLAS Liquid Argon Calorimeter:Read Out Driver Board status and plans

• Outline:

– Introduction– The LArgon readout architecture– ROD system description– Status and plans– Conclusions

Imma RiuUniversité de GenèveRencontres de Bossey12 July 2002

12 July 2002 Imma RiuATLAS LArgon calorimeter: ROD Board status and plans 2

Introduction

ATLAS detector

• The ATLAS Liquid Argon calorimeter is divided into:– Barrel calorimeter (EMB)– Hadronic endcaps (HEC) – Electromagnetic endcaps

(EMEC)– Forward calorimeter (FCAL)

• In total, around 190 000 channels are to be read out.

12 July 2002 Imma RiuATLAS LArgon calorimeter: ROD Board status and plans 3

EM Endcap prototype

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The challenge of the electronics

• Large dynamic energy range: [50 MeV - 3TeV] 16 bits !

• The bunch crossing (BX) rate at LHC is 40 MHz (each 25 ns): For a signal of 600 ns, the pile-up takes up to 24 BXs.

• Required relative energy resolution: ~ 10% / E: Pile-up and electronic noise should be minimized. Good calibration of the electronics response.

Signal after shapingNoise dependence on

luminosity and peak time

Different BXs Detector

signal shape

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The LArgon Read Out Architecture

EM BarrelEMEC EMECHEC HEC FCALFCAL

1 23 45 56 6

FEBFEB

FEBFEB

FEBFEB

FEBFEB

FEBFEB

FEBFEB

FEBFEB

FEBFEB

FEBFEB

FEBFEB

RODROD

RODROD

RODROD

RODROD

RODROD

Detector:Radiation

environment

USA15:Radiation free

DAQ

Front End Boards

Read Out Driver Boards

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FEB and ROD boards functionality

FEBROD

optical fiber

1.6 Gbit/s ~100m

100 kHz event rate

• Radiation tolerant board.

• 128 channels / FEB.

• Fast signal shaping (~ 50 ns).

• Five digitized points (12 bits) using three gains in the ratio 1/10/100.

• Gain selection (2 bits).

• LArgon needs ~1600 FEBs.

Located in the detector Located in USA15room

• Event processing time 10s.

• Computation of time, energy and shape quality flag (2).

• Use of optimal filtering algorithm.

• Use of Digital Signal Processors (DSP).

• Generation of the ‘busy’ signal.

• LArgon needs ~200 RODs.

2i

5

1 ii

2

5

1 iii

5

1 iii

)gE Ped(Sχ

)PedS(b t E

)PedS(a E

FEBFEBFEBFEBFEBFEBFEB8

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ROD physical description

• ROD system:

– Input: 8 optical fibers with FEB raw data (16 bits @ 80 MHz)

– Output: 4 optical fibers with ROD calculations (32 bits @ 40 MHz)

– It consists of:

• 9U VME64x board: ROD module (14 RODs / crate at maximum)• 9U VME64x board: Transition Module

NevisLabs

• ROD module:– ROD mother board (MB)

• Uses G-link chips for deserializing the data from the optical fiber.

• Includes TTCrx ASIC which provides Trigger-Time-Control information: LHC clock, event and bunch crossing identifiers, ATLAS trigger type.

• Uses SDRAMs for storing raw data (for online histograms)

• Uses programmable chips (FPGA).

– 4 processing units (PU) mounted on top of the ROD mother board.• Include Digital Signal Processors (DSP) chips.

• 2 DSP / PU. [1 DSP per FEB]

• Use FPGA chips as well.

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Glink

Glink

Glink

Glink

Glink

Glink

Glink

Glink

stagingFPGA

stagingFPGA

stagingFPGA

stagingFPGA

ProcessingUnit

ProcessingUnit

ProcessingUnit

ProcessingUnit

OutputController

OutputController

OutputController

OutputController

VMEcontrol

receiver

receiver

receiver

receiver

receiver

receiver

receiver

Ser

Ser

Ser

Ser

receiver SDRAM

SDRAM

SDRAM

SDRAM

TTC

Read Out Driver Board

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InputFPGA

InputFPGA

DSP

DSP

OutputFPGA

FIFO

FIFO

VME

TTC

Processing Unit

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Glink

Glink

Glink

Glink

Glink

Glink

Glink

Glink

stagingFPGA

stagingFPGA

stagingFPGA

stagingFPGA

ProcessingUnit

ProcessingUnit

OutputController

OutputController

OutputController

OutputController

VMEcontrol

receiver

receiver

receiver

receiver

receiver

receiver

receiver

Ser

Ser

Ser

Ser

receiver SDRAM

SDRAM

SDRAM

SDRAM

TTC

ROD at the beginning of LHC

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Glink

Glink

Glink

Glink

Glink

Glink

Glink

Glink

stagingFPGA

stagingFPGA

stagingFPGA

stagingFPGA

receiver

receiver

receiver

receiver

receiver

receiver

receiver

receiver

ProcessingUnit

ProcessingUnit

ProcessingUnit

ProcessingUnit

OutputController

OutputController

OutputController

OutputController

VMEcontrol

Ser

Ser

Ser

Ser

SDRAM

SDRAM

SDRAM

SDRAM

TTC

Status of the ROD

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InputFPGA

InputFPGA

DSP

DSP

OutputFPGA

FIFO

FIFO

VME

TTC

Processing Unit

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Delicate points

• Cooling of G-link chips:– 35 ºC at maximum for 80 MHz clock frequency.– Cooling with water or air are being studied.

• For money saving, ‘staging’ is implemented:– Half of the PUs will be used at the beginning of LHC.– The DSP processes 128*2 channels.

• PCB routing with multiple ball-grid-array (bga) chips.

• The output goes through serializer/de-serializer at 280 MHz.

bga chip

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Past experience in Geneva

• Built in 2000.

• Board frequency: 40 MHz.

• 2 optical receivers as mezzanine in TM.

• 1 Output Slink in the Transition Module.

• 4 PUs: 1 DSP/PU, 64 channels/DSP .

• Used in Test Beams and for tests of PU.

• To be built in 2002.

• Parts of the board at 80 MHz.

• 8 optical links integrated in the ROD.

• 4 Outputs Slink in the TM.

• 4 PUs: 2 DSP/PU, 128 channels/DSP.

Need of four times less ROD modules.

• Sending of data serialized LVDS at 280 MHz to the TM. (test in Geneva ok)

• Addition of the staging FPGAs.

• Use of ball-grid-array chips.

ROD demonstratorROD demonstrator ROD prototypeROD prototype

Annie, Daniel, Ilias,

Lorenzo

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PU 1

PU 2

PU 3

PU 4

ROD Demo Transition Module

Input LinkReceiver

Input LinkReceiver

Output LinkTransmitter

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Plans and milestones

• Decision of the DSP chip: Done (DSP TI 6414)

• ROD preliminary design review: September 2002 (planned by Jan.

2002)

• Prototype production: Oct/Nov 2002

• Pre-series production: May 2003

• PRR (production readiness review) : Oct/Nov 2003 (planned by April

2003)

• Series production: January 2004

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Geneva ROD group

• Manpower:– Engineers:

• Daniel La Marra: engineer responsible of the ROD module

• Annie Leger– Physicists:

• Alain Blondel: project leader• Imma Riu: physicist responsible

• Present responsibility:– To finish the ROD mass production by 2004.

• Possible next steps:– Take part on the commissioning of the system.– Participate in the DAQ system for the RODs.

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Conclusions

• The ROD project is ongoing well in Geneva with the collaboration of LAPP and Nevis.

• The Geneva group is getting ready for the preliminary design review in September 2002: finishing schematics and writing documentation.

• The ROD mother board mass production is expected to be finished in 2004.