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Verilog HDLVerilog HDLVerilog HDLVerilog HDL

ASIC DESIGN USING FPGA

BEIT VII

KICSIT

Sep 6 2012 Lecture 6

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Hierarchical Design Hierarchical Design

Sep 6 2012 Lecture 6

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Structural Model (Gate Level)Structural Model (Gate Level)

Sep 6 2012

• Built-in gate primitives:•and, nand, nor, or, xor, xnor, buf, not•bufif0, bufif1, notif0, notif1 (with tristate Output)

•Usage:

nand n1(out, in1, in2);

2-input NAND without delay

Lecture 6

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Structural Model (Gate Level) Structural Model (Gate Level)

Sep 6 2012

and #2 u1(out, in1, in2, in3);

3-input AND with 2 t.u. delay

not #1 N1(out, in);

NOT with 1 t.u. delay and instance name

xor X1(out, in1, in2);

2-input XOR with instance name

• Write them inside module, outside procedures

Lecture 6

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Example: Half Adder Example: Half Adder

Sep 6 2012

•Assuming •XOR: 2 t.u delay• AND: 1 t.u delay

Lecture 6

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Example: Half Adder Example: Half Adder

Sep 6 2012

module half_adder(S, C, A, B);

output S, C;

input A, B;

wire S, C;

xor #2 u1(S, A, B);

and #1 u2(C, A, B);

endmodule

Lecture 6

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Continuous Assignements (Data flow)Continuous Assignements (Data flow)

Sep 6 2012

• Syntax:

assign #del <id> = <expr>;• Where to write them:

• inside a module• outside procedures

• Properties:• they all execute in parallel

• are order independent• are continuously active

Lecture 6

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Example: Half AdderExample: Half Adder

Sep 6 2012 Lecture 6

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Module Ports Module Ports

Sep 6 2012

• Similar to pins on a chip

• Provide a way to communicate with outside world.

• Ports can be input, output or inout

Lecture 6

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Port Assignments Port Assignments

Sep 6 2012 Lecture 6

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Connecting Ports to External Signals Connecting Ports to External Signals

Sep 6 2012

There are two methods of making connections b/w signals specified in the module instantiation and the ports in a module definition.

• Connecting by ordered list

The signals to be connected must appear in the module instantiation in the same order as the ports in the port list in the module definition.

Lecture 6

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Connecting Ports to External Signals Connecting Ports to External Signals

Sep 6 2012

Example:

module Top;

fulladder fa_ordered(SUM, C_OUT, A, B, C_IN);

endmodule • Connecting ports by name

Here you can specify the port connections in any order as long as the port name in the module definition correctly matches the external signal.Lecture 6

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Connecting Ports to External Signals Connecting Ports to External Signals

Sep 6 2012

Example:module Top;

fulladder fa_byname(.c_out (C_OUT),

.sum (SUM),

.in2 (B),

.c_in (C_IN),

.in1 (A) );

endmodule Lecture 6

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Example: Full Adder Example: Full Adder

Sep 6 2012 Lecture 6

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Example: Full Adder Example: Full Adder

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module full_adder(sum, cout, in1, in2, cin);

output sum, cout;

input in1, in2, cin;

wire sum, cout, in1, in2, cin;

wire I1, I2, I3;

half_adder ha1(I1, I2, in1, in2);

half_adder ha2(sum, I3, I1, cin);

assign cout = I2 | I3;

endmoduleLecture 6

Example: Full Adder (Connecting ports by order) Example: Full Adder (Connecting ports by order)

17Sep 6 2012

module full_adder(sum, cout, in1, in2, cin);

output sum, cout;

input in1, in2, cin;

wire sum, cout, in1, in2, cin, I1, I2, I3;

half_adder ha1(S. (I1),

C. (I2),

A. (in1),

B. (in2));

half_adder ha2(A. (I1),

B. (cin),

S. (sum),

C. (I3));

assign cout = I2 | I3;

endmoduleLecture 6

Example: Full Adder (Connecting ports by name) Example: Full Adder (Connecting ports by name)

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2-Bit Full Adder Schematic View2-Bit Full Adder Schematic View