ASP-DAC 95 Table of Contents - CECSpapers/compendium94-03/papers/1995/...Table of Contents Advisory...
Transcript of ASP-DAC 95 Table of Contents - CECSpapers/compendium94-03/papers/1995/...Table of Contents Advisory...
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Table of Contents
Advisory BoardSteering Committee, Organizing CommitteeGeneral Chair’s MessageASP-DAC ‘95 Program CommitteeASP-DAC ‘95 Program Committee Chair’s MessageASP-DAC ‘95 Bst Paper CandidatesKeynote Address I - Atusushi AsadaKeynote Address II - Jim MeadlockKeynote Address III - John Darringer
Session A-1ADesign Methodologies for Low Power
Chair: Massoud PedramCo-Chair: Hidetoshi Onodera
A-1A.1 Transistor Reordering Rules for Power Reduction in CMOS GatesWen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang....................................................................1
A-1A.2 Power Reduction by Gate Sizing with Path-Oriented Slack CalculationHow-Rern Lin, TingTing Hwang..............................................................................................7
A-1A.3 Current and Charge Estimation in CMOS CircuitsSanjay Dhar, Dave J. Gurney.................................................................................................13
Session A-1BDesign Methodology for Processor and Telecommunication Systems
Chair: Winfried HahnCo-Chair: Yoshio Takamine
A-1B.1 Auriga2: A 4.7 Million-Transistor CISC MicroprocessorJ.P. Tual, M. Thill, C. Bernard, H.N. Nguyen, F. Mottini, M. Moreau, P. Vallet................19
A-1B.2 Automatic Design for Bit-Serial MSPA ArchitectureHiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito It........................................................27
A-1B.3 Stoht --- An SDL-to-Hardware TranslatorIvanil S. Bonatti, Renato J.O. Figueiredo...........................................................................33
A-1B.4 Enhancing a VHDL Based Design Methodology with Application Specific Data AbstractionLars Lindqvist........................................................................................................................37
Session A-1CPANEL: Design Automation 2000---Challenges for Gigabit-Era.................41
Moderator: Richard K. WallacePanelists: Joseph B. Costello, Jeffrey H. Edson, Aart J. deGeus, Alan J. Hanover, Jinya Katsube,Walden C. Rhines
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Session A-2AHigh Level Synthesis (1)
Chair: Daniel D. GajskiCo-Chair: Tadatoshi Ishii
A-2A.1 A Scheduling Algorithm for Synthesis of Bus-Partitioned ArchitecturesVasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru..............................................43
A-2A.2 Reclocking for High-Level SynthesisPradip Jha, Sri Parameswaran, Nikil Dutt...........................................................................49
A-2A.3 Synthesis of False Loop Free CircuitsShih Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang.............................................55
A-2A.4 High-Level Synthesis Scheduling and Allocation Using Genetic AlgorithmsM.J.M. Heijligers, L.J.M. Cluitmans, J.A.G. Jess...............................................................61
Session A-2BDesign Abstractions and Environments
Chair: Graham R. HellestrandCo-Chair: Masatoshi Sekine
A-2B.1 A Framework for the Analysis and Design of Algorithms for a Class of VLSI-CADOptimization Problems
C.-J. Shi, J.A. Brzozowski.....................................................................................................67A-2B.2 Generic Fuzzy Logic CAD Development Tool
Eric Q. Kang, Eugene Shragowitz........................................................................................75A-2B.3 A Hardware/Software Codesign Method for Pipelined Instruction Set Processor Using
Adaptive DatabaseNguyen Ngoc Binh, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi...........................81
A-2B.4 EMPAR: An Interactive Synthesis Environment for Hardware EmulationsTsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu................................................................87
Session A-2CSPECIAL SESSION: System-Level Design Automation Activities in Korea (1)
Chair: Chong-Min Kyung, KAIST, KoreaA-2C.1 A Scheduling Algorithm for Multiport Memory Minimization in Datapath Synthesis
Hae-Dong Lee, Sun-Young Hwang......................................................................................93A-2C.2 An Integrated Hardware-Software Cosimulation Environment for Heterogeneous Systems
PrototypingYongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, KiyoungChoi, Soonhoi Ha..............................................................................................................101
A-2C.3 A CSIC Implementation with POCSAG Decoder and Microcontroller for PagingApplications
J.Y. Lim, G. Kim, J.H. Cho, I.S. O, Y.J. Kim, H.Y. Kim...................................................107A-2C.4 Performance-Driven Circuit Partitioning for Prototyping by Using Multiple FPGA Chips
Chunghee Kim, Hyunchul Shin, Younguk Yu...................................................................113
Session A-3APartition and Floorplan
Chair: Chung-Kuan ChengCo-Chair: Kazuhiro Ueda
A-3A.1 A New System Partitioning Method under Performance and Physical Constraints forMulti-Chip Modules
Yoshinori Katsura, Tetsushi Koide, Shin’ichi Wakabayashi, Noriyoshi Yoshida............119
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A-3A.2 A Robust Min-Cut Improvement Algorithm Based on Dynamic Look-Ahead WeightingKatsunori Tani......................................................................................................................127
A-3A.3 Timing Influenced General-Cell Genetic FloorplannerSadiq M. Sait, Habib Youssef, Shahid Tanvir, M.S.T. Benten............................................135
Session A-3BEmbedded System Design
Chair: Akihiko YamadaCo-Chair: Jun Sato
A-3B.1 Power Analysis of a 32-bit Embedded MicrocontrollerVivek Tiwari, Mike Tien-Chien Lee..................................................................................141
A-3B.2 Assessing the Feasibility of Interface Designs before their ImplementationMarco A. Escalante, Nikitas J. Dimopoulos.....................................................................149
A-3B.3 A Hardware-Software Co-simulator for Embedded System Design and DebuggingA. Ghosh, M. Bershteyn, R. Casley, C. Chien, A. Jain, M. Lipsie, D. Tarrodaychik, O.Yamamoto............................................................................................................................155
Session A-3CSPECIAL SESSION: System-Level Design Automation Activities in Korea (2)
Chair: Chong-Min KyungA-3C.1 Integrated Interconnect Circuit Modeling for VLSI Design
Won-Young Jung, Ghun-Up Cha, Young-Bae Kim, Jun-Ho Baek, Choon-Kyung Kim...165A-3C.2 Architectural Simulation for a Programmable DSP Chip Set
Jong Tae Lee, Jaemin Kim, Jae Cheol Son.....................................................................171A-3C.3 System-Level Verification of CDMA Modem ASIC
GyeongLyong Park, KyungHi Chang, Jaeseok Kim, Kyungsoo Kim..............................177A-3C.4 A Digital Audio Signal Processor for Cellular Phone Application
Jeongsik Yang, Chanhong Park, Beomsup Kim..............................................................183
Session A-4ARouting
Chair: Jason CongCo-Chair: Takashi Mitsuhashi
A-4A.1 Region Definition and Ordering Assignment with the Minimization of the Number ofSwitchboxes
Jin-Tai Yan.....................................................................................................................189A-4A.2 A Three-Layer over-the-Cell Multi-Channel Routing Method for a New Cell Model
Masahiro Tsuchiya, Tetsushi Koide, Shin’ichi Wakabayashi, Noriyoshi Yoshida........195A-4A.3 Pin Assignment and Routing on a Single-Layer Pin Grid Array
Man-Fai Yu, Wayne Wei-Ming Dai..............................................................................203
Session A-4BDesign for Testability
Chair: Yervant ZorianCo-Chair: Kiyoshi Furuya
A-4B.1 Design for Testability Using Register-Transfer Level Partial Scan SelectionAkira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai,Michihiro Matsumoto, Michiaki Muraoka.....................................................................209
A-4B.2 A Built-In Self Test Scheme for VLSIT. Raju Damarla, Wei Su, Moon J. Chung, Charles E. Stroud, Gerald T. Michael......217
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A-4B.3 BIST with Negligible Aliasing through Random Cover CircuitsT. Bogue, H. Jürgensen, M. Gössel..........................................................................................223
Session A-4CLogic Synthesis of Sequential Circuits
Chair: Sunil D. SherlekarCo-Chair: Ryuichi Takahashi
A-4C.1 Implicit Prime Compatible Generation for Minimizing Incompletely Specified Finite StateMachines
Hiroyuki Higuchi, Yusuke Matsunaga......................................................................................229A-4C.2 Logic Optimization by an Improved Sequential Redundancy Addition and Removal
TechniqueUwe Gläser, Kwang-Ting Cheng..............................................................................................235
A-4C.3 On Hazard-Free Implementation of Speed-Independent CircuitsAlex Kondratyev, Michael Kishinevsky, Alex Yakovlev...........................................................241
Session A-5ATechnology-Driven Physical Synthesis
Chair: Hon-Wai LeongCo-Chair: Shin’ichi Wakabayashi
A-5A.1 Extending Pitchmatching Algorithms to Layouts with Multiple Grid ConstraintsHiroshi Miyashita...................................................................................................................249
A-5A.2 A New Layout Synthesis for Leaf Cell DesignMasahiro Fukui, Noriko Shinomiya, Toshiro Akino...............................................................259
A-5A.3 A Layout Approach to Monolithic Microwave ICAkira Nagao, Isao Shirakawa, Chiyoshi Yoshioka, Takashi Kambe......................................265
A-5A.4 Performance Driven Multiple-Source Bus Synthesis Using Buffer InsertionChia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Lin.........................................273
Session A-5BLogic Synthesis and Optimization (1)
Chair: Bernd BeckerCo-Chair: Tetsuya Fujimoto
A-5B.1 Communication Based FPGA Synthesis for Multi-Output Boolean FunctionsChristoph Scholl, Paul Molitor..............................................................................................279
A-5B.2 Optimum PLA Folding through Boolean SatisfiabilityJ.M. Quintana, M.J. Avedillo, M.P. Parra, J.L. Huertas......................................................289
A-5B.3 Technology Mapping for FPGAs with Complex Block Architectures by Fuzzy LogicTechnique
Jun-Yong Lee, Eugene Shragowitz.........................................................................................295A-5B.4 Logic Rectification and Synthesis for Engineering Change
Chih-Chang Lin, David Ihsin Cheng, Kuang-Chien Chen, Malgorzata Marek-Sadowska...301
Session A-5CPANEL: Future Direction of Synthesizability and Interoperability of HDL's: Part-1
Chair: Masaharu ImaiCo-Chair: Eugenio VillarPanelists: Raul Camposano, Andrew Guyler, Victor Berman, Jeffrey Fox, Sunil D. Sherlekar,Shigeaki Hakusui..................................................................................................................................311
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Session A-6ACAD Algorithms for FPGAs
Chair: Gabriele SaucierCo-Chair: Akihiro Tsutsui
A-6A.1 A New K-Way Partitioning Approach for Multiple Types of FPGAsBernhard M. Riess, Heiko A. Giselbrecht, Bernd Wurth.........................................................313
A-6A.2 Maple-opt: A Simultaneous Technology Mapping, Placement, and Global RoutingAlgorithm for FPGAs with Performance Optimization
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki.......................................................................319A-6A.3 Routing on Regular Segmented 2-D FPGAs
Yu-Liang Wu, Malgorzata Marek-Sadowska...........................................................................329
Session A-6BLogic Synthesis and Optimization (2)
Chair: Tsutomu SasaoCo-Chair: Shin-ichi Minato
A-6B.1 Flexible Optimization of Fixed Polarity Reed-Muller Expansions for Multiple OutputCompletely and Incompletely Specified Boolean Functions
Chip-Hong Chang, Bogdan J. Falkowski...............................................................................325A-6B.2 GRMIN: A Heuristic Simplification Algorithm for Generalized Reed-Muller Expressions
Debatosh Debnath, Tsutomu Sasao.........................................................................................341A-6B.3 Learning Heuristics by Genetic Algorithms
Rolf Drechsler, Bernd Becker................................................................................................349A-6B.4 Optimization Methods for Lookup-Table-Based FPGAs Using Transduction Method
Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga.....................................................353
Session A-6CPANEL: Future Direction of Synthesizability and Interoperability of HDL's: Part-2..357
Chair: Eugenio VillarCo-Chair: Masaharu ImaiPanelists: Raul Camposano, Andrew Guyler, Victor Berman, Jeffrey Fox, Sunil D. Sherlekar,Shigeaki Hakusui
Session A-7AModeling and Simulation
Chair: David SkellernCo-Chair: Tetsuro Kage
A-7A.1 A New and Accurate Interconnection Delay Time Evaluation in a General Tree-TypeNetwork
D. Deschacht, C. Dabrin......................................................................................................359A-7A.2 An Efficient Logic/Circuit Mixed-Mode Simulator for Analysis of Power Supply Voltage
FluctuationMikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita..........................365
A-7A.3 A Model-Adaptable MOSFET Parameter Extraction SystemMasaki Kondo, Hidetoshi Onodera, Keikichi Tamaru.........................................................373
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Session A-7BExtension of Binary Decision Diagrams
Chair: Tomoyuki FujitaCo-Chair: Yusuke Matsunaga
A-7B.1 Improved Computational Methods and Lazy Evaluation of the Ordered Ternary DecisionDiagram
Per Lindgren............................................................................................................................379A-7B.2 Some Remarks about Spectral Transform Interpretation of MTBDDs and EVBDDs
Radomir S. Stankovic..............................................................................................................385A-7B.3 Manipulation of Regular Expressions under Length Constraints Using Zero-Suppressed-
BDDsShinya Ishihara, Shin-ichi Minato..........................................................................................391
Session A-7CPANEL: How Sub-Micron Delay and Timing Issues Will Be Solved?................397
Chair: Hitoshi YoshizawaPanelists: Ahsan Bootehsaz, Dennis B. Brophy, Donald R. Cottrell, Antun Domic, VassiliosGerousis, Tamotsu Hiwatashi
Session A-8APlacement
Chair: Wayne W.-M. DaiCo-Chair: Masato Edahiro
A-8A.1 Exploiting Signal Flow and Logic Dependency in Standard Cell PlacementJason Cong, Dongmin Xu.......................................................................................................399
A-8A.2 A New Performance Driven Placement Method with the Elmore Delay Model for RowBased VLSIs
Tetsushi Koide, Mitsuhiro Ono, Shin’ichi Wakabayashi, Yutaka Nishimaru, NoriyoshiYoshida.....................................................................................................................................405
A-8A.3 A Neural Network Approach to the Placement ProblemM. Saheb Zamani, G.R. Hellestrand......................................................................................413
A-8A.4 Fanout-Tree Restructuring Algorithm for Post-Placement Timing OptimizationT. Aoki, M. Murakata, T. Mituhashi, N. Goto.......................................................................417
Session A-8BApplication Specific Design
Chair: Hiroaki KuniedaCo-Chair: Tatsuya Fujii
A-8B.1 Synthesis and Simulation of Digital Demodulator for Infrared Data CommunicationHiroshi Uno, Kenji Kumatani, Isao Shirakawa, Toru Chiba................................................423
A-8B.2 A Design of High-Performance Multiplier for Digital Video TransmissionKeisuke Okada, Shun Morikawa, Sumitaka Takeuchi, Isao Shirakawa...............................429
A-8B.3 Design Automation for Integrated Continuous-Time Filters Using IntegratorsKazuyuki Wada, Shigetaka Takagi, Zdzislaw Czarnul, Nobuo Fujii....................................435
A-8B.4 A Hardware-Oriented Design for Weighted Median FiltersChun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao.............................................................441
A-8B.5 Techniques for Low Power Realization of FIR FiltersMahesh Mehendale, S.D. Sherlekar, G. Venkatesh..............................................................447
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Session A-8CInvited Tutorial: EDIF Version 350/400 and Information Modelling...............451
Chair: Mike Church (Zuken-Redac, UK)Speaker: Hilary J. Kahn
Session A-9ADelay Abstraction/Design Verification
Chair: Kewal K. SalujaCo-Chair: Kazuhiro Iwasaki
A-9A.1 Delay Abstraction in Combinational Logic CircuitsNoriya Kobayashi, Sharad Malik.........................................................................................453
A-9A.2 Limits of Using Signatures for Permutation Independent Boolean ComparisonJanett Mohnke, Paul Molitor, Sharad Malik.......................................................................459
A-9A.3 A Tool for Measuring Quality of Test Pattern for LSIs' Functional DesignTakashi Aoki, Tomoji Toriyama, Kenji Ishikawa, Kennosuke Fukami................................465
Session A-9BHigh Level Synthesis (2)
Chair: Youn-Long Steve LinCo-Chair: Vasily Moshnyaga
A-9B.1 Search Space Reduction in High Level Synthesis by Use of an Initial CircuitAtsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, Masatoshi Sekine.................................471
A-9B.2 A Datapath Synthesis System for the Reconfigurable Datapath ArchitectureReiner W. Hartenstein, Rainer Kress...................................................................................479
A-9B.3 Synthesis-for-Testability Using TransformationsMiodrag Potkonjak, Sujit Dey, Rabindra K. Roy................................................................485
Session A-9CPANEL: Electronic Data Book: Current Status of Standard Representation and
Future Perspective.......................................................491Chair: Kinya TabuchiPanelists: Andy Graham, Bob Yencha, Tom Jeffery, Toshitaka Fukusima, Joe Prang
Author Index
MainASP-DAC 95Front MatterTable of ContentsSession 1A-1CSession 2A-3ASession 3B-4BSession 4C-5CSession 6A-7ASession 7B-8BSession 8C-9C
Session IndexAuthor Index