Ari Th Circuits 2

8/2/2019 Ari Th Circuits 2

1/34

ECE 261 James Morizio 1

Arithmetic Circuits-2

Multipliers Array multipliers

Shifters

Barrel shifter Logarithmic shifter


2/34


3/34


Multiplication

Example:

1100 : 1210

0101 : 510


4/34


Multiplication

Example:

1100 : 1210

0101 : 510

1100


5/34


Multiplication

Example:

1100 : 1210

0101 : 510

1100

0000


6/34


Multiplication

Example:

1100 : 1210

0101 : 510

1100

0000

1100


7/34


Multiplication

Example:

1100 : 1210

0101 : 510

1100

0000

1100

0000


8/34


Multiplication

Example:

1100 : 1210

0101 : 510

1100

0000

1100

0000

00111100 : 6010


9/34


Multiplication

Example:

M x N-bit multiplication Produce N M-bit partial products Sum these to produce M+N-bit product

1100 : 1210

0101 : 510

1100

0000

1100

0000

00111100 : 6010

multiplier

multiplicand

partialproducts

product


10/34


The Binary Multiplication

1 0 1 1

1 0 1 0 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 0 1 0

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

+

Partial Products

AND operation

Multiplicand

Multiplier


11/34


General Form Multiplicand: Y = (y M-1 , yM-2 , , y 1, y0) Multiplier: X = (x

N-1, x

N-2, , x

1, x

0)

Product:1 1 1 1

0 0 0 0

2 2 2 M N N M

j i i j j i i j

j i i j

P y x x y

+

= = = =

= =

x0y5 x0y4 x0y3 x0y2 x0y1 x0y0

y5 y4 y3 y2 y1 y0x5 x4 x3 x2 x1 x0

x1y5 x1y4 x1y3 x1y2 x1y1 x1y0x

2y

5x

2y

4x

2y

3x

2y

2x

2y

1x

2y

0x3y5 x3y4 x3y3 x3y2 x3y1 x3y0

x4y5 x4y4 x4y3 x4y2 x4y1 x4y0x5y5 x5y4 x5y3 x5y2 x5y1 x5y0

p0p1p2p3p4p5p6p7p8p9p10p11

multipliermultiplicand

partialproducts

product


12/34


Dot Diagram Each dot represents a bit

partial products

m ul t i pl i er x

x0

x15


13/34


The Array Multiplier

HA FA FA HA

FA FA FA HA

FA FA FA HA

Z 1

Z 2

Z 3Z 4Z 5Z 6

Z 0

Z 7

y0

y3

y1

x0x1x2x3 y2

x0x1x2x3

x0x1x2x3

x0x1x2x3FA: Full adderHA: Half adder

(two inputs)

Propagation delay = ?


14/34


The MxN Array Multiplier Critical Path

HA FA FA HA

HAFAFAFA

FAFA FA HA

Critical Path 1

Critical Path 2

Critical Path 1 & 2


15/34


Carry-Save Multiplier

HA HA HA HA

FAFAFAHA

FAHA FA FA

FAHA FA HA

Carries saved for nextadder stage

Unique critical path

Trade offs?


16/34


Adder Cells in Array Multiplier

A

B

P

C i

V DD A

A A

VDD

C i

A

P

A

B

VDD

VDD

C i

C i

C o

S

C i

P

P

P

P

P

Identical Delays for Carry and Sum


17/34


Multiplier Floorplan

SCSCSCSC

SCSCSCSC

SCSCSCSC

SC

SC

SC

SC

Z0

Z1

Z2

Z3Z4Z5Z6Z7

X 0X1X2X3

Y1

Y2

Y3

Y0

Vector Merging Cell

HA Multiplier Cell

FA Multiplier Cell

X and Y signals are broadcastedthrough the complete array.


18/34


Multipliers Summary

Optimiz a tio n Go a ls Diffe re nt Vs Bina ry Adde r Onc e Ag a in: Ide ntify Critic a l P a th

Othe r pos s ible te c hnique s

- Data e nc o ding (Boo th)

- P ipe lining

- Lo g a rithmic ve rs us Line a r (Wallace treemultiplier)


19/34


Comparators

0s detector: A = 00000 1s detector: A = 11111 Equality comparator: A = B

Magnitude comparator: A < B


20/34


1s & 0s Detectors 1s detector: N-input AND gate

0s detector: NOTs + 1s detector (N-input NOR)

A0A1

A2A3

A4A5

A6A7

allones

A0A

1

A2A3

allzeros

allones

A1

A2A3

A4A5

A6A7

A0


21/34


Equality Comparator Check if each bit is equal (XNOR, aka equality

gate) 1s detect on bitwise equality

A[0]B[0]

A = B

A[1]B[1]

A[2]B[2]

A[3]B[3]


22/34


Magnitude Comparator Compute B-A and look at sign B-A = B + ~A + 1 For unsigned numbers, carry out is sign bit

A0

B0A1

B1A2

B2A3

B3

A = BZ

C

B

N B


23/34


Shifters Logical Shift:

Shifts number left or right and fills with 0s 1011 LSR 1 = 0101 1011 LSL1 = 0110

Arithmetic Shift: Shifts number left or right. Rt shift sign extends

1011 ASR1 = 1101 1011 ASL1 = 0110

Rotate: Shifts number left or right and fills with lost bits

1011 ROR1 = 1101 1011 ROL1 = 0111


24/34


The Binary Shifter

A i

Ai-1

B i

Bi-1

Right Leftnop

Bit-Slice i

One-bit shifts


25/34


Multi-bit Shifters

Cascade one-bit shifters? Complex, unwieldy, slow for larger number of

shifts

Two other types of shifters Barrel shifter Logarithmic shifter


26/34


The Barrel Shifter

Sh3S h2S h1S h0

Sh3

Sh2

Sh1

A3

A2

A1

A0

B3

B2

B1

B0

: Control Wire

: Data Wire

Shift by 0 to3 bits


27/34


The Barrel Shifter Area dominated by wiring Propagation delay is theoretically constant (at most one

transmission gate), independent of shifter size, no. of shifts

Reality: Capacitance on buffer input maximum shiftwidth


28/34


4x4 barrel shifter

BufferSh3Sh2Sh1

Sh0

A3

A2

A1

A0

Width barrel ~ 2 p m M pm = metal/poly pitchM = no. of shifts


29/34


Logarithmic Shifter

Sh1 Sh1 Sh2 Sh2 Sh4 Sh4

A3

A2

A1

A0

B1

B0

B2

B3

Staged approach, e.g. 7 = 1 + 2 + 4, 5 = 1 + 0 + 4 Shifter with maximum shift width M consists of log 2M stages


30/34


0-7 bit Logarithmic Shifter

A3

A2

A1

A0

Out3

Out2

Out1

Out0


31/34


Funnel Shifter A funnel shifter can do all six types of shifts Selects N-bit field Y from 2N-bit input

Shift by k bits (0 k < N)

B C

offsetoffset + N-1

0N-12N-1

Y


32/34


Funnel Shifter Operation

Computing N-k requires an adder


33/34


Funnel Shifter Design 1 N N-input multiplexers Use 1-of-N hot select signals for shift amount

nMOS pass transistor design (V t drops!)k[1:0]

s 0s 1s 2s 3Y3

Y2

Y1

Y0

Z0Z1Z2Z3Z4

Z5

Z6

left Inverters & Decoder


34/34


Funnel Shifter Design 2 Log N stages of 2-input muxes

No select decoding needed

Y3

Y2

Y1

Y0Z0

Z1

Z2

Z3

Z4

Z5

Z6

k0k1left

Ari Th Circuits 2

Documents

Transcript of Ari Th Circuits 2