Architectural Considerations For Today’s Technology Trends · Architectural Considerations For...

19
Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, IAG & DCSG Pathfinding CTO, Datacenter & Connected Systems Group

Transcript of Architectural Considerations For Today’s Technology Trends · Architectural Considerations For...

Page 1: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Architectural Considerations For Today’s Technology Trends

Steve Pawlowski Intel Senior Fellow

GM, IAG & DCSG Pathfinding CTO, Datacenter & Connected Systems Group

Page 2: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

1.E-04

1.E-02

1.E+00

1.E+02

1.E+04

1.E+06

1.E+08

1960 1970 1980 1990 2000 2010 2020

GF

LO

P

Giga

Tera

Peta

Exa

12 Years 11 Years 10 Years

There’s an Insatiable Need For Computing

Hand-held Client

By the End of the Decade….

Terascale Clients and Handhelds Exascale Systems for High Performance Computing

Page 3: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Why Terascale Client….Why Not Use the Cloud?

Compute energy will continue to reduce

with technology scaling

Compute energy is relatively low

Data communication over distance is

energy expensive

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1 10 100 1000

En

erg

y (

Jou

le/b

it)

Distance (meter)

3G

WiFiBluetooth

Compute

Source: Wikipedia

Local Compute Power To Reduce Long Distance Communication

Memory and

Page 4: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

So, Let Us Now Look at the Energy Consumption of a Typical Terascale System Today

100pJ per FLOP

100W

150W

100W

100W

700W Decode and control

Address translations…

Power supply losses

Bloated with inefficient

architectural features

~1.2KW

Compute

Memory

Communication

Disk 10TB disk @ 1TB/disk @10W

0.1B/FLOP @ 1.5nJ per Byte

100pJ com per FLOP

5W 2W

~5W ~3W 5W

Goal

~20W

Page 5: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Moore’s Law Enabling new devices with higher functionality & complexity while controlling power, cost, and size

0.001

0.01

0.1

1

1986 1996 2006 2016

Re

lati

ve

En

erg

y/O

p

5V

Vcc scaling

Relative Performance

1

10

100

1000

1986 1996 2006 2016

Re

lati

ve

Tr

Pe

rfo

rman

ce

30X 250X

Source: Intel labs Source: Intel labs

Page 6: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Technological Challenges to Meet Performance Goals

0.001

0.01

0.1

1

1986 1996 2006 2016R

ela

tive

En

erg

y/O

p

G

Tera

Peta

5V

• Energy/op will not reduce as much

• Need to improve efficiency

• System performance needs to increase faster

than transistor performance

• Need to increase parallelism

1.E-01

1.E+01

1.E+03

1.E+05

1.E+07

1.E+09

1986 1996 2006 2016

G

Tera

Peta

36X

Exa

Transistor Performance

2.5MX

4,000X

Concurrency

Source: Intel

… it’s going to be even more challenging than ever!

Source: Intel

Page 7: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

20mm 45nm

20mm 32nm

20mm 22nm

70 Cores 123 Cores 214 Cores

0

100

200

300

400

65nm 45nm 32nm 22nm 16nm 11nm 8nm

Ch

ip P

ow

er

(W)

Network

Compute

100

150

200

250

300

350

400

450

65nm 45nm 32nm 22nm 16nm 11nm 8nm

Millio

n C

ore

s/E

FL

OP

1x Vdd

0.7x Vdd

0.5x Vdd

• Vdd Almost flat because Vdd close to

Vt @ 0.5x

• Increased communication energy

• Increased HW and unreliability

4x increase in

cores (parallelism)

Need to Strike a Balance Between Communication & Computation

Impact of Exploding Parallelism There is No Free Ride…

Page 8: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Energy Efficiency With Vdd Scaling & Near Threshold Voltage Operation

0

20

40

60

80

100

120

65nm 45nm 32nm 22nm 16nm 11nm 8nm

En

erg

y E

ffic

ien

cy (

GF

/W)

Vdd

0.7x

0.5x

~3X Compute energy efficiency with

Vdd Scaling

Page 9: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

However, Memory Bandwidth Isn’t Scaling With Moore’s Law

• Significant increase in CPU computing power

• Memory BW not keeping up

• Gap must be closed to maintain system balance

Source: Exascale Computing Study: Technology Challenges in achieving Exascale Systems (2008) Source: Intel Forecast

Traditional CPU

BW demand

HE-WS/HPC BW demand

BW Trend DDR3

Assuming DDR4

BW Projections

0

50

100

150

200

2008 2009 2010 2011 2012 2013 2014 2015 2016 2017

GB

/S (

Pe

r S

kt)

0

50

100

150

200

250

300

350

20

06

20

07

20

08

20

09

20

10

20

11

20

12

20

13

20

14

20

15

20

16

20

17

20

18

Relative Growth in

Mem BW

# of cores

Flops/cycle/Socket

Expon. (Required

Memory BW)

Page 10: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Consider New Levels of Memory Hierarchy

On CPU SRAM DRAM Storage (HDD) NVM Storage

Latency 1x ~=20x ~=20,000x ~=10,000,000x

$$/bit 1x ~=0.05x ~=0.005x ~=0.0005x

Scaling Challenges with DRAM and NAND

Source: Memory Technology Trend and Future Challenges – Singjoo Hong; Hynix Semiconductor

Page 11: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

New Memory Technologies Will Replace/Augment DRAM

Memory capacity per compute 5x-10x better than DRAM

Modest need for threading when new technologies available

Program model changes focus on increasing task scaling

Need

exponentially

increasing BW

(GB/sec)

Need

exponentially

decreasing

energy (pJ/bit)

Page 12: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Software Support Must Evolve To Minimize Data Movement and Improve Latency

Locality Optimizations

SW Focused Compression

Create Self Aware Systems

Page 13: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Memory Usage Changes….

How much legacy code needs to be changed given persistent memory, and what new interfaces and abstractions make sense with large fast memories

close to compute?

Page 14: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Continued Push on Integration

• Pins required + IO Power limits the use of traditional packaging

• Tighter integration between memory and CPU

• High BW and low latency using memory locality

CPU with 100s

of cores

Heat Extraction

DRAM or

NVRAM die

Interconnect

substrate

Through

Silicon Via

Source: Exascale Computing Study: Technology Challenges in achieving Exascale Systems (2008)

More cores per chip will slow some programs [red] unless there’s a big boost in memory bandwidth [yellow].

“Multicore Is Bad News For Supercomputers”, IEEE Spectrum Nov 2008

Page 15: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

15

Silicon Photonics Evolution Prediction

2005 2015+

Enterprise Distance: 0.1-10km

Rack-Rack Distance: 1-100m

Board-Board Distance: 20-40”

Chip-Chip Distance: 6-20”

OPTICAL

ELECTRICAL

3.125G 10G 40G

3.125G 5-6G 10G 20G

3.125G 5-6G 10G 15-20G

10G >= 40G

Copper Tech

Optical Tech

Transition Zone

Page 16: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

New Trends Mean New Security Challenges

Defend

Against

Firmware

Attacks

Keep Data Secure and

Private

Ensure

Application and

Platform

Security

Overcome

Programming

Errors

Balance Security With Usability

Source: McAfee

Stuxnet could hijack power plants,

refineries

A worm that targets critical infrastructure

companies doesn’t just steal data, it

leaves a back door that could be used to

remotely and secretly control plant

operations, a Symantec researcher said

on Thursday. CNET, Aug 13 2010

Car Hacks Exposed!

As more and more digital technology is

introduced into automobiles, the threat of

malicious software and hardware

manipulation increases. There are many

examples of research based hacks that show

the potential threats and depth of

compromise that expose the consumer.

Source: McAfee

Page 17: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Connectivity

Storage

Compute

Services

Software

Our Focus At Intel

Technologies &

Solutions

Across the Stack

To Power Balanced ,

More Secure Systems

from Milliwatts to

Petaflops

And Collaborate With the

Ecosystem to Enable Basic Needs

& Solve Grand Challenges

This decade we will create and extend computing technology

to connect and enrich the lives of every person on earth.

Page 18: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required
Page 19: Architectural Considerations For Today’s Technology Trends · Architectural Considerations For Today’s Technology Trends Steve Pawlowski Intel Senior Fellow GM, ... •Pins required

Legal Disclaimer

Today’s presentations contain forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel does not control or audit the design or implementation of third party benchmarks or Web sites referenced in this document. Intel encourages all of its customers to visit the referenced Web sites or others where similar performance benchmarks are reported and confirm whether the referenced benchmarks are accurate and reflect performance of systems available for purchase. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number for details. Intel, processors, chipsets, and desktop boards may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel, Intel Xeon, Intel Core microarchitecture, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others

Copyright © 2013, Intel Corporation. All rights reserved.