APPLICATION NOTE 6.18 Rev. 1.0

SMSC SUPER AND ULTRA I/O DESIGN ADVANTAGES AND COST

SAVINGS (REPLACEMENT FOR AN 5.3)

By Robert Schoepflin INTRODUCTION Historically, designers have favored the simplicity, reliability and cost savings of Super I/O devices over discrete floppy, serial, parallel and IDE controllers. SMSC extended this philosophy even further with the Ultra I/O family of parts wherein fundamental functional blocks of existing Super I/O controllers are combined with a keyboard controller, real-time clock, and may other features, integrating and eliminating expensive discrete logic. These parts include extensive general purpose I/O capabilities that allow designers to differentiate products with useful features without adding PALs, buffers, or rewriting keyboard controller code to take advantage of unused I/O pins. The latest family of parts, enhanced Super I/Os, were designed to mesh perfectly with the latest core logic chipsets with no overlap in functionality. The feature set of these parts includes the standard set of Super I/O functions, to which is added an integrated 8042-compatible keyboard controller. Other features include serial IRQs and power management support. This document will provide an overview of the entire line of SMSC PCI/O parts, including a detailed summary/comparison table listing the functionality provided by each part to date.

BACKGROUND In the late 1980s, SMSC integrated its floppy controller and digital data separator experience with existing UART, parallel port and IDE glue logic to create the FDC37C651. The addition of enhanced floppy cores, 16C550 UARTs and Multi-Mode IEEE1284 parallel ports led to the introduction of SMSC’s FDC37C661, FDC37C663 and finally the FDC37C665 (GT, LV and IR). For the next generation of devices, the integration of additional features to the FDC37C665 series and the support of new industry standards has resulted in the development of the FDC37C669 Super I/Os, the FDC37C93x family of Ultra I/O controllers and the FDC37C957FR Ultra I/O for portable applications. In addition, SMSC’s commitment to help OEMs make their products more affordable by eliminating redundant elements while continuing to support the latest industry standards led to the introduction of the enhanced Super I/O chips, the FDC37C67x and FDC37C68x. Figure 1 illustrates the features and design evolution of SMSC’s I/O product line.

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FEATURE SUMMARY Super I/O The FDC37C665IR Super I/O incorporates the following functional device blocks: one floppy disk controller (FDC), two 16550 serial ports (UARTs), one multi-mode parallel port, one IDE channel, a legacy game port, and IrDA Serial Infrared (SIR) support (115.2 Kbps IR, Sharp ASK and HPSIR) for wireless pointing devices. This part comes in a 100-pin QFP. The FDC37C669 Super I/O adds PC95/96/97 compatibility to the FDC37C665IR through the relocatable base I/O address (to one of 48 locations), 8 IRQ and 3 DMA options for the functional blocks, and 16-bit address qualification. The FDC37C669FR adds Fast IR (IrDA 1.1) and Consumer IR Support to the FDC37C669’s IrDA SIR support. Both parts come in a 100-pin QFP and TQFP. Ultra I/O SMSC’s FDC37C93x Ultra I/O incorporates the fundamental functional blocks of existing Super I/O controllers including a floppy disc controller, two 16550 compatible UARTs, a parallel port with ECP and EPP support, IDE interface (two channels) and IrDA SIR. These blocks are combined with an 8042 keyboard controller, real-time clock, and may other features, including 14 GPI/O pins which provide extensive general purpose I/O capabilities that allow designers to differentiate products with useful features without adding PALs, buffers, or rewriting keyboard controller code to take advantage of unused I/O pins. The FDC37C93x has an ISA Plug-and-Play Standard (Version 1.0a) compatible register set, relocatable base I/O address (to one of 96 locations), 13 IRQ and 4 DMA options for the functional blocks, and 16-bit address qualification. It is also PC 97 compliant. This part comes in a 160-pin QFP. The FDC37C93xFR is an Ultra I/O controller with an extensive feature set in a 160 pin QFP package. This part incorporates the basic features of the FDC37C93x Ultra I/O controller, and it also includes full IrDA 1.1 IR functionality, system power control (soft power management), System Management Interrupt (SMI) support and ACCESS.bus support. The FDC37C93xFR also provides 42 GPI/O pins, two group interrupts, three general purpose address decoders, Port 92 support, 24/48MHz clock output option, and the ability to relocate the configuration registers to any I/O address. The FDC37C93xFR’s IR support includes IrDA 1.1 for Fast IrDA at 1.152Mbps and 4Mbps, as well as Consumer IR to support TV type remote controls. The

soft power management allows the chip to directly control the system power supply to turn the computer on and off under software control or user inputs. It allows a variety of wakeup events to be programmed to wake the system from a low-power state. The FDC37C93xFR has an enhanced RTC which includes a 100 year alarm and a century byte to keep track of the centuries. The FDC37C93xAPM adds support for Advanced Configuration and Power Interface (ACPI) compliance along with the legacy SMI support, system power control, enhanced RTC and additional general purpose I/O pins on the FDC37C93xFR. The FDC37C93xAPM implements the ACPI master register set to allow designers to implement selected ACPI features on lower-cost desktops running ACPI-compliant operating systems. This part also implements individual enable controls for each power management scheme, ACPI and SMI. It supports 15 independently enabled events for either SMI or ACPI interrupts (SCIs), with a 24-bit free running power management timer as a 16th interrupt for ACPI. In addition, the FDC37C93xAPM supports IrDA SIR; it does not include Fast IR or Consumer IR transfer capabilities. This part comes in a 160-pin QFP which is completely footprint-compatible with the FDC37C93xFR. Portable Ultra I/O The FDC37C957FR is an Ultra I/O designed specifically for portable applications. This part incorporates an 8051 based keyboard and system controller to provide keyboard scan and advanced system power management capabilities and has a 256K x 8 shared system FLASH interface. It also meets the Serialized IRQ specifications, allowing the device to be used inside the laptop itself or in a docking station application. Other features include Fast IR and Consumer IR capabilities, four independent PS/2 ports, 42 general purpose I/O pins, two independent pulse-width modulators and an ISA host interface that provides zero-wait state access to the I/O registers. This part comes in a 208-pin QFP. The FDC37C957FR’s IR support includes IrDA 1.1 for Fast IrDA at 1.152Mbps and 4Mbps, as well as Consumer IR to support TV type remote controls. The multiple power rails and low power consumption of the FDC37C957FR allow the 8051 keyboard/power management controller to remain powered entirely under standby power (standby 5V), even while the super I/O section and CPU/core is completely powered down. While in this mode, the 8051 can still execute code without an external clock source by running on an internal CMOS ring-oscillator. The FDC37C957FR has 19 available wakeup events that automatically remove the 8051 from stop-clock state.

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Enhanced Super I/O The enhanced Super I/O parts contain the standard set of Super I/O functions, and include an integrated 8042-compatible keyboard controller containing its own 2Kbyte ROM for the keyboard BIOS. In addition, the 100-pin FDC37C67x has full Fast IR and Consumer IR capability, serial IRQs and power management support, including shadowing all write-only registers for ACPI and SMI power management compliance. The 128-pin FDC37C68x provides support for IrDA, HP-SIR and ASK-IR standards, as well as SMI power management and serial IRQs. It also contains 31 software programmable general purpose I/O pins. These enhanced Super I/Os were designed to be used with the latest core logic chipsets with no overlap in functionality. Tables 1 through 11 summarize the features of each group of I/O devices relative to PC95, PC96 and PC97 requirements. Tables 1 through 5 contain Super I/O parts; Tables 6 through 11 contain Ultra I/O and enhanced Super I/O parts. SYSTEM DESIGN Typical system designs using SMSC’s Super I/O, Ultra I/Os, Ultra I/O for portables and enhanced Super I/O parts are illustrated in Figures 2-7. DESIGN/COST ADVANTAGES Super I/O Designed for the low-cost desktop market, the FDC37C669 provides the full set of Super I/O functions. For a low-cost portable design, the FDC37C669FR is an excellent choice, as it provides Fast IR and Consumer IR data transfer capabilities. Both parts offer selection of all available IRQs and DMA channels that make it software adaptable to changing marketing requirements. In addition, both parts are PC 97 Compliant. Ultra I/O An important consideration to any design is total I/O subsystem cost. Moving a design from a Super I/O to an Ultra I/O eliminates the need for separate components for the keyboard controller and RTC. Thus, although the Ultra I/O is more costly, total subsystem cost is reduced. As the Ultra I/O chips pull in other miscellaneous discrete logic from the motherboard, its price increases slightly, but the overall I/O subsystem cost decreases. For example, the 8-bit BIOS buffer adds negligible cost to the FDC37C93x, but eliminates a 74LS245 from the cost of the motherboard. The FDC37C93x’s internal PLLs generate internal and external ISA clocks, eliminating several clock generators or PLLs and their associated costs.

Another design consideration is that unused “extra” capabilities can help eliminate downtime and costly board revisions with simple software solutions. A competing part with only one or two DMA channel options may pass existing Microsoft Windows ‘95-ready requirements, for example, but the FDC37C669 and FDC37C93x family of parts offer selection of all available IRQs and DMA channels that make it software adaptable to changing marketing requirements. This can mean the difference between one-day BIOS changes and program delays due to “wire-adds” or board redesign. Designers can reduce board space, eliminate costly additional components, and simplify advanced feature implementation such as system power management and wake-up functions through the use of the FDC37C93xFR and FDC37C93xAPM. For example, the system power management afforded by these parts allow a simple implementation to control system power, without the use of GPI/Os and external components such as flip-flops and POR circuitry. It allows the use of a low cost power switch (5 Volts instead of 120 Volts) and will directly control a “smart” ATX power supply without any external switching circuitry to go from full power to standby power. Portable Ultra I/O The FDC37C957FR affords portable designers distinct cost and space advantages. The FDC37C957FR has an 8051 core for advanced system power management, eliminating the need for an external 8051 system controller in the design while providing support for the implementation of advanced features. Although the FDC37C957FR was developed specifically for laptop applications, as desktops adopt more advanced power management features, (e.g. IBM's RapidResumeTM and Microsoft's OnNow and ACPI initiatives), the added flexibility and power of the 95x allows system designers to add new features without increasing overall component cost. The shared flash interface allows the 8051 keyboard/power management code to reside in the same FLASH block as the host CPU's BIOS code, thereby reducing the ROM requirements of the system. Shared ROM provides for more efficient use of ROM space, uses less physical board space, and allows the 8051 to read/write Host code, and vice versa. The flash interface also means that the keyboard BIOS is not fixed - it can be re-flashed to support modifications and updates to support new and improved features, thereby eliminating the need for multiple versions of parts with different mask ROMs during the product cycle. In fact, all motherboard firmware may be updated simultaneously under Host control or 8051 control. In addition, the 8051 has 256 bytes of executable internal RAM that can be loaded with 8051 interrupt vectors and small power-management handlers that

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allow the 8051 to control and modify the flash without executing out of it. SMSC Application Note 6-10, “Flash EPROM Applications for the FDC37C95x Ultra I/O Controllers” describes in detail the applications and advantages of the flash EPROM as implemented in the FDC37C957FR. Enhanced Super I/O To eliminate redundant functions and reduce board space in a design, one of the enhanced Super I/Os can be used: either the 100-pin FDC37C67x or the 128-pin FDC37C68x. These parts mesh perfectly with the latest core logic chipsets with no overlap in functionality, and the 100-pin or 128-pin package footprint is smaller than that of the 160-pin Ultra I/Os, while retaining a full feature set. FEATURE ADVANTAGES AND PRODUCT DISTINGUISHABILITY Fast IR and Consumer IR With the inclusion of Fast IR and Consumer IR capabilities to many of SMSC’s parts including the FDC37C669FR, the FDC37C93xFR, the FDC37C957FR and the FDC37C67x, designers of any type of system have the ability to implement a broad range of IR transfer capabilities in their machines. System Power Management and Wakeup Events The system power management capabilities of the FDC37C93xFR, FDC37C93xAPM and FDC37C957FR provide support for the OnNow features required in the Simply Interactive PC strategy proposed by Microsoft. These parts allow the entire PC system to be powered off except for only one of the multiple power planes inside the device, which powers only the Real-Time Clock (RTC) and a small amount of monitoring circuitry. When an external event, such as a button being pressed or a phone call activating the Ring Indicator signal causes the system to wake up, the chip activates a signal to turn on the power supply to the rest of the system, quickly turning on the system without going through a lengthy boot-up sequence. Ultra I/O The system power management combined with the enhanced RTC in the FDC37C93xFR and FDC37C93xAPM allows the implementation of new capabilities to the machine. With the proper software support, the machine will be able to wakeup (i.e., turn itself on) at a predetermined time (within the next 100 years) or once a minute, hour, day week month or year to do regular maintenance such as performing a tape back-up, or send out a fax when the telephone rates are the lowest. It will also be able to shut itself off at any time under software control, such as when the user

exits Windows 95 instead of having the user wait for the “OK to Shut Off the Machine” and doing it manually. The FDC37C93xAPM provides ACPI support on desktop machines using core logic chipsets that do not fully implement ACPI. The FDC37C93xAPM implements the ACPI master register set to allow designers to implement selected ACPI features on lower-cost desktops running ACPI-compliant operating systems. The FDC37C93xAPM also provides legacy SMI power management, and implements individual enable controls for each power management scheme - SCIs (System Control Interrupts under ACPI) or SMIs, thereby allowing designers to determine on an event by event basis, which events are best handled by SCI or SMI logic. Some examples of power management features that can be implemented with the FDC37C93x family include soft power on/off with direct connection to front panel buttons; wake from snooze or power off upon: any UART activity, keyboard or mouse activity, infrared activity, RTC alarm, SPP, EPP, or ECP Interrupt from Parallel Port, or any other button (implemented through GP key debounce inputs) or non-PnP IRQ input. In addition, a 1-255 minute time-out of CRT, CPUCLK, or system power can be implemented, as well as a hardware blink of the power LED during low-power or "off" mode, triggered by the watchdog timer. SMSC Application Note 6.9, “SoftPower Management (SPM) with SMSC 93x Ultra I/O” describes in detail various methods of soft power supply and clock throttling control with the FDC37C93x and FDC37C93xFR. Each application offers certain tradeoffs of functionality with overall cost. The FDC37C93x circuit allows soft power supply control, and "soft off", but only allows the button to turn on the machine. The FDC37C93xFR example shows the most complete, multiple wakeup and power-off events and choices. Portable Ultra I/O The multiple power rails and low power consumption of the FDC37C957FR allow the 8051 keyboard/power management controller to remain powered entirely under standby power (standby 5V), even while the super I/O section and CPU/core is completely powered down. While in this mode, the 8051 can still execute code without an external clock source by running on an internal CMOS ring-oscillator. When this clock is stopped and the 8051 is idle, the FDC37C957FR pulls less than 20 uA. The FDC37C957FR has 19 available wake-up events that automatically remove the 8051 from stop-clock state.

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SMSC Application Note 6.7, “Application for the FDC37C95x Ultra I/O controllers Dual ‘Personal’ Ring Detect” describes in detail one of the external wake-up event inputs used to detect the phone ring signal directly from the phone line. This application note describes how several PC answering machine features can be enabled with the same software. The BIOS can preset the number of rings before the machine powers up; or, the number of rings can be preset independently depending on the time of day. Using the personalized ring feature provided by the phone company (wherein two phone numbers are routed to the same physical phone line but calling each number produces a distinct ring pattern) the FDC37C957FR equipped PC is capable of answering with a professional message or fax machine for the Home Office, and a personal message for the home number. General Purpose Input/Output Capabilities The many GPI/Os that are on the FDC37C93x, FDC37C93xFR, FDC37C93xAPM, FDC37C68x and FDC37C957FR can be used to add many advanced features to a system to distinguish it from competing products. Ultra I/O To illustrate the flexibility and diversity of application for these parts, the following discussion describes some of the applications for the GPI/Os and wakeup functions for the FDC37C93xFR and FDC37C93xAPM. The GPI/Os can be configured as wake-up functions through the Group Interrupts. Functions such as Power LED, Watch Dog Timer (WDT), IR receive and transmit (IRRX and IRTX), general purpose address decode or write strobe, joystick read/write strobe, serial EEPROM interface, 8042 pins, nSMI, ACCESS.bus clock and data can be used through the alternate functions on some of the GPI/O pins. In addition, IRQs can be mapped to any of the IRQ pins on the chip through GP10 and GP11 (IRQ in) or by enabling the GPI/Os to one of the group interrupts. These group interrupts can then be steered to any of the IRQ pins through the Group Interrupt Registers, GPINT1 and GPINT2. Some possible additional applications for the GPI/Os include I2C or microwire interfaced A/D, D/A converter or pulse width modulator; I2C EEPROM; software control of motherboard jumper settings or “open collector” switches (front panel controls); or card presence detect inputs. In addition, the GPI/O pins can be configured for wake-up functions by enabling them onto one of the group interrupts. One example of this would be using a motion sensor, configured through a GPI/O pin enabled onto a group interrupt, to turn the PC on upon someone entering the room, and turning it off after some delay upon leaving the room.

The following discussion outlines some of the wakeup event and power on/off applications for the FDC37C93xFR and FDC37C93xAPM through the use of the soft power management and RTC features. Soft power management allows a variety of wakeup functions, including the button input pin, UART1,2 ring indicator pins, UART1,2 receive data pins, keyboard clock, mouse clock, IR receive pin, RTC alarm, RTC Alarm 2, and the group interrupt signals (GPINT1 and GPINT2). Soft power management also allows “user friendly” system shutdown through the software control of power off. In addition, by using the button input pin to power the entire system, a low cost power switch can be used (5V instead of 120V switch). The enhanced RTC, along with the soft power management functions will allow the machine to wakeup (i.e., turn itself on) at a predetermined time or once a minute, hour, day, week, month or year to do regular maintenance such as performing a tape back-up, or send out a fax when the telephone rates are the lowest and then shut itself off when it is finished. Naturally, these example applications would require software packages that take advantage of the hardware features of the FDC37C93xFR/APM. The second alarm, alarm 2, provides another wakeup function to the system. Even if power is lost and the time that alarm 2 is set for has passed, the system will wakeup upon the return of the standby power (VTR) if the alarm 2 remember enable bit is set. Using the combined features of soft power management and the real-time clock, there are three ways to turn on the system: Manually, by pressing the button, through an event (wakeup function) or an alarm. Using the features of soft power management, there are two ways to turn off the system: Manually, by pressing the button or through software setting a bit in the configuration registers. Portable Ultra I/O In addition to the GPIO capabilities described above, the FDC37C957FR has several GPIOs that can be used to directly wake up the 8051. These pins can be used to implement features such as lid switch, button press, PCMCIA card or AC adaptor insertion/removal as wake events for the 8051. With this capability, while the system is “off” (in a low power state,

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I. Super I/O Device Summary Regarding PC 97

Revision 1.0 Requirements • FDC37C669 The FDC37C669 supports all the requirements and recommendations of PC 97. • FDC37C669FR The FDC37C669FR supports all the requirements and recommendations of PC 97.

I. Ultra I/O Device Summary Regarding PC 97 Revision 1.0 Requirements

• FDC37C93x The FDC37C93x supports all the requirements

and recommendations of PC 95. (The FDC37C93x does not fully support PC 97 requirements due to the fact that the logical devices do not function while the part is in configuration mode).

• FDC37C93xFR The FDC37C93xFR supports all the requirements and

recommendations of PC 97. • FDC37C93xAPM The FDC37C93xAPM supports all the requirements and recommendations of PC 97. • FDC37C957FR The FDC37C957FR supports all the requirements and

recommendations of PC 97 using Serial IRQs. • FDC37C67x The FDC37C67x supports all the requirements and

recommendations of PC 97 using Serial IRQs. • FDC37C68x

The FDC37C68x supports all the requirements and recommendations of PC 97 using Serial IRQs.

SUMMARY By taking advantage of the integration and advanced features of the SMSC Ultra I/O and Enhanced Super I/O family of parts, designers can reduce board space, eliminate costly additional components, and simplify advanced feature implementation such as system power management, alarm and wake-up functions, Fast IR, and self configuration while adhering to the latest industry standards.

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FIGURE 1 - FEATURES AND DESIGN EVOLUTION OF SMSC’s I/O PRODUCT LINE

F D C 37C 661

F D C 37C 663

FD C 37C 67x

F D C 37C 669

FD C 37C 669F R

IE E E 12 8 4E C P /E P P

E P P 1 .9 /1 .7 P PF lo pp y D ua l P IN T R

IrD A & S harp In frared

4 60 K B U A R T

A uto P o w erM an ag em en t

80 42 K B D R T C

IS A P N P 1 .0 a

2 /4 ID E

E E P R O MW D T im er

B IO S ‘2 45

A d van cedG P IO s

80 51 K eyb oa rd &S ys tem C on tro lle r

F ast IR (IrD A 1 .1 )C on sum er IR

P C 95 C om plian t:M ultip le IR Q s & D M A s,I/O A ddress R elocation

S o ft P ow er M ana gem en t,S M I S u p po rt

F ast IR (IrD A 1 .1 )C o nsu m er IR

E nh an ced R T C ,A d d ition a l G P IO s

F ast IR (IrD A 1 .1 )C o nsu m er IR

S eria l IR Q s

N oF ast IR (IrD A 1 .1 )

o r C o nsu m e r IR

G P IO s

8 0 42 K B D

F lash R O MIn terface

160-P inF D C 37C 93x

100-P inFD C 37C 665IR

100-P inFD C 37C 665G T

100-P inFD C 37C 665

208-P in

208-P in

160-P in

160-P in

100-P in

100-P in

100-P in

128-P in

F ast IR (IrD A 1 .1 )C on sum er IR

S eria l IR Q s

F D C 37C 957 FD C 37C 93xF R

FD C 37C 93xA P M

F D C 37C 957FR

F D C 37C 68x

N o R T C

A C P IS u pp o rt

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PC 97 System Requirements and Comparison, Super I/O Devices

Table 1 - Motherboard (Desktop and Mobile) PC System Configuration, Super I/O SMSC SMSC SMSC

FEATURE PC 95 PC 96 PC 97 665IR 669 669FR Power Management

Software power down no yes yes Y Y Y

Low power standby mode no yes yes 100uA/ 500uA

(3)

2mA (4)

2mA (4)

INTEGRATED DEVICE BLOCKS Floppy Disk Controller optional 1 1 1

Multi-Mode P1284 Parallel Port 1 1 REQ ePC-USB

1 1 1

Serial ports 16450 (see next) (1) 1

Serial Ports 16550 (1) 1 REQ ePC-USB

2 2 2

Serial infrared devices (IrDA specification) (2)

no yes optional ePC-REQ

Y Y Y

IDE/ IDE CD ROM Y Y Y

Game Port Legacy Game

Port (LGP)

LGP RCMD - USB or MIDI

LGP LGP LGP

Wireless Pointing Device RCMD ePC-REQ

IrDA SIR

IrDA SIR

IrDA 1.1

(1) If the serial port is used for a pointer device then two are required in the system.

(2) See specific component section following for detailed requirements and recommendations. IrDA SIR = 115.2 Kbps IR, Sharp ASK and HPSIR. IrDA 1.1 = full compliance to IrDA Specification 1.1 which includes HDLC 0.576 Mbps, HDLC 1.152 Mbps, 4 PPM 4 Mbps and Consumer IR modes. (3) Standby current is 100µA @ 3.3V, 500µA @ 5V. (4) Under Investigation - should be much lower.

Key REQ - Required by PC 97 guidelines RCMD - Recommended by PC 97 guidelines optional - neither recommended or required

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Table 2 - Component - Floppy Disk Drive Controller, Super I/O SMSC SMSC SMSC

FEATURE PC 95 Req PC 96 PC 97 665IR 669 669FR Floppy Disk Drive Controller (1) optional

Write-protect detection no yes Y Y Y

Resources

16 Bit Address Decode REQ N Y Y

I/O: 3Fx yes 2 48 48

I/O: 3Fx and 37x yes 2 48 48

I/O: 3F2h, 3F4h, and 3F5h. REQ Y Y Y

I/O: 3F7h or 377h can not be claimed (2) REQ BIOS BIOS BIOS

IRQ signals: IRQ6 1 REQ 1 7 7

IRQ signals: IRQ6 + 6 more 7 1 7 7

DMA yes yes REQ - Chan 2(3)

1 3 3

Disable yes yes REQ Y Y Y (1) A floppy disk drive controller is not a requirement for a PC 97 computer. Although most systems ship

with some form of floppy disk drive, some systems such as diskless workstations do not need one. A Floppy Disk Controller built onto the system board is recommended unless the Floppy Disk capability is provided through a PC Card, SCSI, ATAPI, IDE, or a USB device. An FDC that is included on a PC 97 motherboard must meet the requirements listed above.

(2) This is a PNP BIOS issue, the FDC will still decode and drive bit 7 in response to an address read of 3F7, 377, or FDC_BASE+07. (3) If FDC supports block data transfers.

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Table 3 - Parallel/Serial Port, Super I/O SMSC SMSC SMSC

FEATURE PC 95 PC 96 PC 97 665IR 669 669FR Parallel (Printer) Port 1 1 1 Compatibility and nibble mode (IEEE P1284) yes yes REQ Y Y Y ECP (IEEE P1284 D2.00) no yes REQ Y Y Y Resource Configurations 16 Bit Address Decode REQ N Y Y I/O: 378h, 278h 2 2 192 192 I/O: 378h, 278h + 4 additional 6 2 192 192 I/O: 378h, 278h, 3BCh REQ 2 192 192 I/O: 378h, 278h, 3BCh + 4 additional (1) RCMD 2 192 192 IRQ signals: IRQ5, IRQ7 2 2 REQ 2 7 7 IRQ5, IRQ7 + 5 additional 7 7 RCMD 2 7 7 DMA channels (if needed) no 3 2 REQ(2) 1

8-bit 3

8-bit 3

8-bit Disable yes yes REQ Y Y Y

SERIAL PORT 2 2 2 16550A UART (or equivalent) no yes REQ Y Y Y 115.2K Baud support yes yes REQ Y Y Y

RESOURCES 16 Bit Address Decode REQ N Y Y I/O: 3F8h, 2F8h, 3E8h, 2E8h 4 4 REQ 7 96 96 I/O: 3F8h, 2F8h, 3E8h, 2E8h + 3 more 7 7 96 96 Independent IRQ signals: IRQ3, IRQ4 2 REQ 2 7 7 IRQ signals: IRQ3, IRQ4 + 5 more 7 2 7 7 IRQ signals: (IRQ3 or IRQ4) + 1 more (3) 2 REQ 2 7 7 Disable yes yes REQ Y Y Y (1) If EPP support is implemented, the hardware cannot use 3BCh as the port’s base address. This avoids legacy conflicts with VGA devices. (2) If parallel port design supports block data transfers to memory using DMA controllers (3) Two IRQs are required for each port. If two serial ports are implemented in the system, the IRQs are assigned as follows: For Serial Port A : IRQ4 + other (i.e., IRQ11) For Serial Port B : IRQ3 + other (i.e., IRQ10)

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Table 4 - Infrared Port, Super I/O SMSC SMSC SMSC

FEATURE PC 95 PC 96 PC 97 665IR 669 669FR Adapter Configuration/Resources 16 Bit Address Decode REQ N Y Y I/O: 4 Unique locations 4 mbd REQ 7 96 96 I/O: 7 Unique locations 7 add-on RCMD 7 96 96 IRQ signals: 4 Unique IRQ channels 4 mbd REQ 2 7 7 IRQ signals: 7 Unique IRQ channels 7 add-on RCMD 2 7 7 DMA channels: N 4 4 Disable yes REQ Y Y Y

IR MODES IrDA SIR yes REQ Y Y Y IrDA HDLC, 0.576Mbps & 1.152Mbps N N Y IrDA 4PPM, 4Mbps RCMD N N Y Both IrDA and Consumer IR support RCMD N N Y RAW IR (bit-banged) Y Y Y

IR ENHANCEMENTS Echo Cancellation in H/W - IrDA SIR yes REQ N N Y Unicast Filtering - IrDA HDLC & 4PPM RCMD N N N

DRIVER REQUIREMENTS Bit-rate adaptation VxD - IrDA SIR yes REQ Y Y Y Mode Switching at Driver Level (1) REQ Config Run Run NDIS-compliant Miniport IR driver for all Modes REQ Y Y Y

(1) Config = IR Mode switched through configuration registers in Configuration Mode. Run = IR Mode switched through run-time registers.

Table 5 - Miscellaneous Features, Super I/O SMSC SMSC SMSC

MISCELLANEOUS FEATURES PC 95 PC 96 PC 97 665IR 669 669FR 5V, 3.3V & Mixed 5V/3.3V - 5V Tolerant I/O Y N N Relocatable Configuration Index/Data Regs 2 2 2 ACPI Features Supported Single Write to enter Configuration Mode REQ N(1) N(1) N(1) Logical Devices Function in Configuration Mode REQ N Y Y Zero Wait State Register I/O Access N N N Selectable Clock Input Frequencies N N N Parallel Port FDC Y Y Y 2Mbps Tape Drive Support N Y Y FDC IDLE & PD output pins N N N Power Down Input Pin / PWRGD pin Y Y Y Steerable IRQs for non-PNP devices N Y Y Vcc Pins 2 2 2 Vss Pins 4 4 4 100 Pin TQFP Y Y Y 100 Pin PQFP Y Y Y

(1) The double write required to enter configuration can be worked around in software.

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PC 97 System Requirements and Comparison, Ultra I/O Devices

Table 6 - Motherboard (Desktop and Mobile) PC System Configuration, Ultra I/O SMSC SMSC SMSC SMSC SMSC SMSC

FEATURE PC 95 PC 96 PC 97 93x 93xFR 93xAPM 957FR 67x 68x Power Management

Software power down no yes yes Y Y Y Y Y Y Low power standby mode no yes yes Y Y Y Y Y Y

INTEGRATED DEVICE BLOCKS Floppy Disk Controller optional 1 1 1 1 1 1 Multi-Mode P1284 Parallel Port 1 1 REQ

ePC-USB 1 1 1 1 1 1

Serial ports 16450(see next) (1) 1 Serial Ports 16550 (1) 1 REQ

ePC-USB 2 2 2 2 2 2

Serial infrared devices (IrDA spec.) (2)

no yes optional ePC-REQ

IrDA SIR

IrDA 1.1 IrDA SIR

IrDA 1.1

IrDA 1.1

IrDA SIR

IDE/ IDE CD ROM Interface 2 Chan 2 Chan 2 Chan N N N Game Port Legacy

Game Port

(LGP)

LGP RCMD - USB or MIDI

LGP LGP LGP N N Y

External Keyboard Interface REQ ePC-USB

PS2 8042

PS2 8042

PS2 8042

2xPS2 8051

PS2 8042

PS2 8042

External Pointing Device Interface REQ ePC-USB

PS2 8042

PS2 8042

PS2 8042

2xPS2 8051

PS2 8042

PS2 8042

Real Time Clock (3) Y ERTC ERTC Y N N CMOS RAM 256B 256B 256B 256B - - USB Interface REQ

ePC-2 portsN N N N N N

P1394 Interface RCMD ePC-REQ

N N N N N N

PC Card Controller Interface RCMD esp for ePC

N N N N N N

Wireless pointing device support RCMD ePC-REQ

IrDA SIR

IrDA 1.1

IrDA SIR

IrDA 1.1

IrDA 1.1

IrDA SIR

(1) If the serial port is used for a pointer device then two are required in the system. (2) See specific component section following for detailed requirements and recommendations. IrDA SIR =

115.2 Kbps IR, Sharp ASK and HPSIR. IrDA 1.1 = full compliance to IrDA Specification 1.1 which includes HDLC 0.576Mbps, HDLC 1.152 Mbps, 4 PPM 4 Mbps and Consumer IR modes.

(3) ERTC = Enhanced Real Time Clock with 2nd Alarm and Century Byte.

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Table 7 - Component - Floppy Disk Drive Controller, Ultra I/O SMSC SMSC SMSC SMSC SMSC SMSC

FEATURE PC 95 PC 96 PC 97 93x 93xFR 93xAPM 957FR 67x 68x Floppy Disk Drive Controller (1) optional Write-protect detection no yes - Y Y Y Y Y Y Resources 16 Bit Address Decode REQ Y Y Y Y Y Y I/O: 3Fx yes 480 480 480 480 224 480 I/O: 3Fx and 37x yes 480 480 480 480 224 480 I/O: 3F2h, 3F4h, and 3F5h. REQ Y Y Y Y Y Y I/O: 3F7h or 377h can not be claimed (2) REQ BIOS BIOS BIOS BIOS BIOS BIOS ISA IRQ signals: IRQ6 1 REQ 13 13 13 7 (4) 8 (4) - (4) ISA IRQ signals: IRQ6 + 6 more 7 13 13 13 7 (4) 8 (4) - (4) Serial IRQ signals N N N 15 15 15 DMA yes yes REQ -

Chan 2 (3)

4 8-bit

4 8-bit

4 8-bit

4 8-bit

3 8-bit

3 8-bit

Disable yes yes REQ Y Y Y Y Y Y (1) A floppy disk drive controller is not a requirement for a PC 97 computer. Although most systems ship with

some form of floppy disk drive, some systems such as diskless work stations do not need one. It is recommended that the Floppy Disk capability be provided through an external bus such as PC Card, USB, or an expansion card for SCSI, or IDE. An FDC that is included on a PC 97 motherboard must meet the requirements listed above. (2) This is a PNP BIOS issue, the FDC will still decode and drive bit-7 in response to an address read of 3F7, 377, or FDC_BASE+07. (3) Use DMA channel 2 if FDC supports block data transfers to memory using DMA controllers. (4) IRQ requirements are fully met through Serial IRQs

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Table 8 - Parallel/Serial Port, Ultra I/O SMSC SMSC SMSC SMSC SMSC SMSC

FEATURE PC 95 PC 96 PC 97 93x 93xFR 93xAPM 957FR 67x 68x Parallel (Printer) Port 1 1 1 1 1 1 Compatibility and nibble mode (IEEE P1284)

yes yes REQ Y Y Y Y Y Y

ECP (IEEE P1284 D2.00) no yes REQ Y Y Y Y Y Y Resource Configurations 16 Bit Address Decode REQ Y Y Y Y Y Y I/O: 378h, 278h 2 480 480 480 480 224 480 I/O: 378h, 278h + 4 additional 6 480 480 480 480 224 480 I/O: 378h, 278h, 3BCh REQ 480 480 480 480 224 480 I/O: 378h, 278h, 3BCh + 4 additional (1) RCMD 480 480 480 480 224 480 IRQ signals: IRQ5, IRQ7 2 2 REQ 13 13 13 7 (4) 8 (4) - (4) IRQ5, IRQ7 + 5 additional 7 7 RCMD 13 13 13 7 (4) 8 (4) - (4) Serial IRQ signals N N N 15 15 15 DMA channels (if needed) no 3 2 REQ (2) 4

8-bit 4

8-bit 4

8-bit 4

8-bit 3

8-bit 3

8-bit Disable yes yes REQ Y Y Y Y Y Y

SERIAL PORT 2 2 2 2 2 2

16550A UART (or equivalent) no yes REQ Y Y Y Y Y Y 115.2K Baud support yes yes REQ Y Y Y Y Y Y

RESOURCES 16 Bit Address Decode REQ Y Y Y Y Y Y I/O: 3F8h, 2F8h, 3E8h, 2E8h 4 4 REQ 480 480 480 480 224 480 I/O: 3F8h, 2F8h, 3E8h, 2E8h + 3 more 7 480 480 480 480 224 480 Independent IRQ signals: IRQ3, IRQ4 2 13 13 13 7 (4) 8 (4) - (4) IRQ signals: IRQ3, IRQ4 + 5 more 7 13 13 13 7 (4) 8 (4) - (4) IRQ signals: (IRQ3 or IRQ4) + 2 more (3) REQ 13 13 13 7 8 - Serial IRQ signals N N N 15 15 15 Disable yes yes REQ Y Y Y Y Y Y (1) If EPP support is implemented, the hardware cannot use 3BCh as the port’s base address. This avoids legacy conflicts with VGA devices. (2) If parallel port design supports block data transfers to memory using DMA controllers (3) Two IRQs are required for each port. If two serial ports are implemented in the system, the IRQs are assigned as follows: For Serial Port A : IRQ4 + other (i.e., IRQ11) For Serial Port B : IRQ3 + other (i.e., IRQ10) (4) IRQ requirements are fully met through Serial IRQs

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Table 9 - Infrared Port, Ultra I/O SMSC SMSC SMSC SMSC SMSC SMSC

FEATURE PC 95 Req PC 96 PC 97 93x 93xFR 93xAPM 957FR 67x 68x Adapter Configuration/Resources 16 Bit Address Decode REQ Y Y Y Y Y Y I/O: 4 Unique locations 4 mbd REQ 480 480 480 480 224 480 I/O: 7 Unique locations 7 add-on RCMD 480 480 480 480 224 480 IRQ signals: 4 Unique IRQ channels 4 mbd REQ 13 13 13 7 (2) 8 (2) - (2) IRQ signals: 7 Unique IRQ channels 7 add-on RCMD 13 13 13 7 (2) 8 (2) - (2) Serial IRQ signals N N N 15 15 15 DMA channels: 4

8-bit 4

8-bit 4

8-bit 4

8-bit 3

8-bit 3

8-bit Disable yes REQ Y Y Y Y Y Y

IR MODES IrDA SIR yes REQ Y Y Y Y Y Y IrDA HDLC, 0.576Mbps & 1.152Mbps N Y N Y Y N IrDA 4PPM, 4Mbps RCMD N Y N Y Y N Both IrDA and Consumer IR support RCMD N Y N Y Y N RAW IR (bit-banged) Y Y Y Y Y Y

IR ENHANCEMENTS Echo Cancellation in H/W - IrDA SIR yes REQ N Y Y Y Y Y Unicast Filtering - IrDA HDLC & 4PPM

RCMD N N N N N N

DRIVER REQUIREMENTS Bit-rate adaptation VxD - IrDA SIR yes REQ Y Y Y Y Y Y Mode Switching at Driver Level (1) REQ Config Run Config Run Run ConfigNDIS 4.0 Miniport IR driver for all Modes

REQ Y Y Y Y Y Y

(1) Config = IR Mode switched through configuration registers in Configuration Mode. Run = IR Mode switched through run-time registers. (2) IRQ requirements are fully met through Serial IRQs

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Table 10 - Component - Mouse/Keyboard I/O Port, Ultra I/O SMSC SMSC SMSC SMSC SMSC SMSC

FEATURE PC 95 PC 96 PC 97 93x 93xFR 93xAPM 957FR 67x 68x Mouse PS/2-style port no yes optional

USB RCMD

Y Y Y 2 Y Y

Personal System/2 Specifications by IBM

yes yes REQ Y Y Y Y Y Y

8042 (or equivalent) (1) yes yes REQ Y Y Y (1) Y Y RESOURCES

IRQ signals: IRQ12 yes yes REQ Y Y Y Y Y Y(2) 16 Address Decode REQ Y Y Y Y Y Y I/O: 60, 64 yes yes REQ Y Y Y Y Y Y Disable yes yes REQ Y Y Y Y Y Y

KEYBOARD PS/2-style port no yes optional

USB RCMD

Y Y Y 2 Y Y

Personal System/2 Specifications by IBM

yes yes REQ Y Y Y Y Y Y

8042 (or equivalent) (1) yes yes REQ Y Y Y (1) Y Y RESOURCES

IRQ signals: IRQ1 yes yes REQ Y Y Y Y Y Y(2) 16 Address Decode REQ Y Y Y Y Y Y I/O: 60, 64 yes yes REQ Y Y Y Y Y Y Disable yes yes REQ Y Y Y Y Y Y No Interference between keyboards for multiple devices

REQ n/a n/a n/a Y n/a n/a

(1) SMSC’s FDC37C957FR has an 8051 embedded KBD controller with an 8042-style Host Interface. (2) Available using serial IRQ.

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Table 11 - Miscellaneous Features, Ultra I/O SMSC SMSC SMSC SMSC SMSC SMSC

MISCELLANEOUS FEATURES PC 95 PC 96 PC 97 93x 93xFR 93xAPM 957FR 67x 68x Power Planes VRUN Y Y Y Y Y Y VSTDBY N Y Y Y N N VBAT Y Y Y Y N N 5V, 3.3V & Mixed 5V Tolerant 5V

only 5V

only 5V

only 5V

only 5V

only 5V

only Power Management (OnNow H/W Support)

REQ

Independent Wake Up Events (1) 0 11 11 19 n/a n/a Vrun Power On Control Output N Y Y Y n/a n/a OFF Timer Delay N Prog Prog Prog n/a n/a Software Controlled Power Off REQ N Y Y Y n/a n/a SMI Events Supported (2) N 13 15 19+ 9 11 ACPI Features Support REQ SCI Events Supported REQ N N 16 N N N Power Management Timer REQ N N Y N N N Override Event on Power Button REQ N N Y N N N RTC Alarm for SCI REQ N N Y N N N RTC Alarm for SMI N N Y N N N Either Edge Triggered Interrupt Inputs REQ N N 3 Y N N Single Write to Enter Configuration Mode

REQ N(5) N(5) Y N(5) Y Y

Logical Devices Function in Configuration Mode

REQ N Y Y Y Y Y

Enhanced Real Time Clock (RTC) (3) N Y Y N N N Relocatable Configuration Registers 370h,

3F0h 00h-

FFFFh00h-

FFFFh 370h, 3F0h

00h- 7FFh

00h- FFFFh

Enhanced KBD Controller (4) N Y Y Y Y Y Direct Keyboard Scan Interface N N N 16x8 N N 8042 P1.2 - P1.7 pins available N Y Y n/a P12,

P16 Y

PLL Clock Outputs 3 14M,1 16M,1 24M

3 14M,1 16M,1 Prog

3 14M, 1 16M, 1 Prog

1 Prog 5 freqs

N 1x24/481x14M

General Purpose I/O 14 42 42 42 0 31 General Purpose Address Decoder 1 3 3 N 0 1 XD Bus (BIOS Buffer) Y Y Y n/a N N Shared Flash BIOS (System and KBD) N N N Y N N Parallel Port FDC Interface N Y Y Y Y Y

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Table 11 - Miscellaneous Features, Ultra I/O (Continued) SMSC SMSC SMSC SMSC SMSC SMSC

MISCELLANEOUS FEATURES PC 95 PC 96 PC 97 93x 93xFR 93xAPM 957FR 67x 68x Package 160

PQFP 160

PQFP160

PQFP 208

TQFP 100

PQFP128

PQFPIRQ Steering 2 2 2 N N Y ACCESS.Bus Interface N Y Y Y N N Pulse Width Modulators N N N 2 N N Serial IRQ Support (SIRQ) N N N Y Y Y System RESET Output Signal N N N Y N N LED Output Pins 1 1 1 3 N 1 Hardware Assisted PS/2 Style Channels N N N Y N N SMI Watchdog Timer N N N N N Y RTC Current Consumption 500nA 500nA 500nA 500nA n/a n/a 1) Includes Power Button input. 2) SMSC’s FDC37C957FR generates System Management Interrupts (nSMI) via the onboard 8051 writing to the

Host’s mailbox register -- thus the FDC37C957FR provides a flexible and programmable set of SMI events. 3) The Enhanced RTC includes a second alarm as well as a century byte. 4) Includes PORT92 features. 5) The double write required to enter configuration can be worked around in the software.

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µP

C LO C K PLLISA

C LO C K S

B IO SB UFFER

B IO S

RS -2 32D R IVER S

RA M C A C H E EEPR O M G LUE

N O R THB R IDG E

SO U THB R IDG E

RT C

KB D

G A M E5 58

SM SCFD C 37 C 6 69 FR

G PI/O

IDE2 ,3

C O M 1 C O M 2

IDE0 ,1

FD D

LPT

F IR /C IR

P C I IS A

FIGURE 2 - SYSTEM IMPLEMENTATION FOR FDC37C669FR

20

µP

C LO C K

IS AC LO C K S

B IO S

E EP R O M

S M S CF D C 3 7 C 9 3 x

G am e2

G P I/O s

ID E 0 ,1

F D D

LPT

ID E 2 ,3

K B D

M o us e

R S -2 3 2D R IV E R S

G A M E5 5 8

C O M 1 C O M 2

G A M E5 5 8

S R A M D R A M

G am e1

S IR

N O R T HB R ID G E

S O U T HB R ID G E

P C I

FIGURE 3 - SYSTEM IMPLEMENTATION FOR FDC37C93x

21

µP

C LO C K

ISAC LO C KS

B IO S

S RA M D RA M EEPR O M

SM SCFD C 37C 93xFR

G am e1

G am e2

R S-2 32D R IV ERS

G AM E558

C O M 1 C O M 2

G AM E558

Button_In

nPow erO nPow erS upp ly

V ccV trF ront Pa ne l

O n /O ff Sw itc h

G PI/O s

F IR /C IR

FD D

LPT

KBD

M ouse

IDE2 ,3

IDE0 ,1

S M I

N O RTHBR ID GE

S OU THBR ID GE

P C I IS A

FIGURE 4 - SYSTEM IMPLEMENTATION FOR FDC37C93xFR

22

CPU

NB

SB

SMSCFDC37C957FR

SRAM

DRAMV

IDEO

34C

90 C

ardb

us

LAN

83C

170

Eth

erne

t

AGP

USB

BATTERY

PCI

ISA

SwitchGPIOVCC1VCC0

VCC2

nRESET_OUT

3V

3V

3V

PWR SWLID SW

IN0 IN1

EIDE

Serial IRQFlash

GPI/Os

FDDLPTKBD

PWM

MouseKBD Scan

LEDs

RS-232DRIVERS

COM1COM2

FIR/CIR

FIGURE 5 - SYSTEM IMPLEMENTATION FOR FDC37C957FR

23

CPU

NB

SB

SMSCFDC37C67x

SRAM

DRAMVI

DEO

34C

90 C

ardb

us

LAN

83C

170

Ethe

rnet

USB

PCI

ISA

EIDE

Serial IRQ

FDD

LPT

KBDMouse

RS-232DRIVERS

COM1

COM2

FIR/CIR

AGP

FIGURE 6 - SYSTEM IMPLEMENTATION FOR FDC37C67x

24

CPU

NB

SB

SMSCFDC37C68x

SRAM

DRAMVI

DE

O

34C

90 C

ardb

us

LAN

83C

170

Ethe

rnet

USB

PCI

ISA

EIDE

Serial IRQ

GPI/Os

FDDLPTKBDMouse

RS-232DRIVERS

COM1

COM2

SIR

AGP

FIGURE 7 - SYSTEM IMPLEMENTATION FOR FDC37C68x

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