“Real Men Do ASICs!” - NMI · “Real Men Do ASICs!” How to reduce risk and cost of ASIC/SoC...

© 2016 Cadence Design Systems, Inc. All rights reserved.

Christian Malter

Director Technology Solutions & Business Development EMEA

Leuven

November 23, 2016

“Real Men Do ASICs!” How to reduce risk and cost of ASIC/SoC design


Big Trends Creating Opportunities

Sources: IBS August 2016; Gardner Dec 2015; Gardner Q2 2016, IHS Markit H1 2016

Cloud Computing

500 EB traffic in 2020

with 57% CAGR

Internetof Things

21B devices by 2020

with 34% CAGR

Autonomous Systems

Self-driving cars by 2020

with 19% CAGR

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.

1.9B smart phones in 2020

with 5.9% CAGR

Mobility

• More and more system companies pursuing vertical integration (developing their own SoCs)

• End devices require high compute performance in a small power and real estate envelope

• IoT creates plenty of opportunities for SMEs


What Keeps Your CEO Awake at Night?

Define a competitive product

Find a global, sustainable,

underserved, growing market

Ensure sustainable

differentiation

Reduce total cost

of ownership

Mitigate risks

Accelerate

time to market

Fingers crossed for you! ;-) Today‘s discussion


From Concept to Silicon to SystemConcept Phase

System architecture

System Integration

Functionality

HardwareSoftware

BOM

Power

SoC Development Phase

Design

Implementation

Verification

Traditional

EDA

ASIC/SoC

Software

Performance

You!

Cadence® System Design EnablementEDA tools, flows, methodologies, IP, services, ecosystem


• Do I go ASIC or COT? – And what‘s the difference?

• How can I get access to EDA tools cost efficiently?– Do I need to hire a CAD manager?

– What do I need in terms of IT infrastructure?

• Where are the biggest risks in my ASIC/SoC design?– And how can I mitigate them?

• Where should I hire, where should I use partners?

• Isn‘t this all too complex, risky, and costly?

Some Fundamental Questions You Might Have…


Do I Go ASIC or COT? And what is the difference?


System-Level Architecture

Software

Architecture

SoC Architecture

A Typical SoC Development Flow …

Hardware

Architecture

RTL DesignIP Sourcing and

Integration

HW/SW System Integration Validation

RTL-GDSII Implementation, DFT, ATPG

Physical Verification and GDSII Tapeout

Test Program Development and Support

SoC Functional Verification

Package DesignChip/Package/Board

Co-Verification

Analog/MS/RF Design

Mixed-Signal Verification

Wafer Manufacturing, Assembly, Test

Supply Chain Management

YOU

ASIC supplier

COTASIC

YOU


COT Means Higher NRE but Lower Part Price

COTASIC

NRE($M) BOM($)NRE($M) BOM($)

BOM:

Wafer cost / good dies per wafer

Package and assembly

Final test (Test Time)

IP royalties

Wafer probing (if appl.)

EDA tools

Services/SOWs

NRE:

IP license fees

Tooling: mask set,

package design,

load boards, etc.


Software

Architecture

SoC Architecture

Hardware

Architecture


Integration




Test Program Development and Support



Co-Verification

Analog/MS/RF Design





How Can I Get Access to EDA Tools Cost Efficiently?Do I need to hire a CAD manager? What do I need in terms of IT infrastructure?


Cadence Hosted Design Solution (HDS)

Customer site

Cadence

Managed CAD

and ITservices

Computeresources

Designdatabase

IT

Packaged design

environment with

software access

Cadenceremotedesktop

Design team

VPN

VPN

• Security to enterprise standards

• Dedicated power and cooling systems

• Redundant/reliable internet connection

• Disaster recovery capability ready/available

• Redundant and dedicated A/C units, generators

• Remote desktop machines

• Dedicated internet connection/VPN

• Pre-configured design environments

• EDA flows, libraries, techfiles, PDKs, etc…

• Cadence (and third-party software, if applicable)

• IP

• Dedicated compute servers

• Dedicated storage

• Dedicated CAD support!

• 24/7 IT support with guaranteed reaction times

Secure, scalable, reliable,

and reducing TCO!

Datacenter

http://images.google.com/imgres?imgurl=http://askbobrankin.com/raid-hard-drive-array.jpg&imgrefurl=http://askbobrankin.com/what_is_raid.html&h=304&w=304&sz=57&hl=en&start=71&sig2=uCazg-HrH6vzed1hGOPvOw&um=1&tbnid=CVI1PV1gkhryFM:&tbnh=116&tbnw=116&ei=uVmrSIX7CoO4iAHek-X9Dw&prev=/images?q=redundant+RAID+storage&start=63&ndsp=21&um=1&hl=en&safe=active&sa=N







Cadence HDS Business Model

Capital and Expenses

IT H

ard

ware

CAD and IT Staff

Classical EDA model

• HDS used today by small- and medium-sized companies

• Special startup packages available

Time

EDA Tools

Expenses

HDS SaaS model

Project-Based Expenses

- Flexible Packages -

TimeBaseline Need

EDA Tools and Flows

IT Support and CAD Management

IT Infrastructure


Integrated Toolchain for IoT DesignReadily available in HDS

System specifications

Virtuoso VSE

and ADE

Incisive/AMSD

Simulation and

Verification

Testbench

Analog Models

Low-power Intent

(CPF)

Verified Design

Virtuoso-VDI OA

Integrated Flow

Floorplanning

Analog

Block

Digital

Block

Chip Integration

Signoff

Synthesis and

Test

AMS IP

PMU

Radio

Sensor

Actuator

CPU/

DSP

Cu

sto

m L

og

ic


Where Are the Biggest Risks in my ASIC/COT Design?And how can I mitigate them?


Key Risks in ASIC/SoC Design

• Design complexity rising

• RTL-GDSII implementation

• One of the strongest SoC verification

methodology and services teams in the

industry

• RTL-GDSII implementation is a matter of

methodology, not just tools!

• Extensively stress test SoCs with software

tests before silicon goes into the fab

• Analog/mixed-signal/RF design and

verification is in the core of our DNA!

• Provides a broad IP portfolio with integration

support and subsystem capabilities

Cadence ExperienceRisk Area

• Hardware-software coherence

• Analog/mixed-to-digital interfacing

• IP integration


IPS

ub

syste

mS

oC

Fir

mw

are

/

Dri

ve

rs

OS

an

d

Mid

dle

wa

reA

pp

s

SiliconTime

Hard

ware

Soft

ware

Early Software Development

and Hardware/Software ValidationSystem

and Silicon

Validation

SoC/Subsystem

Functional Integration

and Verification

IP Design and

Verification

Hardware-Software CoherenceArchitecting, specifying, designing, integrating, and verifying SoC and subsystems, enabling end product hardware-software coherence

• System and SoC architects

• CPU subsystem architects

• IP subsystem integration and verification

• SoC verification

Key talent required:


Cadence System Development Suite for Concurrent Hardware/Software Design

Architectural

IntentRapid

Prototyping

Platform

Functional

Verification

Platform

Verification

Computing

Platform

Cadence System Development Suite

ASIC/SoC Development

Virtual

System

Platform

Software Development


Reasons for Re-Spins in Analog Mixed-Signal SoCs (2013)

Source: 2013 © Semico Research Corp. All Rights Reserved System(s)-on-a-Chip: Changes in SoC Design Methodology

1. Logic and functional errors

2. Clocking issues

3. Analog/MS – Digital interfaces

4. Crosstalk

5. Power management

6. Analog circuits

7. Yield/reliability

8. Timing

9. Firmware

10.IR drops


Core of Our DNA: Mixed-Signal Design and VerificationAdvanced methodology for AMS IP and SoC design, implementation, and verification

Digital Simulation

Virtuoso Analog Verification

Advanced

Mixed-Signal

Verification

Methodologies

Analog- and RF-CentricMetric-Driven Verification

Planning and Management

AMS Modeling RNM Simulation

Incisive Digital Verification

Performance Simulation Functional Verification

RNM Generation

MS Verification Management

Coverage

Metrics

UVM-MS Test

Development

Transistor Level

Analog: High accuracy, low simulation throughput Digital: Lower accuracy, high simulation throughput

Abstraction Level

Higher Quality of Results

More than 85% of SoC design starts are mixed signal (IBS, Jan 2014)


Cadence Provides Comprehensive IP Portfolio

®

®™


Cadence Can Develop Integration-Ready IP Subsystems

Cadence can develop

pre-integrated and validated

IP subsystems with

software drivers for validation

Reduced effort and improved time to market


Where Should I Hire, Where Should I Use Partners?


Cadence Collaboration Model Continuum

Enabling Collaborating Outsourcing

Transfer knowledge to you! We do it for you!

Methodology Services Design Services


Software

Architecture

SoC Architecture

Hardware

Architecture


Integration




Test Program Development Support



Co-Verification

Analog/MS/RF Design





Cadence Collaboration Model Continuum

Enabling Collaborating OutsourcingSystem-Level Architecture

Software

Architecture

SoC Architecture

Hardware

Architecture


Integration



Test Program Development Support




Co-Verification

Analog/MS/RF Design




Transfer knowledge to you! We do it for you!


Leverage the Breadth and Depth of Cadence Talent

SoC/system architects

Architectural explorer

PPA estimator

IP evaluator

Foundry process expert

Project manager

RTL developer

IP subsystem developer

Functional verifier

Performance modeler

DFT expert

RTL-GDSII implementer

Full custom designer

Analog/MS verification expert

RF design expert

Package layouter

Silicon/package/board co-designer

System integrator and bring-up expert

FPGA prototyping expert

Early software development platform builder

Foundry interfacer

Package house interfacer

Test house interfacerPlanning, Execution

Digital Design

AMS/RF DesignPackage/Board Design

System Hardware/Software Validation

Manufacturing1400+ field engineers

Firmware engineerSoftware Engineers

Methodology Services

EDA flows

Tools

IP

Design Services


Isn‘t This All Too Complex, Risky, and Costly?


A Strong Ecosystem that De-Risks Your ASIC/SoC Project

ARM TSMC

Cadence

You and your

ASIC/SoC3rd-Party

IP

Vendors

3rd-Party

EDA

Vendors

Package

House

Test

House


Less Risk and Cost with Cadence as Your Partner

• Deep understanding of ASIC/COT/SoC

design and supply chain

• System-level understanding spanning hardware

and software

• Leader in analog/mixed-signal/RF SoC design

solutions including MEMS

• HDS to reduce your TCO

• Design enablement where you want to

differentiate yourself

• Design Services where you need things done

• Broad IP portfolio with Tensilica and Interface IP

• Flexible business models for SMUs


© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks

are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI Express, PCIe, and M-PCIe are registered trademarks or trademarks of PCI-SIG. MIPI is a

registered trademark owned by MIPI Alliance. All other trademarks are the property of their respective holders.

“Real Men Do ASICs!” - NMI · “Real Men Do ASICs!” How to reduce risk and cost of ASIC/SoC...

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