Processors, FPGAs, and ASICs
Transcript of Processors, FPGAs, and ASICs
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Processors, FPGAs, and ASICsPart 1: Full Custom to PLDs
Stephen A. Edwards
Columbia University
Spring 2020
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Spectrum of IC choicesFlexible, efficient
Cheap, quick to design
Full Custom
ASIC
Gate Array
FPGA
PLD
GP Processor
SP Processor
Multifunction
Fixed-function
You choose
Polygons (Intel)
Circuit (Sony)
Wires
Logic network
Logic function
Program (e.g., ARM)
Program (e.g., DSP)
Settings (e.g., Ethernet Ctrl.)
Part number (e.g., 74HCT00)
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An N-Channel MOS Transistor
D S
G
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An N-Channel MOS Transistor
D S
G
Channel (p)
Gate
Oxide (SiO2)
Drain (n) Source (n)
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An N-Channel MOS Transistor
D S
G
Channel (p)
Gate
Oxide (SiO2)
Drain (n) Source (n)
3V
+
+ 0
Ammeter
Gate at 0V: Off
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An N-Channel MOS Transistor
D S
G
Channel (p)
Gate
Oxide (SiO2)
Drain (n) Source (n)
3V
+
+ 0
Ammeter
Gate at 0V: Off
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An N-Channel MOS Transistor
D S
G
Channel (p)
Gate
Oxide (SiO2)
Drain (n) Source (n)
3V
+
+ 0
Ammeter
Gate at 0V: Off
0V
+
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An N-Channel MOS Transistor
D S
G
Channel (p)
Gate
Oxide (SiO2)
Drain (n) Source (n)
3V
+
+ 0
Ammeter
Gate positive: On
3V
++++++++++
− − − − − − −−
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CMOS Inverter Layout
Cross Section Through N-channel FETA
Vss
Vdd
Y
Top View
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CMOS Inverter Layout
Y
Vss
Vdd
A
Cross Section Through N-channel FETA
Vss
Vdd
Y
Top View
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CMOS Inverter Layout
Y
Vss
Vdd
A
Cross Section Through N-channel FETA
Vss
Vdd
Y
Top View
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The CMOS NAND Gate
AB
Y
Two-input NAND gate:
two n-FETs in series;
two p-FETs in parallel
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The CMOS NAND Gate
AB
Y
Y
A
B
Two-input NAND gate:
two n-FETs in series;
two p-FETs in parallel
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The CMOS NAND Gate
AB
Y
Y
A
B
Two-input NAND gate:
two n-FETs in series;
two p-FETs in parallel
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The CMOS NAND Gate
AB
Y
Y
A
B
1
1
11
0
0
Both inputs 1:
Both n-FETs turned on
Output pulled low
Both p-FETs turned off
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The CMOS NAND Gate
AB
Y
Y
A
B
0
1
01
1
1
One input 1, the other 0:
One p-FET turned on
Output pulled high
One n-FET turned on, but does not controloutput
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The CMOS NAND Gate
AB
Y
Y
A
B
0
0
00
1
1
Both inputs 0:
Both p-FETs turned on
Output pulled high
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Full Custom: Intel 4004 Masks (2,250 Transistors)
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Full Custom: Intel 4004 Die Photograph
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Standard Cell ASICs
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StandardCellASICs
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ChanneledGateArrays
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ChanneledGateArrays
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Sea-of-GatesGateArrays
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FPGAs:Floorplan
DLL DLL
DLLDLL
BLO
CK
RA
MB
LOC
K R
AM
BLO
CK
RA
MB
LOC
K R
AM
I/O LOGIC
CLBs CLBs
CLBs CLBs
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FPGAs: CLB
I3
I4
I2
I1
Look-UpTable
D
CK
EC
Q
R
S
I3
I4
I2
I1
O
O
Look-UpTable
D
CK
EC
Q
R
SXQ
X
XB
CE
CLK
CIN
BX
F1
F2
F3
SR
BY
F5IN
G1
G2
YQ
Y
YB
COUT
G3
G4
F4
Carryand
ControlLogic
Carryand
ControlLogic
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FPGAs: Routing
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PLAs/CPLDs:The 22v10
0 4 8 12 16 20 24 28
Increments
FirstFuseNumbers
32 36 40
Macro-cell
R = 5809P = 5808
R = 5811P = 5810
R = 5813P = 5812
R = 5815P = 5814
R = 5817P = 5816
Asynchronous Reset
23
22
21
20
19
1
2
3
4
5
(to all registers)
396
0
440
880
924
1452
1496
2112
2156
2860
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
CLK/I
Macro-cell
Macro-cell
Macro-cell
Macro-cell