Analysis of the Switched-Capacitor Dual-Slope Capacitance-to-Digital Converter

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 5, MAY 2010 997

Analysis of the Switched-Capacitor Dual-SlopeCapacitance-to-Digital Converter

Boby George and V. Jagadeesh Kumar, Member, IEEE

AbstractA dual-slope capacitance-to-digital converter (CDC)that operates on the elements of a differential capacitive sensorand provides a digital output that is linearly proportional to thephysical quantity being sensed by the sensor is presented andanalyzed in this paper. The converter topology is so chosen thata linear digital output is obtained for not only a sensor possessinglinear inputoutput characteristics but also a sensor possessing in-verse characteristics. The digital output in the proposed converteris dependent only on, apart from the sensitivity of the sensor,a dc reference voltage. Hence, high accuracy and linearity areeasily obtained by employing a precision dc reference. Since theproposed CDC is based on the popular dual-slope analog-to-digitalconverter structure, it possesses all the advantages (resolution,accuracy, and immunity to noise and component parameter varia-tions) and limitations (requirement of auto-zero and low conver-sion speed) applicable to the dual-slope technique. A prototypebuilt and tested for a typical differential capacitive sensor with anominal capacitance value of 250 pF gave a worst-case error of lessthan 0.05%.

Index TermsCapacitance-to-digital converter (CDC), capaci-tive sensor, dual-slope digital converter, integrating type convert-ers, signal conditioning.

I. INTRODUCTION

FOR sensing displacement (linear and angular), pressure,and acceleration, capacitance-type sensors are widely em-ployed in the industry as they provide better resolution, sen-sitivity, and linearity compared with other types of sensors. Adifferential capacitive sensor has two sensing capacitances C1and C2 whose values change in proportion to the parameterbeing sensed, and the changes in C1 and C2 are normallyequal and opposite. Since the value of one of the capacitancesincreases and that of the second capacitance decreases in pro-portion to the parameter being sensed, differential capacitivesensors are also popularly known as pushpull-type capacitivesensors. A simplified electrical equivalent circuit of a typicaldifferential capacitive sensor is shown in Fig. 1. If the parameterbeing sensed alters the area between the plates of the sensor,

Manuscript received June 17, 2009; revised October 26, 2009. First pub-lished January 8, 2010; current version published April 7, 2010. The AssociateEditor coordinating the review process for this paper was Dr. Jerome Blair.

B. George is with the Institute of Electrical Measurement and MeasurementSignal Processing, Graz University of Technology, 8010 Graz, Austria.

V. Jagadeesh Kumar is with the Department of Electrical Engineering,Indian Institute of Technology Madras, Chennai 600 036, India (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIM.2009.2038000

Fig. 1. Electrical equivalent circuit of a differential capacitive sensor. C1 andC2 are the sensor capacitances. P , Q, and R are the terminals for externalconnection.

then such a capacitive sensor will possess a linear inputoutputrelationship, as given by the following:

C1 =C0(1 kx)C2 =C0(1 kx). (1)

Here, k is the transformation constant of the sensor, and C0 isthe nominal value of C1 and C2, when x, which is the physicalquantity being sensed, is zero. Alternatively, a capacitive sensorthat utilizes the distance between the plates as the transductionparameter will possess an inverse relationship, as given by thefollowing:

C1 =C0

(1 kx)C2 =

C0(1 kx) . (2)

To obtain a measurable output relative to the parameter beingsensed by a capacitive sensor, a signal-conditioning circuit thatconverts the variations in the sensor capacitances C1 and C2 toa proportional analog voltage or current is required [1], [2].

Digital instrumentation systems are preferred over analogsystems as they offer better user interface and excellent process-ing power. To interface a sensor to a digital instrumentationsystem, an analog-signal-conditioning circuit cascaded to ananalog-to-digital converter (ADC) is required. A typical ADCwill possess an analog part and a digital part. It would beadvantageous if the analog part of an ADC itself is designed toaccept the elements of a sensor and the ADC logic appropriatelymodified to provide a digital output directly proportional to theparameter being sensed. Such a scheme does not require a sep-arate analog-signal-conditioning unit. A direct digital convertersuitable for a differential resistive sensor has been reported [3].Methods based on a sigmadelta modulator [4], autoranging[5], and duty cycle variation [6] proposed earlier are suitableonly for a single-element-type capacitive sensor. A method suit-able for differential capacitive sensors has been proposed in [7].However, this method provides an output proportional to theratio of two capacitances, and hence, the operation of the method

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998 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 5, MAY 2010

Fig. 2. Schematic of the switched-capacitor DSCDC. C1 and C2 are thesensor capacitances, and VR is the dc reference voltage.

is limited to a small range of variations in the capacitancesof the sensor. A charge-balancing-type capacitance-to-digitalconverter (CDC) reported earlier employs a very complicatedswitching arrangement [8]. The successive approximation-typeCDC that uses the well-known successive approximation reg-ister structure requires a high-precision digital-to-analog con-verter [9]. ICs AD7746 and AD7747 marketed by AnalogDevices Inc. are CDCs that convert single or differential capac-itances to an equivalent digital output utilizing the sigmadeltaprinciple [10]. Since the output of AD7746/AD7747 is depen-dent on the nominal values of the sensor capacitances, as theydo not employ the ratiometric method, additional processingis required if an output directly proportional to the param-eter being sensed is required. Moreover, these ICs can acceptcapacitances only up to 21 pF and have an active but limitedcompensation range over which the effect of stray capacitanceson the output can be nulled.

A novel switched-capacitor dual-slope technique that con-verts the variations in the capacitances C1 and C2 of a dif-ferential capacitive sensor directly into a proportional digitalvalue based on a ratiometric approach was presented [11], andits performance is analyzed in this paper. The conversion timeof the proposed technique is 33% less than that of the triple-slope CDC reported earlier [12]. Apart from the increased speedof conversion, the proposed dual-slope CDC (DSCDC) offersadditional advantages, i.e., negligible sensitivity toward vari-ous error sources, such as stray capacitances, switch leakagecurrents, and opamp offset voltage, in comparison with thetriple-slope CDC. Moreover, this method requires only a singledc reference voltage and hence avoids errors arising out ofmismatched dc reference voltages (offset voltage) of oppositepolarity, which is a major source of error in the triple-slopeCDC scheme.

II. SWITCHED-CAPACITOR DSCDC

The functional block diagram of the proposed DSCDC isshown in Fig. 2. As in any dual-slope technique, the DSCDCis made of an integrator and a control and logic unit (CLU)incorporating an n-bit or N -digit timer counter. As indicatedin Fig. 2, the sensor capacitances C1 and C2 in combination

with three single-pole double-throw (SPDT) switches S1, S2,and S3, opamp OA and the feedback capacitor CF form aswitched-capacitor integrator. The status of the output of theintegrator is sensed by the comparator OC. If the output of theintegrator voi 0, then the output vc of the comparator willbe high; otherwise, the comparator output will be low. A high-to-low or low-to-high transition on vc indicates that the outputvoi is crossing through zero. The CLU senses output vc of thecomparator and controls the switches through control lines SC1,SC2, and SC3, and performs two integrations for a completeconversion. All the operational logic of the CLU is timed by aclock signal possessing a period TC and 50% duty cycle. Asin a conventional dual-slope ADC, the CLU of the DSCDCperforms an auto-zero function to force the integrator outputto zero to ensure an appropriate initial condition for initiating aconversion.

A. Auto-Zero Phase

The auto-zero ensures that the integrator output voltage voiis initialized to zero prior to the start of the first integrationperiod T1. Forcing the integrator output to become zero canalso easily be accomplished by shorting CF (discharging thefeedback capacitor) with a switch placed across it. However,such an arrangement will then introduce an error due to theoffset voltage of the comparator and is hence not preferred.The duration of the auto-zero cycle can be considerable at thestart of the first conversion cycle, but it can be as low as oneclock cycle from the second conversion cycle onward whenthe CDC is operated in a continuous conversion mode. In theauto-zero phase, the CLU senses the comparator output vc. Ifvc is high (integrator output voi 0), then the CLU logic isdesigned to set S1 and S2 to be in position 1 and S3 to be inposition 2 for a period TC/2 (whenever the clock is high) bysuitably controlling lines SC1, SC2, and SC3. When the clockturns low (at the end of TC/2), all three switches are toggledand kept in that position for the next TC/2. Thus, during thefirst TC/2, the capacitors C1 and C2 get charged to VR with thecharging current discharges CF . In the succeeding TC/2, C1and C2 are discharged and hence made ready for the chargingagain in the first half of the next clock cycle. Hence, for everyclock cycle, the output of the integrator voi ramps down with astep of v = VR(C1 + C2)/CF and reaches zero. Fig. 3 showsthe pertinent waveforms at cardinal points of the scheme. Whenvoi reaches zero, the comparator output vc will transit from highto low, signaling to the CLU that voi has reached zero and theCLU enters the conversion phase.

If, in the beginning, voi is negative, then vc will be low.In such a case, the CLU logic sets S1, S2, and S3 to be inposition 1 for a period TC/2, toggles all the switches, andkeeps them in the toggled position for the next TC/2. Hence,during the first half of the clock, C1 and C2 get charged toVR, and during the second half, they discharge to ground,drawing a charge of VR (C1 + C2) from CF . Hence, for everyclock cycle, the output of the integrator voi ramps up with astep of v = VR (C1 + C2)/CF and reaches zero. Once voibecomes zero, the comparator output vc will transit from lowto high, indicating to the CLU the end of the auto-zero phase.

GEORGE AND KUMAR: ANALYSIS OF SWITCHED-CAPACITOR DSCDC 999

Fig. 3. Integrator output voi and the comparator output vc for (solid line)C1 > C2 and (dotted line) C1 < C2. In the auto-zero phase, the integratorvoltage is assumed to be positive for C1 < C2, and vice versa. The assumptionis only to have a simple diagram, but, in reality, the auto-zero phase isindependent of the condition C1 < C2 or C1 > C2. Note that |C1 C2| ischosen to be different for two cases, i.e., C1 < C2 and C1 > C2, for easyvisualization.

Fig. 4. Flowchart of the auto-zero phase of the DSCDC.

A flowchart of the auto-zero phase of the DSCDC is shownin Fig. 4. After the auto-zero phase is completed, a conversioncycle is initiated.

B. Conversion Cycle

A typical conversion cycle consists of two time periods, i.e.,T1 and T2. While the period T1 is a preset value, T2 is measured.During T1, when the clock is high (TC/2), switch S2 is set atposition 2, and switches S1 and S3 are set to position 1. Whenthe clock turns low, switch S2 is changed to position 1, and S1and S3 are set to position 2. Thus, whenever the clock is high,C1 will charge to VR, and C2 will get discharged to ground. Assoon as the clock goes low, the charge in C1 will be transferredto CF , and at the same time, the charging current of C2 is also

sent into CF . Hence, the differential charge between VRC1 andVRC2, i.e., VR (C1 C2), will get transferred to CF for everyclock cycle. If C1 > C2, then voi ramps in the positive directionin steps of value VR (C1 C2)/CF for every clock period TC ,as indicated by the solid line in Fig. 3. On the other hand, ifC2 > C1, then voi will ramp in the negative direction in stepsof value VR (C2 C1)/CF for every clock, as indicated by thedotted line in Fig. 3. If C1 = C2, then the differential chargetransferred to CF for every clock is zero; hence, at the end ofT1 (= N1TC , with N1 being a preset integer), the output ofintegrator voi will remain zero.

The second integration period T2 commences as soon as theperiod T1 is completed. The CLU senses the output of thecomparator vc at the end of T1 and also starts an internal counterwhich is clocked by TC to measure T2. If vc is high at the endof T1 (i.e., C1 > C2), then the CLU switches S1 and S2 toposition 1 and S3 to position 2 whenever the clock is high andtoggles all three switches whenever the clock turns low. Thus,when the clock is high, both C1 and C2 will get charged to VR,and their charging currents will discharge CF by VR (C1 +C2). When the clock goes low, the sensor capacitances aredischarged to ground. This process is repeated for every clockcycle. Hence, the output of the integrator gradually decreases insteps of VR (C1 + C2)/CF and reaches zero. voi reaching zerois indicated to the CLU by a high-to-low transition on vc.

On the other hand, if vc is low at the end of T1 (i.e.,C2 > C1), then the CLU switches S1, S2, and S3 to position 1whenever the clock is high and changes all three to position 2whenever the clock turns low. Thus, when the clock is high,both C1 and C2 will get charged to VR. In addition, when theclock goes low, their net charge VR (C1 + C2) is transferred toCF , discharging it. Under this condition, voi increases in stepsof VR (C1 + C2)/CF and reaches zero, as indicated by thedotted line in Fig. 3. Here, voi reaching zero is indicated to theCLU by a low-to-high transition on vc. As soon as the transitionis sensed, the CLU stops the counter, and the count value, i.e.,N2, is taken as the output. A flowchart showing the sequenceof operations and switch positions set by the CLU during theperiods T1 and T2, depending on the comparator output voltagevc, is shown in Fig. 5. In either case, the time taken for voi toreach zero, i.e., T2 (vide Fig. 3), is measured by the CLU and isprovided as the final digital output. In all the cases, at the endof period T2, the net charge in CF is zero; hence, we get

VR

(C1 C2

CF

)T1TC

= VR

(C1 + C2

CF

)T2TC

. (3)

Rearranging the terms, we get

T2 =(

C1 C2C1 + C2

)T1. (4)

If the number of clock cycles in T1 and the number ofclock cycles measured during T2 are denoted as N1 and N2,respectively, then

N2 =(

C1 C2C1 + C2

)N1. (5)


Fig. 5. Flowchart showing the logic of the conversion phase.

Substitution of the values for C1 and C2, as given in (1), into(5) results in the following:

kx =N2N1

. (6)

It nicely turns out that substitution of the values for C1 andC2 for a sensor possessing inverse relationship, as given in(2), into (5) also results in (6). Hence, even if C1 and C2 aregoverned by the inverse relationship, as given in (2), the digitaloutput N2 is linearly related to x, as given in (6). The polarityof x is taken as positive if vc = 1 at the end of T1; otherwise,the polarity is treated as negative, as shown in Fig. 5.

Since N1 is a preset value and k is the sensors transformationconstant, the digital value N2 directly represents the quantityx being sensed by the sensor. Thus, the technique presentedhere implements a linear direct CDC applicable for not onlydifferential capacitive sensors possessing linear characteristicsbut also sensors possessing inverse characteristics without anychange.

The triple-slope method presented earlier takes a total timeperiod of 3N1TC for a full-scale conversion [12]. Comparedwith that method, in the present method, the total conversiontime is (T1 + T2), which works out to be 2N1TC for fullscale, thus providing 33% improvement in conversion speed.In the triple-slope CDC, two separate integration periods areemployed to get information proportional to (C1 C2) anda third integration period to obtain an output proportional to

Fig. 6. Circuit (part) of the DSCDC with all possible stray capacitances.

(C1 + C2). In the DSCDC, the information proportional to(C1 C2) is achieved in a single integration period, reducingthe overall number of integration periods from three to two. Asthe technique used for developing the proposed CDC is basedon the well-known dual-slope integrating type ADC principle[13], the DSCDC possesses features such as high repeatabilityin the output, even in the presence of high-frequency noise,very small nonlinearity errors, and very good rejection ofinterfering frequencies with periods of integral multiples of themeasurement period. Two opposing criteria, i.e., fast conversionand noise suppression, dictate the selection of T1. T1 should beas small as possible for fast conversion, whereas for suppressionof noise and interference, it should be as large as possible [14].Typically, with the proposed method, a conversion speed of afew conversions to a few hundred conversions per second isobtainable.

III. ERROR ANALYSIS AND DISCUSSION

The foregone discussions, analysis, and derivations on theoperation of the DSCDC assumed ideal conditions. Errorswould be introduced in the output due to circuit parameters,such as stray capacitances, switch delay, leakage current, chargeinjection, comparator delay, opamp offset voltage, opamp biascurrent, and ON resistances of the switches. The followingsections detail the effects of the aforementioned parameters onthe output of the proposed DSCDC:

A. Effect of Stray Capacitance on the OutputFig. 6 shows the sensor capacitances C1 and C2 with lead-to-

ground stray capacitances CGP, CGQ, and CGR. During periodT1, in every clock cycle, switch S1 is at position 1 for the initialTC/2; hence, along with C1, CGP also gets charged to VR.For the next TC/2, S1 is set to position 2. Since both the endsof CGP are at ground, it discharges to zero without affectingthe charge in CF . During T1, when S2 is set to position 1,the stray capacitance CGR will get charged to VR, but theresulting charging current does not flow through the feedbackcapacitor CF . When S2 goes to position 2, CGR will dischargeto ground. Node Q is always at virtual ground or circuit ground;thus, CGQ is always under short-circuit condition. During T2,depending on the condition C1 < C2 or C1 > C2, both the


Fig. 7. Few cycles of the switching sequence with the time delay d are shownfor the time periods T1 and T2.

switches S1 and S2 are operated in a similar manner, as wasdone during T1. Hence, stray capacitances CGP, CGQ, and CGRhave negligible effect on the circuits performance. However, alarge CGQ may influence the performance of opamp OA. High-accuracy differential capacitive sensors are always providedwith a guard ring to avoid effects due to fringing [1], [2].The guard ring and the fact that the common terminal is atthe ground potential preclude any stray capacitances betweennodes P and R on the transducer. However, stray capacitanceCPR can exist between nodes P and R due to cabling. DuringT1, when node P is at VR, the node R is at ground. Whennode P is at ground potential, the node R is at VR. Thus, thecharging and discharging currents of CPR will directly flowfrom VR to ground and will not affect the performance of thecircuit.

During T2, nodes P and R will be at the same potential;hence, cable capacitances CPR cannot contribute additionalcharge to the feedback capacitor. Thus, no additional error willoccur in the output of the proposed DSCDC, even if the straycapacitances are a few orders larger in value than the sensorcapacitances C1 and C2. Hence, the present method works wellfor differential capacitive sensors having a full-scale value ofa few femtofarads to a few thousand nanofarads. The value ofthe feedback capacitor CF must suitably be selected, dependingon the range of value of the capacitive sensor to be used,considering the output swing of the opamp OA.

B. Effect of Switch Delay and the Constraints Imposed on theSwitching Sequence

In a practical situation, switches S1, S2, and S3 can havemismatches in their propagation delay times (d). A mismatchin the delay times of the switches may cause unwanted anderroneous charging or discharging of the feedback capacitorCF . This problem can easily be solved by setting the switch S3to operate in advance, compared with the other two switches.During the period T1, as soon as the clock signal goes high,S3 is set to position 1, but the switches S1 and S2 are set topositions 1 and 2, respectively, after a minimum delay timed. Similarly, when the clock goes low, S3 is set to position2 with a time d in advance, before setting the switches S1 andS2 to positions 2 and 1, respectively. Similarly, during T2, theswitching sequence must also be nonoverlapping. A few typicalcycles of the switch control signals for periods T1 and T2 areshown in Fig. 7. The nonoverlapping switching process willensure that the charging and discharging of CF is as envisagedand without any errors.

Fig. 8. Circuit part of the dual-slope CDC showing the leakage currents of theswitches.

C. Influence of Switch Leakage Currents on the OutputAs shown in Fig. 8, the leakage current ILS1 exists between

nodes 1 and 2 of switch S1 as its node 1 is at VR and node 2is at ground potential. Similarly, the leakage current ILS2 ofswitch S2 flows between its nodes 1 and 2. However, for bothswitches S1 and S2, leakage currents flow from VR to groundand hence do not affect the operation of the DSCDC. In the caseof switch S3, its nodes 1 and 2 are at ground and virtual ground,respectively; hence, there will not be any leakage current. Thus,the performance of the present DSCDC is not affected by theleakage currents ILS1 and ILS2 of the switches.

When switch S1 is in position 2, leakage current ILC1 dueto the finite OFF resistance of the internal switching deviceconnected between node 1 and the common terminal P ofswitch S1 will flow to ground through P . Hence, the voltage ofthe common terminal P will be raised by ILC1RON1. Similarly,when switch S2 is in position 2, the voltage of the commonterminal Q will be ILC2RON2, instead of zero. Here, RON1and RON2 are the ON resistances of switches S1 and S2,respectively. Due to the fact that the ON resistances of theswitches are quite low, these voltages will have a negligibleeffect on the performance of the circuit. For clarity, only ILC2is shown in Fig. 8. For the prototype developed, ILC 100 pA,and RON 120 , leading to a voltage drop (ILCRON =)12 nV, which is negligible, compared with the uncertaintyof the reference voltage. Thus, the leakage currents flowingthrough the common terminal also have negligible effect on theperformance of the circuit.

D. Error Due to Delay in the Comparator

As shown in Fig. 9, the comparator delay is critical onlyat the end of period T2. Whenever voi crosses zero, there aretwo operations to be carried out during the second half ofthe clock period TC/2. These operations are given as follows:1) the transfer of charge from sensor capacitances to CF and2) the change of state of the comparator. Let ti be the timetaken for the transfer of charge. During the period ti, the sensorcapacitances discharge to zero, resulting in appropriate changein the output voi of the integrator. In the second part of theoperation, the comparator after a delay of seconds changes itsstate, as shown in Fig. 9 [15]. Thus, by taking into account the


Fig. 9. Output voltage of the integrator voi and comparator vc indicating theeffect of comparator delay. The dotted lines (voi and vc) show the theoreticaloutput, assuming ideal components. The solid waveforms of voi and vc indicatethe actual output owing to the finite ON resistances of the switches and the delayof the comparator.

Fig. 10. Effect of opamp and comparator offset voltages in the DSCDC.

preceding factors, the maximum clock frequency fC (= 1/TC)can be selected as fC < 1/2( + ti), so that the resulting error(/N2TC) is made negligible.

E. Effects Due to the Offset Voltages of Opampand Comparator

As shown in Fig. 10, the charging and discharging of thecapacitances are affected due to the offset voltage VOS1 ofopamp OA. In the presence of offset voltage VOS1 (assuming itto be a constant during a conversion cycle), the charge balanceequation (3) gets modified as

(VR VOS1) T1TC

(C1C2

CF

)=(

C1+C2CF

)(VR VOS1) T2

TC.

(7)

It is seen from the preceding expression; the offset voltageappears on both sides of the equation and hence gets canceledout. Hence, the offset voltage of OA has negligible effect onthe output, provided the drift in VOS1 is negligible during aconversion cycle (1.3 V/C for the OP07 used in the proto-type [16]).

Sensing of the integrator output reaching zero is affected if anoffset voltage, e.g., VOS2, is present in the comparator. In sucha case, the comparator will change state when the integratorvoltage reaches VOS2, instead of zero. As long as the change ofstate in either direction happens at VOS2, instead of zero, errorswill not be introduced in T1 or T2; hence, the output of theDSCDC will not be affected. A change of VOS2 in VOS2,during conversion, leads to an error of (VOS2CF /2VRC0)counts in N2, where C0 = (C1 + C2)/2. For the prototype witha VOS2 = 5 V, this error is found to be negligible.

F. Influence of Opamp Bias Current on the OutputThis section discusses the effect of bias current drawn by the

input terminals of opamp OA, when a practical opamp is used.The bias current of the noninverting terminal of the opamphas negligible effect on the CDC, as it is directly connectedto the circuit ground. Whenever the switch S3 is in position 1,the bias current IB drawn by the inverting terminal of theopamp OA (shown in Fig. 8) will alter the charge stored in CF .When S3 is in position 2, the capacitor CF will be chargedby the current (Ich IB), instead of Ich. Thus, the currentIB alters the charge in CF by IBTCN1 during the period T1.Hence, the time period T2 will get altered. If the directions ofthe bias current IB and the charging current Ich are different,then additional charge will be added during T1, and T2 will beextended to discharge the extra charge (IBTCN1) accumulatedduring T1 and the additional charge that will continually beadded by IB , i.e., (IBTCN2) during T2. If the directions ofIB and Ich are the same (as shown in Fig. 8), then T2 will getshortened. The number of clocks by which T2 will differ fromthe expected value (the error introduced in N2 in counts) dueto the opamp bias current will be (IBTC/2VRC0)[N1 + N2].For the prototype developed, this works out to be 0.5 counts.This effect can be made negligible by choosing the minimumcharging current (the current that transfers the charge from thesensor capacitance to CF ) Ich|min ( 2VR(C1, C2)min/TC) tobe several orders of magnitude higher than the opamp biascurrent IB .

G. Effects of ON Resistances of the SwitchesSince the sensor capacitances are very small in value (femto-

farad to picofarad) and the ON resistances of the switches S1,S2, and S3 are in the range of a few ohms, the charging anddischarging time constants are very small. Thus, an appropri-ate selection of clock frequency makes the error introducedby the ON resistances of the switches negligibly small. Theselection of switches with low ON resistance becomes moreimportant as far as the stray capacitances are concerned. Toachieve negligible effect for large values (on the order of a fewhundred nanofarads) of stray capacitances, the ON resistance


of the switches must be low enough, so that the charging anddischarging time constants for the stray capacitance CGP andCGR are very low, compared with half of the clock time period(TC/2).

H. Influence of Noise and Charge Injection Due toExternal Interference

The main sources of noise in the DSCDC are the resistances(specifically, ON resistances) of switches, opamp OA, and com-parator OC. Since noise is random in nature, the noise voltage isalways expressed in terms of the mean-square value of the noisevoltage. When the switches are under conditions S1 = S3 = 1and S2 = 2, along with the charging from the reference voltage,the sensor capacitance C1 will also be charged to the equivalentvalue of the thermal noise voltage of the switches S1 and S3.The noise voltage acquired by C1 under this condition is takenas v2c1,1. When the switches are under conditions S1 = S3 = 2and S2 = 1, C1 will additionally get charged from the thermalnoise sources of S1 and S3 and the input noise voltage ofopamp OA. The acquired noise due to the thermal noise ofthe switches is denoted as v2c1,2, and that of opamp is denotedas v2c1,op. Hence, the total noise voltage v2c1 in C1 is given byv2c1 = v

2c1,1 + v

2c1,2 + v

2c1,op. (The mean square noise voltages

are simply added as they are uncorrelated.) When the switchesare under conditions S1 = S3 = 2 and S2 = 1, the charge inC1 will be transferred to CF . Thus, CF will get a noise chargeq2CF |C1 = C21 v2c1 by the end of a full clock cycle, and thecorresponding integrator output noise voltage is C21 v2c1/C2F .The value of (v2c1,1 + v2c1,2) is 2kT/C1 [17], where k is theBoltzmann constant (k = 1.38 1023 J/K) and T is the ab-solute temperature in Kelvin. Thus, the noise charge transferredto CF by C1 is q2CF |C1 = 2kTC1 + C21 v2c1,op. A similar ex-pression can be derived for the noise charge transferred byC2CF ; hence, the total noise charge q2CF = 2kT [C1 + C2] +C21 v

2c1,op + C

22 v

2c2,op, where v2c2,op is the mean square noise

voltage acquired by C2 due to the input opamp noise source.The overall noise voltage that affects the CDC is the sumof the noise voltages present in the integrator output and theinput terminal of the comparator (v2oc). The noise voltage at theintegrator output is the sum of the noise voltages in CF andinput terminal of the opamp v2op. Thus, the overall noise v2ONcan be written as

v2ON=1

C2F

[2kT (C1+C2)+C21 v

2c1,op+C

22 v

2c2,op

]+v2op+v

2oc.

(8)Equation (8) shows that the mean square noise voltage is

proportional to (1/C2F ). This fact should also be consideredwhile selecting the value of CF . The feedback capacitor shouldalso have a low voltage coefficient, low temperature coefficient,low dielectric absorption, and low leakage current [14]. Poly-carbonate, polypropylene, and polystyrene capacitor types aresuitable for this application.

Charge injection effects at nodes 1 and 2 of the switches S1and S2 will not affect the performance of the circuit as node 1is connected to a voltage source and node 2 is tied to the circuitground. Charge injection due to an external interference will

not affect the common terminals (P or Q) of the switches S1and S2 whenever the switches are in position 1 or 2. SinceSPDT switches are normally of break-before-make type, for abrief period, the common terminal of the SPDT will be floating(connected to neither position 1 nor position 2) [18]. During thisperiod, the common terminal is susceptible to charge injectionfrom an external interference. In the proposed CDC, the effectdue to this will be small, as the time window in which the chargeinjection can take place is a few tens of nanoseconds in a clockperiod of a few tens of microseconds. Even this small effectcan further be minimized by choosing S1 and S2 to be nearlyidentical. In such a case, the injected charge in C1 will cancelthat injected in C2 since both the SPDT switches S1 and S2 areoperated through the same control signal.

I. Uncertainty in DC Reference VoltageThe proposed DSCDC uses only one dc reference voltage VR

and thus eliminates a possible significant error due to mismatchin reference voltages present in the triple-slope method [12].Since VR appears on both sides of (3), the output of theproposed DSCDC will be affected only if VR changes duringthe conversion cycle. Worst case error occurs if the referencevoltage is (VR VR) during T1 and (VR VR) during T2.Under such a condition, (3) will get modified as(VR VR)N1(C1 C2) = (C1 + C2)(VR VR)N2 orN2 = N1kx (VR/VR) (N1kx + N2). (9)This shows that there will be an error of

(VR/VR)(N1kx + N2) counts in the output. For theprototype developed, a precision dc reference voltage of1.235 V 100 V was used, leading to a worst case error oftwo counts in the output. An accurate output requires the useof a precision and stable dc voltage as reference.

J. Resolution

The CLU sets the number of clocks during T1 as N1, whereasN2 during T2, as given by (5), may not always be an integer.This will introduce an error of 1 count in the output. For afull scale of 20 000 counts, the error due to quantization worksout to be 0.005%, which is the least significant bit and, hence,the resolution of the CDC.

IV. EXPERIMENTAL SETUP AND RESULTS

To validate the proposed technique, the scheme was firstsimulated in SPICE. Components and ICs that are equivalent tothat used for the prototype were chosen to simulate the DSCDC.The output and error characteristics, which were obtained fromSPICE simulation, for variation of kx between .52 and +.52in steps of 0.04 for a sensor with C0 = 250 pF possessinglinear characteristic, as given in (1), are shown in Fig. 11. Theperformance of the DSCDC for a sensor with C0 = 250 pF andpossessing inverse characteristic as in (2) is shown in Fig. 12.The worst-case error noted from the simulation studies was lessthan 0.03%.


Fig. 11. Results from SPICE simulation for a sensor with linear characteristic.

Fig. 12. Results obtained from SPICE simulation for a sensor with inversecharacteristic.

To check the practicality of the proposed DSCDC, a proto-type unit was built and tested. Precision reference voltage VRwas derived using an LM 385 1.2-V reference diode. CD4053IC was used to realize switches S1S3. OP07 served as theopamp OA. The comparator was accomplished with LM311.The value for CF was chosen to be 0.68 F. The CLU wasrealized with a PIC16F877A microcontroller [19]. A suitableprogram was written and burnt into the microcontroller torealize the logic of the CLU to control the analog switches,generate N1 clocks during T1, count N2 clocks during T2, anddisplay the output as N2. The clock frequency was chosen to be300 kHz, resulting in a conversion speed of 10 conversion/s.The prototype was tested with sensors possessing linear andinverse characteristics.

To verify the performance of the prototype circuit, a con-trolled standard capacitance input is given by suitably adjust-ing two standard capacitance boxes manufactured by Neptun,Geretsried, Germany, and possessing 0.01% accuracy. Thenominal values of the capacitances C1 and C2 were chosen tobe 250 pF, and the variations were limited to 130 pF in stepsof 10 pF. Fig. 13 shows the test results, wherein the outputand error characteristics of the prototype DSCDC are given.

Fig. 13. Actual output and error characteristic obtained from the prototypeDSCDC.

The output was linear for the entire range tested. Worst-caseerror was found to be less than 0.05% of reading. These resultsestablish the efficacy of the proposed method.

The performance of important signal-conditioning methodssuitable for differential-type capacitive sensors proposed earlier[20][24] is compared with that of the proposed DSCDC inTable I. It is seen from Table I that the proposed method doesnot suffer from the common sources of errors, i.e., parasiticcapacitances and mismatch in reference voltages at the sametime, providing equal or better performance characteristics,compared to the existing methods. The proposed dual-slopeCDC being tested with a differential capacitive angle sensor isshown in Fig. 14.

V. CONCLUSION

A simple high-accuracy switched-capacitor dual-slope digi-tal converter suitable for differential capacitive sensors has beenpresented. In the presented scheme, the sensor capacitancesbecome an integral part of a dual-slope converter, and theconverter logic has been chosen, such that it provides a digitaloutput directly proportional to the parameter being sensed bythe sensor. The proposed DSCDC is based on the popular dual-slope ADC structure and hence possesses all the advantages,such as high resolution, accuracy, and immunity to noise andcomponent parameter variations. Normally, sensors operatein a noisy environment, and the inherent noise suppressioncapability of integrating-type digital converters is well suitedfor such applications.

An added advantage of the proposed method is that a linearoutput characteristic is obtained for not only sensors possessinglinear characteristics but also sensors having inverse character-istics, without any change in the either topology or logic. Theeffects owing to nonidealities such as stray capacitances, com-parator delay, switch leakage currents, opamp offset current,finite clock frequency, bias current of the opamp, and the ONresistances of the switches are analyzed. It is found that straycapacitance and comparator offset have a negligible effect onthe output. The criteria for the selection of active and passivecomponents and clock frequency that make the effects due to


TABLE IRATIO-METRIC SIGNAL-PROCESSING METHODS FOR CAPACITIVE SENSORS

Fig. 14. Experimental setup of the dual-slope CDC with a differential capac-itive angle sensor.

other parameters negligible were identified. Conversion timefor the proposed scheme is as good as a typical dual-slope ADC,and the proposed technique promises high accuracy since theoutput is dependent only on a single dc reference voltage otherthan the sensor transduction parameter. Results obtained fromsimulation studies and on a prototype developed and testedvalidate the practicality of the DSCDC. Both in simulationand prototype, the output was found to be linear for the entirerange, and the worst case error of the prototype was found to beless than 0.05% of the reading. The proposed CDC scheme iswell suited for signal conditioning of capacitive-type pressuresensors, inclinometers, and rotational angle sensors.

REFERENCES[1] E. O. Doebelin, Measurement SystemsApplication and Design, 5th ed.

New York: McGraw-Hill, 2004.[2] H. K. P. Neubert, Instrument TransducersAn Introduction to Their

Performance and Design, 2nd ed. London, U.K.: Oxford Univ. Press,2003.

[3] E. W. Owen, An integrating analog-to-digital converter for differentialtransducers, IEEE Trans. Instrum. Meas., vol. IM-28, no. 3, pp. 216220,Sep. 1979.

[4] J. M. G. Cama, S. A. Bota, E. Montane, and J. Samitier, A MOSFET-onlysecond order Delta-Sigma modulator for capacitive sensors interfaces, inProc. IEEE ICECS, Pafos, Cyprus, Sep. 1999, pp. 16891692.

[5] K. Kazuyuki and K. Watanabe, An auto ranging switched-capacitoranalog-to-digital converter, IEEE Trans. Instrum. Meas., vol. IM-36,no. 4, pp. 879881, Dec. 1987.

[6] Z. Ignjatovic and M. F. Bocko, An interface circuit for measuring capac-itance changes based upon capacitance-to-duty cycle (CDC) converter,IEEE Sensors J., vol. 5, no. 3, pp. 403410, Jun. 2005.

[7] B. Wang, T. Kajita, T. Sun, and G. Temes, High accuracy circuits for on-chip capacitance ratio testing and sensor readout, IEEE Trans. Instrum.Meas., vol. 47, no. 1, pp. 1620, Feb. 1998.

[8] H. Matsumoto, H. Shimizu, and K. Watanabe, Switched-capacitorcharge-balancing analog-to-digital converter and its application to capac-itance measurement, IEEE Trans. Instrum. Meas., vol. IM-36, no. 4,pp. 873877, Dec. 1987.

[9] P. D. Dimitropoulos, D. P. Karampatzakis, G. D. Panagopoulos, andG. I. Stamoulis, A low-power/low-noise readout circuit for integratedcapacitive sensors, IEEE Sensors J., vol. 6, no. 3, pp. 755769, Jun. 2006.

[10] Data Sheet, AD7745/AD7746, 24-Bit Capacitance-to-Digital ConverterWith Temperature Sensor, Norwood, MA: Analog Devices, Inc. [Online].Available: http://www.analog.com

[11] B. George and V. J. Kumar, Novel switched-capacitor dual slope ca-pacitance to digital converter for differential capacitive sensors, in Proc.IEEE I2MTC, Singapore, May 2009, pp. 14.

[12] B. George and V. J. Kumar, Switched-capacitor triple slope capacitanceto digital converter, Proc. Inst. Elect. Eng.Circuits, Devices Syst.,vol. 153, no. 2, pp. 148152, Apr. 2006.


[13] E. R. Hnatek, A Users Handbook of A/D and D/A Converters.Melbourne, FL: Krieger, 1988.

[14] Application note, 1999, AN017, The Integrating A/DConverter (ICL7135), Milpitas, CA: Intersil Americas Inc., 2002.[Online]. Available: http://www.intersil.com/data/an/an017.pdf

[15] Datasheet, LM111/LM211/LM311, Voltage Comparator, SantaClara, CA: Nat. Semicond. Corp., 2000. [Online]. Available:http://www.national.com/ds/LM/LM311.pdf

[16] Datasheet, OP07, Ultra Low Offset Voltage Operational Ampli-fier, Norwood, MA: Analog Devices, Inc., 2003. [Online]. Available:http://www.analog.com/UploadedFiles/Data_Sheets/OP07.pdf

[17] R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, Design-orientedestimation of thermal noise in switched-capacitor circuits, IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 52, no. 11, pp. 23582368, Nov. 2005.

[18] Datasheet, Max333A, Precision, Quad, SPDT, CMOS Analog Switch,Sunnyvale, CA: Maxim Integr. Products, 1999. [Online]. Available:http://datasheets.maxim-ic.com/en/ds/MAX333A.pdf

[19] Data Sheet, PIC16F87XA, 28/40/44-Pin Enhanced FlashMicrocontrollers, Chandler, AZ: Microchip Technol. Inc., 2003. [Online].Available: http://ww1.microchip.com/downloads/en/DeviceDoc/39582b.pdf

[20] L. K. Baxter, Capacitive Sensors Design and Applications. New York:IEEE Press, 1997.

[21] K. Mochizuki, K. Watanabe, T. Masuda, and M. Katsura, A relaxation-oscillator-based interface for high accuracy ratiometric signal process-ing of differential-capacitance transducer, IEEE Trans. Instrum. Meas.,vol. 47, no. 1, pp. 1115, Feb. 1998.

[22] K. Mochizuki, T. Masuda, and K. Watanabe, An interface circuit forhigh-accuracy signal processing of differential-capacitance transducers,IEEE Trans. Instrum. Meas., vol. 47, no. 4, pp. 823827, Aug. 1998.

[23] N. M. Mohan, A. R. Shet, S. Kedarnath, and V. J. Kumar, Digital con-verter for differential capacitive sensors, IEEE Trans. Instrum. Meas.,vol. 57, no. 11, pp. 25762581, Nov. 2008.

[24] B. George and V. J. Kumar, Switched capacitor signal conditioning fordifferential capacitive sensors, IEEE Trans. Instrum. Meas., vol. 56,no. 3, pp. 913917, Jun. 2007.

Boby George was born in Kannur, India, in 1977.He received the M.Tech. and Ph.D. degrees in electri-cal engineering from Indian Institute of Technology(IIT) Madras, Chennai, India, in 2003 and 2007,respectively.

He is currently a Postdoctoral Fellow with the In-stitute of Electrical Measurement and MeasurementSignal Processing, Graz University of Technology,Graz, Austria. His research interests include sensorsand electronic instrumentation.

V. Jagadeesh Kumar (M96) was born in Madras,India, on July 21, 1956. He received the B.E. degreein electronics and telecommunication engineeringfrom the University of Madras, Madras, in 1978and the M.Tech. and Ph.D. degrees in electricalengineering from Indian Institute of Technology,(IIT) Madras, Chennai, India, in 1980 and 1986,respectively.

He is currently the Head of the Department ofElectrical Engineering, IIT Madras. During 1999, hewas a Visiting Scientist with the Technical University

of Aachen, Aachen, Germany. In the summer of 1999, he taught for a term atthe Asian Institute of Technology, Bangkok, Thailand. He has published morethan 40 papers in international journals and presented more than 60 papers atvarious conferences. He is the holder of six patents. His teaching and researchinterests are measurements, instrumentation, and signal processing.

Dr. Kumar was a BOYSCAST Fellow with the Kings College London,London, U.K., during 19871988, and a DAAD Fellow with the TechnicalUniversity of Braunschweig, Braunschweig, Germany, during 1997.

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Analysis of the Switched-Capacitor Dual-Slope Capacitance-to-Digital Converter

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