Analysis of Isolated Two -Transistor Zeta Converter · simulation study of Zeta converter in open...

Analysis of Isolated Two-Transistor Zeta Converter

1Dr.V.Jayalakshmi,

2Sujeet Kumar

1Associate Professor,

2UG Student

Department of EEE

BIHER, BIST, Bharath University

Chennai- 600073.

[email protected]

ABSTRACT

In this paper a two-transistor Zeta-flyback DC-DC converter along with experimental results is

introduced. The proposed converter topology is the extension of the single-transistor Zeta-

flybackconverter.The system consists of a Zeta converter associated with a full bridge inverter

operating at low frequency. The Zeta converter, operating in discontinuous conduction mode

(DCM), plays the main role in this arrangement, producing a rectified sinusoidal current

waveform synchronized with the electric grid. The full-bridge inverter, connected with the Zeta

converter, provides de AC conversion inverting the current each half cycle. Initially it is

presented the analysis of the Zeta converter operating in DCM, as well as a design criterion.

Finally, the control strategy and experimental results for the proposed system are presented and

discussed.

Keywords:Zeta converter, continuous conduction mode (CCM),Discontinuous conduction

Mode(DCM)

1.INTRODUCTION

A Zeta converter is a fourth-order DC-DC converter made up of two inductors and two

capacitors and capable of operating in either step-up or step-down mode. Compared with other

converters in the same class, such as Cuk and SEPIC converters, the Zeta converter has received

the least attention, and more importantly, its dynamic modeling and control have never been

reported before in the literature.Similar to the SEPIC DC/DC converter topology, the ZETA

converter topology provides a positive output voltage from an input voltage that varies above and

below the output voltage.[1-5] The ZETA converter also needs two inductor sand a series

capacitor, sometimes called a flying capacitor. Unlike the SEPIC converter, which is configured

with a standard boost converter, the ZETA converter is configured from a buck controller that

drives a high-side PMOS FET.The ZETA converter is another option for regulating an

International Journal of Pure and Applied MathematicsVolume 119 No. 12 2018, 7927-7940ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

7927

unregulated input-power supply, like a low-cost wall wart. To minimize board space, a coupled

inductor can be used. This article explains how to design a ZETA converter running in

continuous-conduction mode (CCM) with a coupled inductor. This brief introduces an isolated

two-switch Zeta dc-dc converter, along with the steady-state analysis and experimentation. The

high transistor voltage stress due to the ringing caused by the resonance of the transformer

leakage inductance and the transistor output capacitance is a major drawback in the conventional

isolated Zeta converter. [6-9]With the incorporation of an additional transistor and two clamping

diodes on the primary side of the transformer of the isolated Zeta converter, an isolated two-

transistor Zeta converter is proposed. In the proposed converter, the voltage stress of both

transistors is reduced to the dc input voltage VI. Experimental results from a laboratory prototype

is presented to validate the theoretical analysis[10-12]

2.BLOCK DIAGRAM

Figure 1 BLOCK DIAGRAM

2.1 ZETA CONVERTER

International Journal of Pure and Applied Mathematics Special Issue

7928

Figure 2-Zeta Converter

2.2 Principle of operation

When analyzing Zeta waveforms it shows that atequilibrium, L1 average current equals IIN and

L2average current equals IOUT,[13-17] since there is no DCcurrent through the flying capacitor

CFLY. Also thereStage-1[M1ON]

Figure 3-Zeta converter during MOSFET ON time

The switch M1 is in ON state, so voltages VL1 andVL2 are equal to Vin. In this time interval

diode D1 isOFF with a reverse voltage equal to - (Vin + VO).Inductor L1 and L2 get energy

from the voltagesource, and their respective currents IL1 and IL2 areincreased linearly by ratio

Vin/L1 and Vin/L2respectively. Consequently, the switch currentIM1=IL1+IL2 is increased

linearly by a ratio Vin/L,where L=L1.L2/ (L1+L2). At this moment, dischargingof capacitor Cfly

and charging of capacitor C0take place.[19-24]

Stage-2 [M1 OFF]

In this no DC voltage across either inductor. Therefore,CFLY sees ground potential at its left

side and VOUT atits right side, resulting in DC voltage across CFLYbeing equal to VOUT.


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Figure 4 -Zeta converter during Mosfet OFF time

In this stage, the switch M1 turns OFF and thediode D1 is forward biased starting to conduct.

Thevoltage across L1 and L2 become equal to –Voand inductors L1 and L2 transfer energy to

capacitorCfly and load respectively. The current of L1 andL2 decreases linearly now by a ratio –

V0/L1 and –V0/L2, respectively.[25-29]The current in the diodeID1=IL1+IL2 also decreases

linearly by ratio –V0/L. Atthis moment, the voltage across switch M1 isVM=Vin + V0. Figure 4

shows the main waveformsof the ZETA converter, for one cycle ofoperation in the steady state

continues mode.

2.3 DESIGN OF COMPONENTS OF ZETA

CONVERTER [3]

A ZETA converter performs a non-invertingbuck-boost function. For a ZETA converter

operatingin CCM, the duty cycle is defined as

To determine the value of inductances L1 andL2 the peak-to-peak ripple current is taken

approximately 10-20% of the average output current.The value of these inductances may be

expressed as,

The coupling capacitor (C1) is designed on thebasis of its ripple voltage. The maximum voltage

handled by a coupling capacitor (C1) is equal to inputvoltage. It can be estimated as


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The output capacitor (C0) must have enoughcapacitance to maintain the dc link voltage and

musthave to provide continuous load current at highswitching frequency. [21-29]It can be

calculated as:

where, D is duty cycle, Vo is dc link voltage, Vin isrms value of the input voltage,[30-37] Io is

output ratedcurrent, fs is switching frequency, AVc1 is the ripplevoltage of the coupling

capacitor, AVco is the ripplevoltage of the output capacitor.

3. SIMULATION RESULTS

3.1 Conventional Single switch zeta converter

Figure 5 simulation circuit of Conventional Single switch zeta converter

System behaviorand performance can be predicted with the help of the simulation. To verify and

investigate the design and performance of the conventional single switch zeta converter, a

TX1

TN33_20_11_2P90

D4

1N4500

12

C2

10u

M1

IRF840

D2

1N4500

12

V2

TD = 0

TF = 1nsPW = 5uPER = 10u

V1 = 0

TR = 1ns

V2 = 5v

0

D3

1N4500

12

D1

1N4500

12

V1

FREQ = 50hzVAMPL = 20vVOFF = 0

0

C1

10u

L2

10uH

1

2

R1

100k

V-

V+

R2

100k

L3

10uH

1 2

D5

1N4500

12


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simulation study of Zeta converter in open loop is performed for input[31-36] AC voltage of 20V

at 50Hz with R load. Power circuit of Zeta converter with open loop is shown in figure5.Output

voltage, output current and are shown in fig 8,&10 respectively

Output voltage waveform

Figure 6 Output voltage waveform

Current waveform

Figure 7 Current waveform

3.2 Proposed Circuit Diagram

To verify and investigate the design and performance of the proposed zeta converter, a

simulation study of Zeta converter in open loop is performed for input DC voltage of 50V at

with R load. Power circuit of Zeta converter with open loop is shown in figure5. Input voltage

current, pulse waveform,transformer [38-40]primary and secondary voltage , Output voltage,

output current and are shown in fig 8,&10 respectively


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Figure 8 Proposed Circuit Diagran

Input Voltage

Figure 9 Input Voltage Wave form

Triggering Pulse

Figure 10 Triggering pulse

M2

IRF840

C3

700u

M3

IRF840

0

V-

V3

TD = 0U

TF = 1NPW = 5UPER = 10U

V1 = 0

TR = 1N

V2 = 5

TX1

TN33_20_11_2P90

V2

TD = 0

TF = 1NPW = 5U

PER = 10U

V1 = 0

TR = 1N

V2 = 5

V+L2

1m

1

2

D1

MUR150

0

R2

.001

I

D17

MUR150

L1

10uH

1 2

D2

MUR150

L3

10u

1 2V1

50V

R1

3

C1

10u


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Transformer Primary

Figure 11 Transformer primary waveform

Transformer Secondary

Figure 12 Transformer Secondary

Output Voltage And Current


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Figure 13 Output voltage and current waveform

4. HARDWARE CIRCUIT

Experimental results are presented in thissection to show the validity of the proposed method,

and an experimental prototype of the pulse-widthmodulated zeta power factor correction

converter hasbeen constructed.[28-30] The experimental setup withdetailed specifications are

shown in fig28.74HC244 isused as the driver circuit.PICpic12c508 is used as theprocessor. A pi-

filter is added to avoid control errorcaused by the switch noise.[31-45]

Figure 14 Hardware circuit diagram

HARDWARE KIT

78121 3

2

VIN VOUT

GN

D

22

12

0

U2

74HC244

10

202

4 18

16

GND

VCC1A1

1A21Y1

1Y2

TX1

230-1

5V

-500m

A

D2

MUR150

TX1

230-1

5V

-500m

A

1 2

220 TO 1K

1 2

1 2

22

D7

LED

1 2

12

10

00

U-3

5V

78121 3

2

VIN VOUT

GN

D

10U

D1

MUR150

10U

0

78051 3

2

VIN VOUT

GN

D

C1

10u

1 2

TX1

TN33_20_11_2P90

10k

1 2

L3

10u

1 2

10

00

U-3

5V

M3

IRF840

D17

MUR150

12

U7

PIC12C508/SO

1

467

VDD

GP3/MCLR/VPPGP1GP0

M2

IRF840

220 TO 1K

D7

LED

C3

700u

10k

U4

MCT2E

10

00

U-3

5V

L2

1m

1

2

12

12

U4

MCT2E

V1

50V

L1

10uH

1 2

R2

.001

220 TO 1K

R1

3

D7

LED

TX1

230-1

5V

-500m

A

12

10U


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Figure 15 Hardware kit diagram

CONCLUSION

The conventional and proposed methods have been analyzed and discussed with advantages and

disadvantages of each method. Simulation of both conventional and proposed method has been

presented. Theprototype hardware has been designed and implemented for the proposed method.

Finally Simulation output and the hardware output of the proposed method has been verified and

compared.

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