Analog Elec EDB2034 Jan 2016 - MOSFET - Intro Biasing.pdf

7/26/2019 Analog Elec EDB2034 Jan 2016 - MOSFET - Intro Biasing.pdf

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MOS Field-Effect Transistors (MOSFETs)

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EDB 2034

Analogue Electronics (Jan 2016 Semester)MOS Field-Effect Transistors (MOSFET)Intro & Biasing

Lecturer: Saiful Azrin bin Mohd ZulkifliPhone: 05-368 7852

Email: [email protected]


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Coverage :

Introduction to MOSFETs

Derivation of iDv

DSRelationship

MOSFET Current-Voltage Characteristics

Summary of MOSFET Current-VoltageCharacteristics

MOSFET Circuit at DC


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Introduction

Three-terminal devices (Gate, Drain, Source). Most widely used electronic devices as ICs. Current flow in longitudinal direction S to D. Fabricated on a single silicon chip. Symmetrical device (S D) Small in sizes compared to BJT.

Focusing on Enhancement-typeof MOSFET. TWO types: n-channel & p-channel. For n-channel MOSFET :

Fabricated on p-type substrate Two heavily doped n+created namely source

and drain Thin insulator (SiO2) between Gate to

substrate (tox250 nm) 4 Metal contacts deposited for

connection (G, S, D, B) Polysilicon contact is now used

as gate electrode


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Introduction : MOSFET Operations

No Gate Voltage :

With no bias voltage to the gate, two back toback diodes exist in series between drain andsource. Prevent current conduction from drain to

source when vDSis applied.

n-channel MOSFET


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Creating a Channel For Current Flow:

S and D are grounded. Positive voltage applied to the Gate, vGS. Positive gate voltage causes:

Free holes (positively charged) repelled from

the region underneath the G (pushed towardsubstrate). Leave behind a carrier-depletion (populated

negative charge) region. Positive gate also attract electrons from n+

source and drain. (abundance in the channel). Sufficient electrons create nregion between S

and D. If voltage is applied between D to S, current

will flow in the channel. The value of vGSwhich allow for mobile

electrons to accumulate and form conductingchannel is called the Threshold voltage, VT.


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Applying a Small vDS:

Consider vdsis small (i.e. 50 mV or so) whenvGS> VT.Voltage vDScauses iDto flow through the

induced nchannel.

Current is carried by free electrons travellingfrom S to D. By convention Ifrom D to S. iDdepends on density of electrons in the

channel, which depends on magnitude of vGS. iDversus vDSshows a linear resistance

relationship as vDSis increased and controlled

by vGS. The resistance is infinite for vGSVT.


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Operation as vDSis Increased :

Let vGSbe held constant greater than VT.As vDSis increased, it appears as a voltage

drop across the channel.Voltage measured relative to source increases

from 0 to vDS.Voltage between G and points along the

channel decreases from vGSat S to vGS - vDSatD end. Since channel depth depends on thisvoltage, channel is therefore has non-uniformdepth (Deepest at S while shallowest at D).

Thus, iD - vDScurve no longer straight butbends. (Picture next slide)


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When vDSis increased to the value that reduces the voltage between gate andchannel at the D end to VT(or vGSvDS= VT), the channel depth at the D enddecreases to almost ZERO. Channel is said to be pinched-off. Increasing vDSbeyond this value has little effect of iD. iDbecomes constant

(saturate). The voltage v

DSat which saturation occurs is denoted as v

Dsat= v

GS-V

T


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Derivation of the iDvDSRelationship

Objective to derive the iDv

DSrelationship at Triode and Saturation region of

operations.Assume that vGS> VTto induce a channel.Voltage vDSis applied between D to S. Consider operation in Triode region:

vDS< vGS- VT

Since the gate and the channel form a parallel platecapacitor denoted by Coxtherefore, the capacitance perunit gate area Cox is given by

oxox

ox

C

t

Where oxis the permittivity of the SiO2,ox= 3.45 x 10

-11F/m

[F/m2]


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Consider the infinitesimal strip of thegate at distance xfrom the source:

The capacitance of the strip is givenby

oxC Wdx

The electron charge dqin theinfinitesimal portion of the channel atpointxis given by

Q CV

( )ox GS T

dq C Wdx v v x V

Effective voltage

Negative charge

The electric field produced by vDSin the negative xdirection can be written as

[F]

dv x

E x

dx


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The electric field produced causes the electron charge dqto drift toward the drainwith velocity of

n n

dv xdxE x

dt dx

n- Mobility of electrons

Finally the resulting drift current, i can be obtained as follows:

dq dq dxi

dt dx dt

( )n ox GS T dv x

i C W v v x V dx

The drain-to-source current, iDcan therefore be written as

( )D n ox GS Tdv x

i i C W v v x V dx

( )D n ox GS Ti dx C W v v x V dv x


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Integrating both sides from x= 0 tox= L, corresponding to v(0) = 0 to v(L) = vDSyield

0 0

( )DS

vL

D n ox GS Ti dx C W v v x V dv x

21

2D n ox GS T DS DSi L C W v V v v

21

2D n ox GS T DS DS

Wi C v V v v

L

iDTriode region

To obtain current in the saturation region, we substitute vDS= vGSVTinto aboveequation which yield

21

2D n ox GS T

Wi C v V

L


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The term nCoxis known as the process transconductance parameter an normallysubstitute as kn

'n n oxk C

Therefore iDvDScan be rewritten as

' 21

2D n GS T DS DS

Wi k v V v v

L

2'1

2D n GS T

Wi k v V

L

(Triode region)

(Saturation region)

Aspect ratio


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Example:

Consider a process technology for which Lmin= 0.4 m, tox= 8 nm, n= 450 cm2/V.s,and VT= 0.7 V.

a) Find Coxand kn.b) For a MOSFET with W/L = 8 m/0.8 m, calculate the values of VGSand VDSmin

needed to operate the transistor in the saturation region with a dc current ID= 100

A.c) For the device in (b), find the value of VGSrequired to cause the device to operate

as a 1000 resistor for very small vDS.

Solution:

a) 11

3 2

9

3.45 104.32 10 /

8 10

oxox

ox

C F mt

' 2 3 2 6450 / . 4.32 10 / 194 10 / .n n oxk C cm V s F m F V s


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b) For operation in the saturation region,

2'1

2D n GS T

Wi k v V

L

26 61 8100 10 194 10 0.72 0.8

GSv

0.32 0.7 1.02GSv V min 1.02 0.7 0.32DS GS Tv v V V

c) For operation in the triode region,

' 21

2D n GS T DS DS

Wi k v V v v

L

For very small vDS, equation above can be reduced to

'D n GS T DSW

i k v V vL


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From which the drain-to-source resistance rDS

can be found as

'

1

n GS T W

k v VL

_DS

DSDS

D small v

vr

i

611000

194 10 10 0.7GSv

1.22GSv V


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MOSFET Current-Voltage Characteristics

The iD-vDSCharacteristics:

- Figure shows a std biasing ofn-channel MOSFET.

- The circuit can be used to measureiDvDS characteristics family of

curves at a constant vGS.- The characteristics show 3 regions

of operation : cutoff, triode, &saturation.

- Saturation region Amplifier- Cutoff & triode Switching

- CUTOFF:

- TRIODE:

GS Tv V

GS Tv V

(Induced Channel)


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GD Tv V (To maintain continuous Channel)

In terms of vDS,

GD GS SD GS DS v v v v v

Which yieldGS DS T v v V

Rearranging above equation will result in

DS GS Tv v V (To maintain continuous Channel)

In Triode region, the iDvGScharacteristic can be described as

' 21

2D n GS T DS DS

Wi k v V v v

L


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If vDS

is sufficiently small then the previous equation will become

'D n GS T DSW

i k v V vL

Specifically, for a value of vGS, rDSis given by

1'

_DS

DSDS n GS T

D small v

v Wr k v V

i L

It is also useful to express above equation in terms of gate-to-sourceoverdrive voltage given by

OV GS T V V V

Which will lead to

1'

DS n OVW

r k VL


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- SATURATION:

GS Tv V (Induced Channel)

The pinched off at drain end occurs by raising vDSto a value that results the gate-to-drain voltage, VGDfalling below VT,

GD Tv V (Pinched-off Channel)In terms of vDS,

GD GS DS v v v

GS DS T v v V DS GS T v v V (Pinched-off Channel)

The boundary between the triode and the saturation region is given by

DS GS Tv v V (Boundary)


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In Saturation region, the iDvGScharacteristic can be described as

2'1

2D n GS T

Wi k v V

L

The large-signal equivalent-circuit model that represents the MOSFET operation in

Saturation region is given by:


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Channel-Length Modulation:

- Previously we assume that increase of vDSbeyond vDSsathas no effect on channelsshape.

- In reality, as vDSis increased beyond VDSsat, the channel pinch-off point is movedslightly away from the drain, toward the source.

- This is due to the additional voltage applied beyond vDSsatwhich accelerates theelectrons that reach the drain end of the channel and sweeps them across thedepletion region into the drain.

- With depletion-layer widening, thechannel length effect is reducedfrom L to L - L.

- This phenomenon is known aschannel-length modulation.


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From previous equation and by including the channel-length modulation effect weget

2'1

2D n GS T

Wi k v V

L L

2'1 1

2 1D n GS T

W

i k v V LLL

2'1

12

D n GS TW L

i k v V L L

1LLPreviously assumed

and

' DSL v

Where is a process technology parameter (m/V).


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Inserting into previous equation yield

2'1 '

12

D n DS GS TW

i k v v V L L

Usually, /L is denoted as , therefore

2'1 1

2D n DS GS T

Wi k v v V L

A typical set of iD-vDScharacteristics showing the effectof channel-length modulation is as follows:

From the plot, when the straight-line are extrapolated,they intercept at the point vDS= -VA (Early Voltage).

Due to VA, the output resistance, rocan be derived as

A

o D

Vr

I


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Finally the large-signal equivalent circuit model by including the channel-lengthmodulation is given by

OS i ld ff i ( OS )


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Summary of the MOSFET Current-Voltage Characteristics

NMOS Transistor:Operation in the Triode region:

Conditions:

(1)

(2)

GS Tv V

GD Tv V DS GS T v V V

i-v Characteristics:

21

2

D n ox GS T DS DSW

i C v V v v

L

For vDS


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Operation in the Saturation region:

Conditions:

(1)

(2)

i-v Characteristics:

GS Tv V

GD Tv V DS GS T v V V

2'1 1

2D n DS GS T

Wi k v v V

L

2'1

2D n GS T

Wi k v V

L

(With Channel-Length Modulation effect)

MOS Fi ld Eff t T i t (MOSFET )


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MOSFET Circuit at DC: Example 1

Analysis of MOSFET circuit at dc. Neglect channel-length modulation unless specified (= 0).

Design the circuit of the circuit below so that the transistoroperates at ID= 0.4 mA and VD= 0.5 V. The NMOS transistor hasVT= 0.7 V, nCox= 100 A/V

2, L = 1 m, and W = 32 m.

Since,

0 0.5 0.5 0.7GD G D T v V V V

NMOS transistor is operating in Saturation region.

2 2' '1 1

2 2D n GS T n OV

W Wi k v V k V

L L

21 32

0.4 1002 1

OVm V

0.5OVV V ; 1.2OV GS T GS OV T V V V V V V V



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Since the Gate is grounded,

0 1.2 ; 1.2GS G S S S V V V V V V V

From the G to S loop,

1.2 2.53.25

0.4

S SSS

D

V VR k

I m

From D region,

2.5 0.55

0.4

DD DD

D

V VR k

I m



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Example 2

Design the circuit of the circuit below so that the transistoroperates at ID= 80 A. Find the value required for R and find thedc voltage VD. Let the NMOS transistor has VT= 0.6 V, nCox=200 A/V2, L = 0.8 m, and W = 4 m.

From the circuit,

0 0.6GD D D T v V V V V G D

v V

NMOS transistor is operating in Saturation region.

2 2' '1 1

2 2D n GS T n OV

W Wi k v V k V

L L

21 4

80 2002 0.8

OVV

0.4OVV V ; 1.0OV GS T GS OV T GV V V V V V V V



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Since the S is grounded,

0 1.0GS G S G G DV V V V V V V

From D region,

3 1

2580

DD DD

D

V V

R kI



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Example 3

Design the circuit of the circuit below to establish a drain voltage of 0.1 V. Whatis the effective resistance between drain and source at this operating point?. LetVT= 1 V, and kn(W/L) = 1 mA/V

2.

5 0.1 4.9 1GD G D T v V V V V V

MOSFET is operating in Triode region.

21

2D n ox GS T DS DS

Wi C v V v v

L

21

1 5 1 0.1 0.1 0.3952

Di m mA

The required value for RDcan bedetermined by

5 0.112.4

0.395

DD DD

D

V VR k

I m

The effective drain-to-source resistanceis calculated as

0.1253

0.395

DSDS

D

Vr

I m

MOS Field Effect Transistors (MOSFETs)


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Example 4

Analyze the circuit shown below to determine the voltages at all nodes and thecurrent through all branches. Let VT= 1 V, and kn(W/L) = 1 mA/V

2.

Since the gate current, IGis zero, the voltage at thegate is simply given by the voltage divider

22 1

1010 510 10

GG DDG G

R MV V V V R R M M

Assuming that the MOSFET is operating insaturation region,

5 6GS DV I k

Using

22'1 1

1 5 6 12 2

D n GS T DW

i k v V m I k L

2

18 25 8 0D DI I 0.89 ; 0.5

D DI mA I mA

MOS Field Effect Transistors (MOSFETs)


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Since we have two solution for ID, check the first solution yield 6 0.89 6 5.34S DV I k m k V

S GV V Doesnt make sense (NMOS is OFF).

Check the second solution yield

6 0.5 6 3S DV I k m k V

5 3 2GS G S V V V V

10 10 0.5 6 7D D DV I R m k V

Since VD> VG - VT, the transistor is indeed operating in saturation region.

Analog Elec EDB2034 Jan 2016 - MOSFET - Intro Biasing.pdf

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Transcript of Analog Elec EDB2034 Jan 2016 - MOSFET - Intro Biasing.pdf