An Introduction to VHDL Using Altera’s Quartus II IDE
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An Introduction to VHDL Using Altera’s Quartus II IDE
Dr. William M. JonesCoastal Carolina University
Numbers and Bytes Meeting20 OCT 2008
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VHDL Quick Start 2
Pre-Intro
• VHDL– Very Hard Difficult Language– Jk– VHSIC Hardware Description Language
• VHSIC– Very High Speed Integrated Circuits
• Intended uses– Circuit simulation– Circuit synthesis (realization)
• FPGA’s, (C)PLDs, ASICs
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VHDL Quick Start 3
Some Background
• VHDL vice Verilog• Altera and Xilinx • VHDL is a language
– But, is very different from traditional languages– In general, all statements are CONCURRENT (parallel)– Traditional is SEQUENTIAL – Typically referred to as code as opposed to a program– VHDL is not case sensitive
• PROCESS, FUNCTION, PROCEDURE – Only places were sequential behavior is seen
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Basic VHDL Code Parts
• LIBRARY– Like #include <stdio.h> in C or import in JAVA– Commonly used pieces of code– 2 are generally included by default
• ENTITY– List of specifications for input and output PORTS– Kinda like function prototypes in C (provides interface)
• ARCHITECTURE– Provides a description of how the circuit should behave
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LIBRARY
LIBRARY library_name;USE library_name.package_name.package_parts;
LIBRARY ieee;USE ieee.std_logic_1164.all;
LIBRARY std; -- included by defaultUSE std.standard.all;
LIBRARY work; -- included by defaultUSE work.all;
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ENTITY (Modeling Interfaces) (VHDL-93)
• Entity declaration– describes the input/output ports of a module
entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );end entity reg4;
entity name port names port mode (direction)
port typereserved words
punctuation
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PORTS – Signal Modes
• IN– Unidirectional
• OUT– Unidirectional
• INOUT– Bidirectional
• BUFFER– Used when output signal needs to be used internally
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Putting Them Together
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A Simple Multiplexer
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MUX Implementation with Pure Logic
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VHDL Quick Start 11
Synthesized Hardware (Pure Logic)
But what do you do now?
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Altera DE 2 Board
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MUX Implementation with WHEN/ELSE
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Synthesized Hardware (WHEN/ELSE)
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A Simple ALU
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ALU Specifications
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ALU Part 1
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ALU Part 2
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ALU Part 3
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Kickin’ It Up A Notch
Combinational v. Sequential LOGIC
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Concurrent v. Sequential Code
• Code placed inside a PROCESS, FUNCTION, or PROCEDURE is executed sequentially
• Otherwise the does is executed concurrently– In parallel– Order of statements would not matter– Often called ‘dataflow’ code
• With only a few exceptions purely concurrent code will only produce ‘combinational’ circuits
• Sequential code must be employed to produce sequential logic circuits (this code can produce both in fact)
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A Simple Counter (Sequential Code Intro)
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Simple Counter Code
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Synthesized Hardware (Counter)
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Counter (Zoom 1)
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Counter (Zoom 2)
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A Counter With A Display
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Counter With Display VHDL (Part 1)
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Counter With Display (Part 2)
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Counter With Display (Part 3)
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Counter With Display (Part 4)
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Synthesized HW (Partial)
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Creating A Symbol File (Schematic)
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End of N&B Presentation
Have a nice day!