Ambassador Hotel Hsinchu - Cadence · Ambassador Hotel Hsinchu CONFERENCE AGENDA 08:20 – ......
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Ambassador Hotel Hsinchu CONFERENCE AGENDA 08:20 – 09:00 Registration Open/Complimentary Breakfast 09:00 – 09:15 Welcome Remarks Brian Sung, Country Manager, Cadence Taiwan 09:15 – 09:45 Keynote I The Challenges of Physical Implementation for Advanced Technology Dr. Chin-Chi Teng, Corporate Vice President, Cadence 09:45 – 10:15 Keynote II Accelerating Innovation, Driven by High-Performance Computing Dr. Sogo Hsu, Vice President, Foxconn Technology Group 10:15 – 10:45 Keynote III System in Package - Moore with Heterogeneous Dr. Harrison Chang, Vice President, ASE Group 10:45 – 11:00 Coffee Break/Designer EXPO 11:00 – 11:50 Automotive Panel Discussion Moderator: Michael Shih, Corporate Vice President, Cadence Panelists: (in company alphabetical order): • Raja Tabet, Corporate Vice President of Emerging Technologies and Solutions, Cadence • K.S. Pua, Founder, Chairman, and CEO, Phison • Masayasu Yoshida, Senior Director, Automotive Solution Business Unit, Renesas • Kazuyoshi Yamada, Director, System Business Development, TSMC 11:50 – 12:10 Presentation Award Ceremony 12:10 – 13:30 Lunch/Designer EXPO Track 1. Digital Implementation and Signoff Ballroom C -10F Track 2. Digital Front-End Design and Test Ambassador Room 9F Track 3. System Design/ Verification Ballroom D -11F Track 4. Custom Analog and Mixed Signal Ballroom A-10F Track 5. IC Packaging and PCB Design Ballroom B-10F Track 6. Design IP/Tensilica Processor IP Mezzanine AB Room-13F 13:30 – 14:00 DIP 1. Innovations in RTL to Signoff: Faster and Smarter I Cadence FED 1. Technology Advancements in Design Creation I Cadence VER 1. 13:30-14:15 Cadence Verification Suite Technology Update Cadence CUS 1. Why You Must Use 3D Parasitic Extraction Field Solver for Characterization of Standard Cells, Memory, IPs, Automotive Designs, Etc. for FinFET Designs Cadence PCB 1. Bridging the Gap Between PCB Design and Analysis Cadence IP 1. TSMC Design Enablement for HPC, Mobile, IoT, and Automotive Applications TSMC 14:00 – 14:30 DIP 2. Innovations in RTL to Signoff: Faster and Smarter II Cadence FED 2. Technology Advancements in Design Creation II Cadence CUS 2. Efficient Approach for SDL Deployment - autoSVS and CPH autoReMapping eMemory PCB 2. Allegro Sigrity Analysis Technology: What’s New and What’s Coming Soon Cadence IP 2. Win-Win Collaboration Between Design Service and IP Provider GUC View the latest agenda in the mobile app © 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. MIPI is a registered trademark owned by MIPI Allliance. All other trademarks are the property of their respective owners.
Transcript of Ambassador Hotel Hsinchu - Cadence · Ambassador Hotel Hsinchu CONFERENCE AGENDA 08:20 – ......
Ambassador Hotel Hsinchu
CONFERENCE AGENDA08:20 – 09:00
Registration Open/Complimentary Breakfast
09:00 – 09:15
Welcome Remarks Brian Sung, Country Manager, Cadence Taiwan
09:15 – 09:45
Keynote I The Challenges of Physical Implementation for Advanced Technology Dr. Chin-Chi Teng, Corporate Vice President, Cadence
09:45 – 10:15
Keynote II Accelerating Innovation, Driven by High-Performance Computing Dr. Sogo Hsu, Vice President, Foxconn Technology Group
10:15 – 10:45
Keynote III System in Package - Moore with Heterogeneous Dr. Harrison Chang, Vice President, ASE Group
10:45 – 11:00
Coffee Break/Designer EXPO
11:00 – 11:50
Automotive Panel Discussion Moderator: Michael Shih, Corporate Vice President, Cadence Panelists: (in company alphabetical order): • Raja Tabet, Corporate Vice President of Emerging Technologies and Solutions, Cadence • K.S. Pua, Founder, Chairman, and CEO, Phison • Masayasu Yoshida, Senior Director, Automotive Solution Business Unit, Renesas • Kazuyoshi Yamada, Director, System Business Development, TSMC
11:50 – 12:10
Presentation Award Ceremony
12:10 – 13:30
Lunch/Designer EXPO
Track 1. Digital Implementation and SignoffBallroom C -10F
Track 2. Digital Front-End Design and TestAmbassador Room 9F
Track 3. System Design/ VerificationBallroom D -11F
Track 4. Custom Analog and Mixed Signal Ballroom A-10F
Track 5. IC Packaging and PCB DesignBallroom B-10F
Track 6. Design IP/Tensilica Processor IPMezzanine AB Room-13F
13:30 – 14:00
DIP 1. Innovations in RTL to Signoff: Faster and Smarter I Cadence
FED 1. Technology Advancements in Design Creation ICadence
VER 1. 13:30-14:15 Cadence Verification Suite Technology UpdateCadence
CUS 1. Why You Must Use 3D Parasitic Extraction Field Solver for Characterization of Standard Cells, Memory, IPs, Automotive Designs, Etc. for FinFET DesignsCadence
PCB 1. Bridging the Gap Between PCB Design and AnalysisCadence
IP 1. TSMC Design Enablement for HPC, Mobile, IoT, and Automotive ApplicationsTSMC
14:00 – 14:30
DIP 2. Innovations in RTL to Signoff: Faster and Smarter IICadence
FED 2. Technology Advancements in Design Creation IICadence
CUS 2. Efficient Approach for SDL Deployment - autoSVS and CPH autoReMappingeMemory
PCB 2. Allegro Sigrity Analysis Technology: What’s New and What’s Coming SoonCadence
IP 2. Win-Win Collaboration Between Design Service and IP ProviderGUC
View the latest agenda in the mobile app
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. MIPI is a registered trademark owned by MIPI Allliance. All other trademarks are the property of their respective owners.
Ambassador Hotel Hsinchu
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. MIPI is a registered trademark owned by MIPI Allliance. All other trademarks are the property of their respective owners.
CONFERENCE AGENDA14:30 – 15:00
DIP 3. Joint Collaboration on 7nm Digital Design Enablement TSMC
FED 3. Case Study: Applying Cadence Modus DFT to ARM Cortex CPUMediaTek
VER 2. 14:15 –15:00 Simulate the Effectiveness of Safety Mechanism in IC Design FlowITRI
CUS 3. Joint Collaboration on 7nm Custom Design Reference FlowTSMC
PCB 3. Run Simulations and Then Become an InventorMediaTek
IP 3. Scaling ADAS SoC Computation with Tensilica Vision DSP-Based Heterogeneous ArchitectureCadence
15:00 – 15:15
Break/Designer EXPO
15:15 – 15:45
DIP 4. Lithography Hotspot Fixing and Hotspot Testcase Creation with InnovusGLOBALFOUNDRIES
FED 4. A Programmable Power Structural Analyzer By Using CLP-APIMediaTek
VER 3. Formal Verification on ARM Cortex-M33 CPU Using JasperGold PlatformARM
CUS 4. Spectre RF-Based and Jitter Sensitivity-Aware Methodology to Solve Next-Generation Signal Integrity DescriptionGUC
PCB 4. Integrated Fan-Out on Substrate for HPC ApplicationMediaTek
IP 4. New Characterization Techniques for DDR4/LPDDR4 and Next Generation Memory StandardsTektronix
15:45 – 16:15
DIP 5. Designing Next-Generation ARM GPU Using ARM 7nm Libraries with Cadence ARM
FED 5. Body Supply Validation Within CLPMediaTek
VER 4. MIPI PHY IP Design with Cadence Design EnvironmentM31
CUS 5. Flow SharingUMC
PCB 5. USB 3.0 IBIS-AMI Generation Using Sigrity SystemSI AMI BuilderFaraday
IP 5. Meeting ADAS SoC Safety Design Challenges with Active Safety Features Built-In to IPCadence
16:15 – 16:45
DIP 6. Early Analysis of Standard Cell Routability on UMC 28nm LibrariesUMC
FED 6. Leverage LEC to Achieve Better Design QoR with Complete VerificationMediaTek
VER 5. When High-Level Synthesis Meets EmulationRealtek
CUS 6. In-Design DFM Recommended Rule Checking and Scoring with PVSGLOBALFOUNDRIES
PCB 6. Brand-New Electrical/ Thermal Co-Simulation AnalysisFoxconn
IP 6. Intelligent Interconnect for Autonomous Vehicle SoCsNetspeed
16:45 – 17:15
DIP 7. Best Practices for Energy Efficiency-Driven Implementations of ARM Cortex-A55/-M33 ProcessorsARM
FED 7. Genus Adoption Experience Sharing Cadence
VER 6. Enable Complex CPU System’s Coverage Closure by SW-Driven Stimulus with Structural Coverage Beyond Accelerated EmulatorMediaTek
CUS 7. QCI-Quantus Transistor-Level Extraction FlowRichtek
PCB 7. PCB Fabrication of Software SolutionsEastek
17:15 Lucky Draw
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