AMBA_bus_rev1.ppt_0.odp
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Transcript of AMBA_bus_rev1.ppt_0.odp
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Bus AMBA
Advanced Microcontroller Bus Architecture
(AMBA)
Rf: AMBA Specification
(Rev 2.0)
www.a!.co!
ARM "#" 00$$A
mailto:[email protected]://www.arm.com/http://www.arm.com/mailto:[email protected] -
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What to see
AMBA %&%te! achitectue
'eivative% Bu% A#B ASB AB
*an%action%
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Bus hierarchies
Advanced Microcontroller Bus
Architecture (AMBA)
Advanced High-performance Bus (A#B) Advanced System Bus (ASB)
Advanced Peripheral Bus (AB).
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Typical System
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Advanced High-performance Bus(AHB)
*he AMBA A#B i% fo high-performance high clock
freuency system modules!
*he A#B act% a% the high+pefo!ance %&%te! backbone
bu%. A#B %uppot% the efficient connection of poce%%o% on+
chip !e!oie% an, off+chip e-tenal !e!o&
inteface% with low+powe peipheal !aco cell function%.
A#B i% al%o %pecifie, to en%ue ea%e of u%e in an efficient,e%ign flow u%ing %&nthe%i% an, auto!ate, te%t
techniue%.
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A,vance, S&%te! Bu%(ASB)
*he AMBA ASB i% fo high+pefo!ance
%&%te! !o,ule%.
AMBA ASB i% an altenative %&%te! bu%
%uitable fo u%e whee the high+pefo!ance
featue% of A#B ae not euie,.
ASB al%o %uppot% the efficient connection of
poce%%o% on+chip !e!oie% an, off+chipe-tenal !e!o& inteface% with low+powe
peipheal !acocell function%.
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A,vance, eipheal Bu%(AB)
*he AMBA AB i% fo low+powe
peipheal%.
AMBA AB i% opti!i/e, fo !ini!alpowe con%u!ption an, e,uce,
inteface co!ple-it& to %uppot
peipheal function%. AB can be u%e, inconunction with eithe ve%ion of the
%&%te! bu%.
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1bective% of the AMBA%pecification
*he AMBA %pecification ha% been ,eive, to
%ati%f& fou e& euie!ent%: to facilitate the right-first-time ,evelop!ent of
e!be,,e, !icocontolle po,uct% with one o!oe 34% o %ignal poce%%o%
to be technology-independent an, en%ue that
highl& eu%able peipheal an, %&%te! !acocell%
can be !igate, aco%% a ,ive%e ange of "3poce%%e% an, be appopiate fo full+cu%to!
%tan,a, cell an, gate aa& technologie%
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1bective% of the AMBA%pecification (2)
to encouage modular system design to
i!pove poce%%o in,epen,ence povi,ing
a ,evelop!ent oa,+!ap fo a,vance,
cache, 34 coe% an, the ,evelop!ent ofpeipheal libaie%
to !ini!i/e the %ilicon infa%tuctue
euie, to %uppot efficient on+chip an, off+chip co!!unication fo both opeation an,
!anufactuing te%t.
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AMBA AHB" ne# generationAdvanced High-performance Bus
AMBA A#B i!ple!ent% the featue% euie, fo
high+pefo!ance high cloc feuenc&
%&%te!% inclu,ing:
5 bu%t tan%fe%
5 split transactions
5 %ingle+c&cle bu% !a%te han,ove
5 %ingle+cloc e,ge opeation
5 non+ti%tate i!ple!entation
5 wi,e ,ata bu% configuation% (678$29 bit%).
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AHB $omponents
AHB master transfers initiator
AHB slave
AHB ar%iter multi-master AHB decoder centrali&ed decoder
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AHB" general vie#" multi-master
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AHB Master
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AHB Slave
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AHB Slave" mu' data
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AHB" simple transfert
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AHB" #ait
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AHB" multiples transfers
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AHB" e'amples of transfers
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ata %us" little endian
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AHB" central ar%iter
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$entrali&ed Ar%itration
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Ar%itration
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AHB decoder
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AHB" decoding" e'ample
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AMBA ASB" old generationAdvanced System Bus
bu%t tan%fe%
pipeline, tan%fe opeation
!ultiple bu% !a%te.
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ASB Master
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ASB Slave
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ASB decoder
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ASB ar%iter
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AMBA AB
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AB transferts
ite tan%fe Rea, tan%fe
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AB %ridge
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AB Slave
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AB" tri-state Bus availa%le depending on the implementation#rite cycle
AHB
AB
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AB" tri-state Bus availa%le depending on the implementationread cycle
AHB
AB