Agilent HFBR-7924 andHFBR-7924E/H/EH Four-ChannelPluggable Parallel Fiber Optic TransceiverPart of the Agilent METRAK familyData Sheet Features

• Four Transmit and Four ReceiveChannels; 1 to 2.7 GBd perchannel

• Compatible with SONET scrambledand 8B10B encoded data formats

• 850 nm VCSEL array source• Conforms to “POP4” Four-Channel

Pluggable Optical TransceiverMultisource Agreement

• 50/125 µm multimode fiberoperation• Distance up to 300 m with

500 MHz.km fiber at 2.5 Gb/s• Distance up to 600 m with

2000 MHz.km fiber at 2.5 Gb/s• Pluggable package• Outputs (Tx & Rx) are squelched

for loss of signal• Control I/O is compatible with

LVTTL and LVCMOS• Standard MTP® MPO ribbon fiber

connector interface• Integrated heat sink• Manufactured in an ISO 9002

certified facility• Rx Signal Detect

Applications• Telecom and Datacom Switch/

Router Rack-to-Rack Connections• OC-192 Very Short Reach (VSR),

OIF-VSR4-03.0, Interconnects• Computer Cluster Interconnects

DescriptionThe HFBR-7924 transceiver is ahigh performance fiber opticmodule for parallel optical datacommunication applications. Itincorporates 8 independentdata channels (4 for transmitand 4 for receive) operatingfrom 1 to 2.7 Gb/s per channelproviding a cost effectivesolution for very short reachapplications requiring 10.8 Gb/saggregate bandwidth. Themodule is designed to operateon multimode fiber systems ata nominal wavelength of 850nm. It incorporates highperformance, highly reliable,short wavelength optical devicescoupled with proven circuittechnology to provide long lifeand consistent service.

The HFBR-7924 transceivermodule incorporates a 4 channelVCSEL (Vertical Cavity SurfaceEmitting Laser) array togetherwith a custom 4 channel laserdriver integrated circuitproviding IEC-825 and CDRHClass 1M laser eye safety. It alsocontains a 4 channel PINphotodiode array coupled with acustom preamplifier / postamplifier integrated circuit.

Operating on 3.3 V powersupply this module providesLVTTL/LVCMOS controlinterfaces and CML compatiblehigh speed data lines whichsimplify external circuitry. Thetransceiver is housed in MTP®/MPO receptacled package withintegral finned heatsink.Electrical connections to thedevice are achieved by means ofa pluggable 10x10 connectorarray.

Ordering InformationThe HFBR-7924 product isavailable for production ordersthrough the Agilent ComponentField Sales Office.

HFBR-7924 No EMI NoseShield

HFBR-7924E With ExtendedEMI Nose Shield

HFBR-7924H No heatsink, NoEMI Nose Shield

HFBR-7924EH No heatsink,with EMI NoseShield

2

Figure 1 Block Diagram (dimensions in mm)

Figure 2 - Case temperature measurement

Figure 3 - Ambient air temperature and air flow for TC = +80 °C

VCSELArrayInput

Stage

DIN Ch 0 - 3 +

Driver

4 Channels

Driver

PIN Array

InputStage

Control

Vcc_TX

GND_TX

Vcc_RX

GND_RX

DIN Ch 0 - 3 -

DOUT Ch 0 - 3 +

DOUT Ch 0 - 3 -

4 Channels

TX_DIS

TX_EN

TX_FAULT*

TX_RESET*SD

POINT FOR TAKINGMODULE TEMPERATURE

Bar CodePart Number

Agilent

0

5

10

15

20

25

0 0.5 1 1.5 2

Air Velocity (m/s)

Mo

du

le C

ase T

em

pera

ture

Ris

e A

bo

ve A

mb

ien

t (

C)

3

Package Dimensions

Figure 4A - HFBR-7924 Package dimensions (dimensions in mm)

Notes:1. Module mass approximately 20 grams.

Figure 4B - HFBR-7924E Package dimensions (dimensions in mm)

4

Figure 5B - HFBR-7924EH Package Dimensions (dimensions in mm)

Figure 5A - HFBR-7924H Package Dimensions (dimensions in mm)

5

Figure 6 - Package Board Footprint (dimensions in mm)

Figure 7 - Host Frontplate Layout (dimensions in mm)

2 x ∅ 2.54 MIN. PAD KEEP-OUT

18.42 MIN.

13.72

50KEEP-OUT AREA

FOR MPO CONNECTOR

6.73

30.23

1.89 REF.

6.73

9 x 1.27 TOT = 11.43

8.95 REF.

FRONT

SYM.

9 x 1.27 TOT = 11.43

18 REF.

SYM.

END OFMODULE

2 x ∅ 1.7 ± 0.05 HOLES

3 x ∅ 4.17 MIN. PAD KEEP-OUT

3 x ∅ 2.69 ± 0.05 HOLESFOR #2 SCREW

(10 x 10 =) 100 x ∅ 0.58 ± 0.05 PADS

PCB TOP VIEW

100 PIN FCIMEG-Array® RECEPTACLE

CONNECTORS

∅ 0.1 A B-C

∅ 0.1 A B-C

∅ 0.1 A B-C

∅ 0.1 A B-C

B

A

C

∅ 0.05 A B-C

19.02 min 0.50 max

13.4

0 ±

0.2

3.60

± 0

.2

15.70 ± 0.25 35.31+/- 0.20

PCB

PCB

Front Panel

NOTE: The host electrical connector attached to the PCB must be a 100-position FCI Meg-Array® plug (FCI PN: 84512-102) or equivalent.

6

Absolute Maximum RatingsStresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter inisolation, all other parameters having values within the recommended operating conditions. It should not be assumed that limitingvalues of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum ratings forextended periods can adversely affect device reliability.

Recommended Operating ConditionsRecommended Operating Conditions specify conditions for which the optical and electrical characteristics hold. Optical andelectrical characteristics are not specified for operation beyond the Recommended Operating Conditions, reliability is not impliedand damage to the device may occur for such operation over an extended time period.

Notes:1. This is the maximum voltage that can be applied across the Transmitter Differential Data Inputs without damaging the input circuit.2. Case Temperature is measured as indicated in Figure 2.3. Data inputs are CML compatible. Coupling capacitors are required to block dc. DVDIN p-p = DVDINH - DVDINL, where DVDINH = High State Differential

Data Input Voltage and DVDINL = Low State Differential Data Input Voltage.4. Power Supply Noise is defined at the supply side of the recommended filter for all VCC supplies over the frequency range from 500 Hz to 2700 MHz

with the recommended power supply filter in place.5. For data patterns with restricted run lengths, e.g. 8B10B encoded data, smaller value capacitors may provide acceptable results.

retemaraP lobmyS muminiM mumixaM tinU ecnerefeRerutarepmeTegarotS TS 04- 001+ Cº

egatloVylppuS V CC 5.0- 6.4 V

egatloVtupnIlangiSlortnoC/ataD VI 5.0- V CC 5.0+ V

egatloVtupnIlaitnereffiDrettimsnarT V| D| 2 V 1

)cd(tnerruCtuptuO ID 52 Am

)gnisnednoCnoN(ytidimuHevitaleR HR 5 59 %

retemaraP lobmyS muminiM lacipyT mumixaM tinU ecnerefeRerutarepmeTesaC TC 0 08+ Cº ,2serugiF,2

egatloVylppuS V CC 531.3 3.3 564.3 V 8erugiF

lennahC/etaRgnilangiS 1 7.2 dBG

kaeP-ot-kaePlaitnereffiDtupnIataD

gniwSegatloV

DV P-PNID 571 0061 Vm P-P 21,11serugiF,3

)%08-02(emiTllaF&esiRtupnIataD tr t, f 061 sp

hgiHegatloVtupnIlortnoC V HI 0.2 V CC V

woLegatloVtupnIlortnoC V LI V EE 8.0 V

esioNylppuSrewoP NP 002 Vm P-P 8erugiF,4

sroticapaCgnilpuoCO/IataD C CA 1.0 Fµ 9erugiF,5

daoLtuptuOataDlaitnereffiDrevieceR R LD 001 W 9erugiF

7

Transmitter Electrical Characteristics(Over recommended operating conditions: Tc= 0ºC to +80ºC, Vcc=3.3V + 5%)

Transmitter Optical Characteristics(Over recommended operating conditions: Tc= 0ºC to +80ºC, Vcc=3.3V + 5%)

Notes:6. Differential impedance is measured between DIN+ and DIN- over the range 4 MHz to 2 GHz.7. The specified optical output power, measured at the output of a 2 meter test cable, will be compliant with IEC 60825-1 Amendment 2, Class 1M

Accessible Emission Limits, AEL Regulatory Compliance section.8. Extinction Ratio is defined as the ratio of the average output optical power of the transmitter in the high (“1”) state to the low (“0”) state and is

expressed in decibels (dB) by the relationship 10log(Phigh avg/Plow avg). The transmitter is driven with a 550 MBd, 101010 pattern.9. These are unfiltered 20% - 80% values measured with a 550 MBd 101010 pattern.10. Inter-channel Skew is defined for the condition of equal amplitude, zero ps skew input signals.11. Deterministic Jitter (DJ) is defined as the combination of Duty Cycle Distortion (Pulse-Width Distortion) and Data Dependent Jitter. Deterministic

Jitter is measured at the 50% signal threshold level using a 2500 MBd Pseudo Random Bit Sequence of length 223-1 (PRBS-23), or equivalent, testpattern with zero skew between the differential data input signals.

12. Total Jitter (TJ) includes Deterministic Jitter and Random Jitter (RJ). Total Jitter is specified at a BER of 10-12 for the same 2.5 GBd test pattern asfor DJ and is measured with all channels operating.

retemaraP lobmyS muminiM lacipyT mumixaM tinU ecnerefeRecnadepmItupnIlaitnereffiD Z ni 08 001 021 W 9erugiF,6

emittressA*TLUAF T FFO 001 sµ 31erugiF

emittressA*TESER T FFO 5.7 sµ 41erugiF

emittressa-eD*TESER T NO 81 sm 41erugiF

emittressA)NE_XT(elbanEtimsnarT T NO 81 sm 51erugiF

emittressa-eD)NE_XT(elbanEtimsnarT T FFO 5.7 sµ 51erugiF

emittressA)SID_XT(elbasiDtimsnarT T FFO 5.7 sµ 51erugiF

emittressa-eD)SID_XT(elbasiDtimsnarT T NO 81 sm 51erugiF

emiTnoitaitinInO-rewoP 12 sm 71erugiF

sO/IlortnoC

,NE_XT,SID_XT

,*TLUAF_XT

*TESER_XT

hgiHtnerruCtupnI I| HI | 5.0 Am V0.2 < V HI < V CC

woLtnerruCtupnI I| LI | 5.0 Am V EE < V HI < V8.0

woLegatloVtuptuO V LO V EE 4.0 V I LO Am0.4=

hgiHegatloVtuptuO V HO 4.2 V CC V I HO Am5.0-=

retemaraP lobmyS muminiM lacipyT mumixaM tinU ecnerefeRrewoPlacitpOtuptuO

2.0=ANrebiF,mµ521/05

P TUO 0.8- 5.4- 0.2- .gvamBd 7

oitaRnoitcnitxE RE 6 5.7 Bd 8

htgnelevaWretneC lC 038 058 068 mn

smr-htdiWlartcepS s 58.0 smrmn

emiTllaF,esiR tr t, f 06 051 sp 9

wekSlennahc-retnI 05 001 sp 01

esioNytisnetnIevitaleR NIR 721- 121- zH/Bd

noitubirtnoCrettiJcitsinimreteD JD 02 05 sp p-p 11

latoT JT 54 021 sp p-p 21

8

Receiver Electrical Characteristics(Over recommended operating conditions: Tc= 0ºC to +80ºC, Vcc=3.3V + 5%)

Receiver Optical Characteristics(Over recommended operating conditions: Tc= 0ºC to +80ºC, Vcc=3.3V + 5%)

Notes:13. Measured over the range 4 MHz to 2 GHz.14. DVDOUTP-P = DVDOUTH - DVDOUTL, where DVDOUTH = High State Differential Data Output Voltage and DVDOUTL = Low State Differential Data Output

Voltage. DVDOUTH and DVDOUTL = VDOUT+ - VDOUT-, measured with a 100 W differential load connected with the recommended coupling capacitors andwith a 2500 MBd, 101010 pattern.

15. Inter-channel Skew is defined for the condition of equal amplitude, zero ps skew input signals.16. Rise and Fall Times are measured between the 20% and 80% levels using a 550 MHd square wave signal.17. The Signal Detect output will change from logic “0” (Low) to “1” (High) within the specified assert time for a step transition in optical input power

from the deasserted condition to the specified asserted optical power level.18. The Signal Detect output will change from logic “1” (High) to “0” (Low) within the specified de-assert time for a step transition in optical input power

from the specified asserted optical power level to the deasserted condition.19. Sensitivity is defined as the average input power with the worst case, minimum, Extinction Ratio necessary to produce a BER < 10-12 at the center of

the Baud interval. For this parameter, input power is equivalent to that provided by an ideal source, i.e. one with RIN and switching attributes that donot degrade the sensitivity measurement. All channels not under test are operating receiving data with an average input power of up to 6 dB abovePIN MIN. Sensitivity at signal rates from 1 to 2.7 GBd is defined for a PRBS 223-1 test pattern.

20. The stressed receiver sensitivity is measured using 2.6 dB Inter-Symbol Interference, ISI, (min), 30 ps Duty Cycle Dependent Deterministic Jitter,DCD DJ (min) and 6 dB ER (ER Penalty = 2.23 dB). All channels not under test are operating receiving data with an average input power of up to 6dB, above PIN MIN.

21. The stressed receiver eye opening is measured using 2.6 dB ISI (min), 30 ps DCD DJ (min), 6 dB ER (ER Penalty = 2.23 dB) and an average inputoptical power of -11.7 dBm. All channels not under test are operating receiving data with an average input power of up to 6 dB above PIN MIN.

22. Return loss is defined as the ratio, in dB, of the received optical power to the optical power reflected back down the fiber.23. Signal Detect assertion requires all optical inputs to exhibit a minimum 6 dB Extinction Ratio at PA = -17 dBm. All channels not under test are operating with

PRBS 223-1patterns, asynchronous with the channel under test, and average input power of up to 6 dB above the specified PIN MIN.

retemaraP lobmyS muminiM lacipyT mumixaM tinU ecnerefeRytivitisneS-rewoPlacitpOtupnI P NIMNI 81- 0.61- .gvamBd 91

noitarutaS-rewoPlacitpOtupnI P XAMNI 0.2- .gvamBd

htgnelevaWretneCgnitarepO lC 038 068 mn

ytivitisneSrevieceRdessertS 7.11- mBd 02

gninepOeyErevieceRdessertS 111 sp 12

ssoLnruteR 21 Bd 22

tceteDlangiS

detressA PA 22- 71- .gvamBd 32

detressaeD PD 13- 72- .gvamBd

siseretsyH PA P- D 5.0 0.1 Bd

retemaraP lobmyS muminiM lacipyT mumixaM tinU ecnerefeRecnadepmItuptuOlaitnereffiD Z TUO 001 W 9erugiF,31

gniwSegatloVkaeP-ot-kaePlaitnereffiDtuptuOataD DV P-PTUOD 005 056 008 Vm P-P 01erugiF,41

wekSlennahc-retnI 05 001 sp 51

emiTllaF,esiRtuptuOataD tr t, f 021 051 sp 61

O/IlortnoC

tceteDlangiS

SOMCVL&LTTVL

elbitapmoC

woLegatloVtuptuO V LO V EE 4.0 V I LO Am0.4=

hgiHegatloVtuptuO V HO 4.2 V CC V I HO Am5.0-=

)NO-ot-FFO(emiTtressA t ADS 05 sµ 71

)FFO-ot-NO(emiTtressa-eD t DDS 05 sµ 81

9

General/Control Electrical Characteristics(Over recommended operating conditions: Tc= 0ºC to +80ºC, Vcc=3.3V + 5%)

retemaraP lobmyS muminiM lacipyT mumixaM tinU ecnerefeRtnerruCylppuS I TCC 003 004 Am

noitapissiDrewoP P TSID 0.1 93.1 W

Regulatory ComplianceThe overall equipment designwill determine the certificationlevel. The module performanceis offered as a figure of merit toassist the designer inconsidering their use inequipment designs.

Electrostatic Discharge (ESD)There are two design cases inwhich immunity to ESD damageis important.

The first case is during handlingof the module prior to mountingit on the circuit board. It isimportant to use normal ESDhandling precautions for ESDsensitive devices. Theseprecautions include usinggrounded wrist straps,workbenches and floor mats inESD controlled areas. Themodule performance has beenshown to provide adequateperformance in typical industryproduction environments.

The second case to consider isstatic discharges to the exteriorof the equipment chassiscontaining the module parts. Tothe extent that the MT-basedconnector receptacle is exposedto the outside of the equipmentchassis it may be subject towhatever system-level ESD testcriteria that the equipment isintended to meet. The moduleperformance exceeds typicalindustry equipmentrequirements of today.

Electromagnetic Interference (EMI)Most equipment designs usingthese high-speed modules fromAgilent will be required to meetthe requirements of FCC in theUnited States, CENELECEN55022 (CISPR 22) in Europeand VCCI in Japan. Thesemodules, with their shieldeddesign, perform to the limitslisted in Table 1 to assist thedesigner in the management ofthe overall equipment EMIperformance.

ImmunityEquipment utilizing thesemodules will be subject to radiofrequency electromagnetic fieldsin some environments. Thesemodules have good immunity tosuch fields due to their shieldeddesign.

Eye SafetyThese 850 nm VCSEL-basedtransceiver modules provide eyesafety by design.

The HFBR-7924 has beenregistered with CDRH andcertified by TUV as a Class 1Mdevice under Amendment 2 ofIEC 60825-1. See the RegulatoryCompliannce Table for furtherdetail. If Class 1M exposure ispossible, a safety-warning labelshould be placed on the productstating the following:

LASER RADIATIONDO NOT VIEW DIRECTLY WITHOPTICAL INSTRUMENTS.CLASS 1M LASER PRODUCT

MTP®(MPO) Optics CleaningStatementThe optical port has recessedoptics that are visible throughthe nose of the port. The portplug provided should beinstalled whenever a fiber cableis not connected. This ensuresthe optics remain clean and nocleaning should be necessary. Inthe event of the optics beingcontaminated, forced nitrogenor dry clean air at less than 20psi is the recommended cleaningagent. The features of theoptical port and guide pinspreclude the use of any solidinstrument. Liquids are notadvised due to potentialdamage.

Application of wave soldering,reflow soldering and/or aqueouswash processes with the HFBR-7924 modules device on boardis not recommended as damagemay occur.

Normal handling precautionsfor electrostatic sensitivedevices should be taken (seeESD section).

10

Table 1 - Regulatory Compliance

erutaeF dohteMtseT ecnamrofrePotDSE(egrahcsiDcitatsortcelE

)sdaPlacirtcelEeht

-411A-22DSEJ()MBH(ydoBnamuHCEDEJ

)B

)MM(ledoMenihcaMCEDEJ

V0001>eludoM

V05>eludoMotDSE(egrahcsiDcitatsortcelE

)elcatpeceRrotcennoCeht

2-4-00016CEIfonoitairaV egamadtuohtiw)desaibeludom(Vk6tsaeltadnatshtiwyllacipyT

ledoMydoBnamuHaybdetcatnocsielcatpecerrotcennocehtnehw

eborpecnerefretnIcitengamortcelE

)IME(

BssalCCCF

BssalC22055NECELENEC

1ssalCICCV)A22RPSIC(

.nigramBd5htiwssapyllacipyT

)52dna42setoNeeS(

ytinummI 3-4-00016CEIfonoitairaV morftpewsdleifm/V01amorftceffeelbarusaemonwohsyllacipyT

.erusolcnesissahcatuohtiweludomehtotdeilppazHG1otzHM08ytefaSeyEresaL

gnitseTepyTtnempiuqEdna

2tnemdnemA1-52806CEI

0401noitceS12RFC

M1ssalCHRDCADFSU&LEACEI

22-1510279:rebmuNnoisseccAHRDC

40.5901712E:esneciLtrauaBVUTtnenopmoC

noitingoceR

naidanaCdnaseirotarobaLsretirwrednU

tnenopmoCtnioJnoitaicossAsdradnatS

noitingoceR

tnempiuqEygolonhceTnoitamrofnIrof

.tnempiuqEssenisuBlacirtcelEgnidulcnI

478371E:rebmuNeliFLU

Notes:24. EMI performance only refers to shielded version (HFBR-7924E and HFBR-7924HE).25. EMI performance could be improved by connecting the following pads to electrical ground : C9, G7 and H9.

11

4+4 Transceiver Module Pad Assignment - HFBR-7924

DOUT00-

K

VEE RX

J

DOUT03+

H

VEE RX

G

VEE RX

F

VEE TX

E

VEE TX

D

DIN03-

C

VEE TX

B

DIN00+

A

1

DOUT00+ VEE RX DOUT03- VEE RX VEE RX VEE TX VEE TX DIN03+ VEE TX DIN00-2

VEE RX VEE RX VEE RX VEE RX VEE RX VEE TX VEE TX VEE TX VEE TX VEE TX3

DOUT1+ VEE RX DOUT02- DNC DNC DNC DNC DIN02+ VEE TX DIN01-4

DOUT1- VEE RX DOUT02+ DNC DNC DNC DNC DIN02- VEE TX DIN01+5

VEE RX VEE RX VEE RX DNC DNC DNC DNC VEE TX VEE TX VEE TX6

VCCB RX VCCB RX VCCB RX DNC DNC DNC DNC VCC TX VCC TX VCC TX7

DNC ReservedTBD MSA

ReservedTBD MSA

ReservedTBD MSA

DNC TX_DIS TX_EN DNC DNC DNC8

DNC ReservedTBD MSA

ReservedTBD MSA

SD DNC RESET* FAULT* DNC DNC DNC9

VCCA RX VCCA RX VEE RX DNC DNC DNC DNC VEE TX VCC TX VCC TX10

TOP VIEW (PCB LAYOUT)

(10 x 10 ARRAY)

12

Table 2. Transceiver Module Pad Description

lobmyS noitpircseDlanoitcnuF

hguorht-/+3-0hCniD-/+3-0hCniD

.elbitapmocLMCerastupniataD:3hguorht0slennahcrofstupniatadlaitnereffidrettimsnarT

SID_XT rettimsnartehtffonrutotdesutupnilortnoC.)nwodlluplanretnI(tupnISOMCVL:elbasiDrettimsnarT.woLnehwdelbanesinoitarepolamroN.hgiHnehwffosiyarraLESCV.evitcAhgiH.stuptuolacitpo

NE_XT rettimsnartehtelbaneotdesutupnilortnoC.)pulluplanretnI(tupnISOMCVL:elbanErettimsnarT.hgiHnehwdelbanesinoitarepolamroN.woLnehwffosiyarraLESCV.evitcAhgiH.stuptuolacitpo

*TLUAF_XT tnerruc-revoytefas-eyenagnitacidnituptuosutatsrettimsnarT.tuptuOSOMCVL:tluaFrettimsnarTnoitpurrocatadnoitarbilacaro/dnanoitidnocegnarerutarepmetfotuona,LESCVynarofnoitidnoc

tluafehtsetacidnietatstuptuowoL.noitarepolamronsetacidnietatstuptuohgiH.noitceted.*TESER_XTybderaelcsidnayarraLESCVehtselbasidnoitidnoc*TLUAFdetressanA.noitidnoc

*TESER_XT cigolrettimsnartehtteserotdesutupnilortnoC.)pulluplanretnI(tupnISOMCVL:teseRrettimsnarT.hgiHnehwdelbanesinoitarepolamroN.woLnehwffosiyarraLESCV.woLevitcA.snoitcnuf

V EE XT_ esiwrehtosselnulaitnetopsihtotdecnerefererasegatlovrettimsnartllA.nommoclangisrettimsnarT.enalpdnuorgrettimsnartdraobCPehtotsdapesehttcennocyltceriD.detats

V CC XT_ .ylppusrewoprettimsnarT

hguorht-/+3-0hCtuoD-/+3-0hCtuoD

ataD.elbitapmocLMCerastuptuoataD:3hguorht0slennahcrofstuptuoatadlaitnereffidrevieceR.tceteDlangiSdetressa-edrofdehcleuqserastuptuo

DS llanilangisdilavgnitacidnituptuosutatsrevieceR.tuptuOSOMCVL:tceteDlangiSrevieceRwoL.lennahcyrevednahcaeotstupnilacitpodilavsetacidni)detressa(etatstuptuohgiH.slennahc

llA.stupnireviecerderotinomehtfoynatalangisfossolsetacidni)detressa-ed(etatstuptuo.derotinomeraslennahc

CND .laitnetoplacirtceleynaottcennoctonoD.tcennoCTONoD

V EE XR_ esiwrehtosselnulaitnetopsihtotdecnerefererasegatlovreviecerllA.nommoclangisrevieceR.enalpdnuorgreviecerdraobCPehtotsdapesehttcennocyltceriD.detats

V CC XR_A .liarylppusrewopreifilpmaerpniP

V CC XR_B .liarylppusrewoprezitnauqrevieceR

V CC VdnaXR_A CC fotcapmiehteziminimdnaytivitisnesreviecermumixamerusniot,revewoH.ylppusrewopemasehtotdetcennocebnacXR_Bkrowtengniretlifylppusrewopdednemmocerehtesuotdnaetarapesseilppusrewopehtpeekotdednemmocersiti,ylppusrewopehtmorfesion

Vno CC .)8erugiFees(XR_A

esaCeludoM secafrusevitcudnocdesopxellasetaroprocninommoCesaCreviecsnarT.nommoCesaCreviecsnarT.nommoClangiSrevieceRdnanommoClangiSrettimsnarTmorfdetalosiyllacirtcelesidna

13

Figure 8 - Recommended power supply filter

VccA Rx

VccA Rx

VccB Rx

VccB Rx

VccB Rx

C120.1 µF0603

C110.1 µF0603

C1010 µF1210

C910 µF1210

R6 1.0 kΩ 0603 R5 100 Ω 0603

L6 6.8 nH 0805 L5 1 µH 2220VCCVcc Tx

Vcc Tx

Vcc Tx

Vcc Tx

HFBR-7924

R4 1.0 kΩ 0603 R3 100 Ω0603

L4 6.8 nH 0805 L3 1 µH 2220

C80.1 µF0603

C70.1 µF0603

C610 µF1210

C510 µF1210

R2 1.0 kΩ 0603 R1 100 Ω 0603

L2 6.8 nH 0805 L1 1 µH 2220

C40.1 µF0603

C30.1 µF0603

C210 µF1210

C110 µF1210

VCC

VCC

14

Figure 9 - Recommended AC coupling and data signal termination

Figure 10 - Differential signals

Figure 11 - Transmitter data input equivalent circuit Figure 12 - Receiver data output equivalent circuit.

RECEIVER

DOUT+

DOUT-

DIN+

DIN-

CAC

CAC

ZINRDL

AC COUPLING CAPACITORS (DC BLOCKING CAPACITORS) SHOULD BE USED TOCONNECT DATA OUTPUTS TO THE LOAD. THE DIFFERENTIAL DATA PAIR SHOULD BETERMINATED WITH A DIFFERENTIAL LOAD, RDL, OF 100 Ω USING EITHER AN INTERNALLOAD, ZIN, AS SHOWN ABOVE, OR AN EXTERNAL LOAD, IF NECESSARY.

VDI/O REFERS TO EITHER VDIN

OR VDOUT AS APPROPRIATE.

RECEIVER

DOUT+

DOUT-

∆VDOUT

+

-

∆VDI/OL

VDI/O+

VDI/O-

∆VDI/OH

∆VDI/OH

∆VDI/OL

∆VDI/O P-P

-

+

+

-

TRANSMITTER

DIN+

DIN-

∆VDIN

DIN-

DIN+

ZIN

50 Ω

50 Ω

VBIAS(NONIMAL 1.9V)

VCCT

VEE

DOUT+

VEE

50 Ω

DOUT-

VCC

50 Ω

15

Figure 13 - Transmitter FAULT* signal timing diagram

Figure 14 - Transmitter RESET* timing diagram

NO FAULT DETECTED FAULT DETECTED

TX OUT Ch 0 - 3

FAULT*

< 100 µs ~ 100 ns

TX_OUT Ch 3

TX_OUT Ch 2

TX_OUT Ch 1

7.5 µs (max)

SHUTDOWN NORMAL

RESET*

FAULT*

18 ms (max)

>100 ns

~4.2 ms

~4.6 ms(typ)

TX_OUT Ch 0

16

Figure 15 - Transmitter TX_EN and TX_DIS timing diagram

Figure 16 - Transmitter fault recovery via TX_EN timing diagram

~ 7.5 µsTX_EN

TX OUT Ch 0 - 3Normal Shutdown

(a)

~ 7.5 µsTX_DIS

Normal ShutdownTX OUT Ch 0 - 3

(b)

(c)

~4.2 ms ~4.6 ms

~18 ms

TX OUT Ch 0

TX OUT Ch 1

TX_EN [1]

TX OUT Ch 3

NOTE [1]: TX_DIS, WHICH ISNOT SHOWN, IS THEFUNCTIONAL COMPLEMENT OFTX_EN.

TX OUT Ch 2

> 1 ms

~ 200 ns

~18 ms

~4.2 ms

TX_EN [1]

NOTE [1]. TX_DIS, WHICH IS NOT SHOWN, IS THE FUNCTIONAL COMPLEMENT OF TX_EN.

~4.6 ms

Tx OUT Ch 0

Tx OUT Ch 1

FAULT*

Tx OUT Ch 3

Tx OUT Ch 2

17

TX_OUT 0

TX_OUT 1

TX_OUT 3

TX_OUT 2

Vcc

Vcc > 2.8V

~21 ms

6.5ms

~4.6ms

~4.6ms

~4.6ms

NORMAL

NORMAL

NORMAL

NORMAL

Figure 17. Typical Transmitter Power-Up Sequence

www.agilent.com/semiconductorsFor product information and a complete list of

distributors, please go to our web site.

For technical assistance call:

Americas/Canada: +1 (800) 235-0312 or

(408) 916-6763

Europe: +49 (0) 6441 92460

China: 10800 650 0017

Hong Kong: (+65) 6756 2394

India, Australia, New Zealand: (+65) 6755 1939

Japan: (+81 3) 3335-8152(Domestic/International), or

0120-61-1280(Domestic Only)

Korea: (+65) 6755 1989

Singapore, Malaysia, Vietnam, Thailand, Philippines,

Indonesia: (+65) 6755 2044

Taiwan: (+65) 6755 1843

Data subject to change.

Copyright © 2003 Agilent Technologies, Inc.

February 1, 2004

5989-0360EN