AdvanceMS Example

What’s all this mixed-signal simulation stuff anyway ?

Rich Klinger2006

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AdvanceMS Example

1.0 Scope

We have been using AdvanceMS for mixed-signal simulations using ModelSim and Eldo. The documentation from Mentor was enough to get us started but did not address issues specific to our usage. This document is meant to fill in the gaps.

Examples of using AdvanceMS can be found in Appendix H of AdvanceMS User’s Manual from Mentor Graphics. See example #4 for a simple example of verilog-on-top. The examples shown address a broad range of uses including VHDL, VHDL-AMS, and verilog in a variety of situations. This document addresses usage with verilog-on-top and expands on example #4.

This document shows how to use: multiple power supply domains digital stimulus from the verilog testbench analog stimulus in the spice netlist multiple levels of verilog and spice hierarchy

The circuit used in this example is a simplified version of circuits similar to what we designed for SoC’s. It is trivial enough that it could be simulated quickly in Eldo as a pure spice circuit without the gain of separating the digital function into verilog. The intent is to demonstrate the mechanics of running a mixed-signal simulation using AdvanceMS.

If you are interested in just copying a working example then copy the files listed in Table 1 and run the sim as described in section 2.2.

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2.0 The Guts of It

2.1 Circuit OverviewThe circuit consists of a low-to-high and a high-to-low level-shifter, a HVT NAND, a pad, and digital control in verilog. A summary of files is listed in Table 1, a complete listing of each file is in Appendix A. Figure 1 shows a schematic of the circuit with rectangles delineating the file boundaries. The point of the sim in this example is to test the circuit described in nander_top.v.

File Description

tb_nander.run Shell script that controls the sim

tb_nander.cmd Eldo command file. Contains sim OPTIONS, LIB, PROBE, PARAM, MODEL, a2d and d2a, DEFWAVE statements.

tb_nander.v Verilog testbench

nander_top.v* Top-level verilog file

nander_logic.v Verilog logic module

tb_nander_analog.v

Eldo spice subcircuit declarations

sp_nander.cir Top-level Eldo testbench netlist

nander.cir Eldo subcircuit.

pad.cir Eldo subcircuit

add_waves.do Optional file that adds waves to the waveform viewer window

Table 1: File Summary - The files used in this example should be in the directory example_files in the same directory where this file resides.

* There are two versions of this file. One is in analog_src directory and is used for mixed-signal sims. There is another copy that is the src directory, it is used for pure verilog sims. The difference is in the instantiation of the analog circuit. The mixed-signal version instantiates a spice subcircuit, whereas the pure verilog version instantiates a verilog behavioral model. See lines 43 -51 of nander_top.v.

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Figure 1: Circuit Schematic

2.2 The FilesThe circuit consists of 3 types of files; command, verilog ,and spice. The files used in this example should be in the directory example_files in the same directory where this file resides. Use the directory structure in example_files as a template for your own directory structure, making sure to change the paths in tb_nander.run and sp_nander.cir appropriately.

2.2.1 Command FilesThe command files are tb_nander.run, tb_nander.cmd, and add_waves.do. The run-file is a shell script and the cmd-file contains commands for Eldo. The do-file contains commands to add waveforms to the waveform viewer, EZWave, and a command to start the sim, run -all. The do-file could contain other commands for the waveform viewer but this example only uses the add wave commands.

2.2.1.1 The Run FileThe simulation is run by executing the run file, tb_nander.run. Let’s look at each section of the file, stopping to point out anything interesting or useful.

The first section contains header comments.

################################################################### File Name : tb_nander.run## Author : Rich Klinger## Date Created : 05/09/06#################################################################

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## Description : Shell script of AdvanceMS commands for nander testbench## This file defines the sim.#################################################################

The next 2 lines delete any previous instances of the design library, SPICE, and then creates a fresh one using the valib command. The valib command is very similar to the ModelSim command vlib.

\rm -rf SPICE *.inivalib SPICE

The design library is where the compiled files are put for use during the simulation. The name of the library can be any directory name that UNIX supports, however, AdvanceMS uses a special library called WORK during compilation, so don’t use the name WORK/work or any name that ends in WORK/work.

The next section compiles the verilog source files with the valog command. The –ms switch is used to specify ModelSim mode for the compilation. This is stated as a mandatory switch in the AdvanceMS User’s Manual.†

################################################################### Compile the Verilog files#################################################################valog ../src/nander_logic.v -msvalog ../analog_src/nander_top.v -msvalog ../test_src/tb_nander_analog.v -msvalog ../test_src/tb_nander.v -ms

Note the four directories; ../src/, ../analog_src/, ../test_src/, ./ The first directory, ../src/, is where the source verilog that will be synthesized and APR’ed is stored. The second, ../analog_src/, is where analog behavioral models and other analog-only files are kept. The third, ../test_src/, is where files used in either pure verilog or mixed-signal sims are kept. The last, ./, is the current simulation directory.

The next section compiles the spice file with the vacom command. The –f switch forces overwriting of existing compiled files. The –ams switch compiles the files in AdvanceMS and then imported into ModelSim. The –spice switch indicates that the file to be compiled is a spice file. The next item in the command, sp_nander, is the ADMS entity name to be used for the sim. In this example the entity name is the same as the spice subcircuit name, sp_nander. The last item is the subcircuit and file path, sp_nander@sp_nander.cir.

################################################################### Compile the SPICE files#################################################################vacom -f -ams -spice sp_nander sp_nander@sp_nander.cir

† AdvanceMS User’s Manual, v2.0_1, page 9-21

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The last section of the run file runs the simulation using the vasim command. The –cmd switch indicates the next item is the name of the Eldo command file to be used for the simulation. The item after the command file is the name of the top-level entity, in our case it is the verilog module, tb_nander, in the top-level testbench file, tb_nander.v. The –do switch calls the do-file add_waves.do. As stated previously the do-file can contain other commands for vasim but in this example only add wave commands are called. Also, the last line of the do-file in this example has the command that actually starts the sim after all files have been locked and loaded. The command is run –all, this can also be typed into the GUI command window that will start with the vasim command.

################################################################### Run the sim#################################################################vasim -cmd tb_nander.cmd tb_nander -do add_waves.do

2.2.1.2 The Cmd FileEldo commands are contained in the file tb_nander.cmd. The Eldo command file can contain any Eldo commands and even subcircuits. It is essentially just another spice file. However, one thing it must have in an AdvanceMS sim are the A-to-D and D-to-A converters that are inserted at the boundary between the spice simulation and the verilog simulation.

The first section contains header comments.

******************************************************************* File Name : tb_nander.cmd** Author : Rich Klinger** Date Created : 05/09/06******************************************************************* Description : Eldo commands for the nander testbench.*****************************************************************

The next section contains global declarations. Use’em if ya need’em. But most likely you won’t.

************************************************* Globals************************************************.GLOBAL 0

The next section contains simulation options using the .OPTION command. The settings shown are for accuracy. Other OPTIONS are available. See your handy-dandy Eldo User’s Manual for more information.

************************************************* Options************************************************.OPTION+gear

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+eps= 1.0e-6+abstol= 1.0e-15+reltol= 1.0e-6+vntol= 1.0e-9

The next section contains the path to the model library and the skew corner to be used.

************************************************* Libraries************************************************.LIB "/usr/eda/models/eldo/prod/90nm.lib" typ

The next section contains the simulation type, TRAN, and the most efficient convergence algorithm, RAMP, to be used during DC convergence. This was found through trial-and-error on the TSI ADC circuit. Your mileage may vary.

************************************************* Simulation Types************************************************.TRAN 1p 1u.RAMP tran 1u

The next section contains PROBE statements to save signals in the spice circuit to the waveform file. Unless you have changed where the signals are saved, the default is a WDB file with the same name as the CMD file. That is, the results from this sim will be saved to tb_nander.wdb.

************************************************* Probes************************************************.PROBE tran v.PROBE tran w

.PROBE tran V(nt1.tnd1.in_ext)

.PROBE tran V(nt1.tnd1.in2_hv)

.PROBE tran V(nt1.tnd1.Xnand1.out1_hv)

.PROBE tran V(nt1.tnd1.Xnand1.out_lv)

The next section contains PARAM statements that declare values for the supplies in the spice testbench, sp_nander.cir.

************************************************* Supplies************************************************.PARAM vcc3p3 = 3.3V.PARAM vcc1p8 = 1.8V.PARAM vcc1p0 = 1.0V

The next section contains MODELS, DEFHOOK and HOOK statements necessary for inserting A-to-D and D-to-A converters at the spice/verilog boundary. The MODEL

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statements define the A-to-D and D-to-A converters. In our example we have several different power domains and so we need several different A-to-D and D-to-A converters. A complete description of MODEL commands can be found in the Eldo User’s Manual. The HOOK and DEFHOOK commands are defined in the AdvanceMS User’s Manual.

The DEFHOOK command is used to define the default converters to be inserted in nodes that are not explicitly connected in the following HOOK statements. In this example any ports not explicitly connected in the HOOK statements are assumed to be in the 1V domain and are connected with the d2a_std and a2d_std converters. The HOOK statements connect the ports that are not on the 1V domain.

************************************************* Converters************************************************.MODEL a2d_std a2d mode=std_logic vth1=0.2 vth2=0.5.MODEL d2a_std d2a mode=std_logic vhi=1.0 vlo=0 trise=1n tfall=1n.MODEL d2a_3p3 d2a mode=std_logic vhi=3.3 vlo=0 trise=1n tfall=1n.MODEL a2d_3p3 a2d mode=std_logic vth1=0.2 vth2=2.5.MODEL d2a_1p8 d2a mode=std_logic vhi=1.8 vlo=0 trise=1n tfall=1n.DEFHOOK d2a_std a2d_std.HOOK adc1.vcc_tsi_3p3v_hv nt1.tnd1.vcc_tsi_3p3v_hv bidir mod=a2d_3p3 mod=d2a_3p3.HOOK adc1.vcc_tsi_1p8v_mv nt1.tnd1.vcc_tsi_1p8v_mv mod=d2a_1p8.HOOK adc1.vcc_tsi_3p3v_hv nt1.pad1.vcc_tsi_3p3v_hv mod=d2a_3p3.HOOK nt1.fireb_mv nt1.tnd1.fireb_mv mod=d2a_1p8

The last section contains DEFWAVE statements. As with the PROBE statements, unless you have changed the defaults, the waveforms defined here will be saved to tb_nander.wdb.

************************************************* Wave Definitions************************************************.DEFWAVE I_1p0v V(nt1.tnd1.vcc_1p0v_lvx) - V(nt1.tnd1.vcc_1p0v_lv).DEFWAVE I_1p8v V(nt1.tnd1.vcc_1p8v_mvx) - V(nt1.tnd1.vcc_1p8v_mv).DEFWAVE I_3p3v V(nt1.tnd1.vcc_3p3v_hvx) - V(nt1.tnd1.vcc_3p3v_hv).DEFWAVE I_vss V(nt1.tnd1.vssx) - V(nt1.tnd1.vss)

2.2.1.3 The Do FileA simple file in our example, it adds waves to be saved in the waveform file and the last line is the line that actually starts the sim. If you don’t use a do-file or you omit the last line shown here, then you will need to type, run -all, in the GUI command window that will start with the vasim command in the run-file.

add wave :tb_nander:in_extadd wave :tb_nander:nt1:in_ext

add wave :tb_nander:dinadd wave :tb_nander:nt1:dinadd wave :tb_nander:nt1:lg1:din

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run -all

2.2 Running the simThis document only covers running simulation from the command-line. It’s quick and easy. No, really, it is. Once you have a working example of the files needed to run a sim, setting up other sims is quicker than using a GUI.

It is recommended that you setup a sim directory structure prior to running the sim so that you can keep track of your data. If I were you I would do that before proceeding.

Next, set up an xterm with advancems:

xterm> tsetup advancems version#

If you don’t know the version number, then just do the tsetup advancems and the available versions will be listed.

Execute the run file at the command prompt.

xterm> tb_nander.run &

If everything is in order, then AdvanceMS will start and the sim will run. If you do not use a do-file or do not have the run –all command at the end of the do-file then you will need to enter run –all in the GUI command window. If you have errors in any of the verilog files the error will be shown in the GUI command window. If you have errors in the spice files then the errors may or may not be listed in the GUI command file. My suggestion is that if you have an error related to not being able to load the spice file, then make a simple testbench that calls the spice circuit and just use Eldo to get the spice errors debugged.

As of May 2006, the default waveform viewer is EZWave and will show the results of the sim. The waveforms listed in add_waves.do will be automatically added to the window and updated as the sim progresses. The signals saved in the tb_nander.cmd file will need to be selected from the signal browser in the left-hand column of the EZWave window.

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Appendix A: Source File Listing

tb_nander.run######################################################################### File Name : tb_nander.run## Author : Rich Klinger## Date Created : 05/09/06######################################################################### Description : Shell script of AdvanceMS commands for nander testbench## This file defines the sim.#######################################################################\rm -rf SPICE *.inivalib SPICE

######################################################################### Compile the Verilog files#######################################################################valog ../src/nander_logic.v -msvalog ../analog_src/nander_top.v -msvalog ../test_src/tb_nander_analog.v -msvalog ../test_src/tb_nander.v -ms

######################################################################### Compile the SPICE files#######################################################################vacom -f -ams -spice sp_nander sp_nander@../analog_src/sp_nander.cir

######################################################################### Run the sim#######################################################################vasim -cmd tb_nander.cmd tb_nander -do add_waves.do

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tb_nander.cmd************************************************************************* File Name : tb_nander.cmd** Author : Rich Klinger** Date Created : 05/09/06************************************************************************* Description : Eldo commands for the nander testbench.***********************************************************************

************************************************* Globals************************************************.GLOBAL 0

************************************************* Options************************************************.OPTION+gear+eps= 1.0e-6+abstol= 1.0e-15+reltol= 1.0e-6+vntol= 1.0e-9

************************************************* Libraries************************************************.LIB "/usr/eda/models/eldo/prod/90nm.lib" typ

************************************************* Simulation Types************************************************.TRAN 1p 1u.RAMP tran 1u

************************************************* Probes************************************************.PROBE tran v.PROBE tran w

.PROBE tran V(nt1.tnd1.in_ext)

.PROBE tran V(nt1.tnd1.in2_hv)

.PROBE tran V(nt1.tnd1.Xnand1.out1_hv)

.PROBE tran V(nt1.tnd1.Xnand1.out_lv)

************************************************* Supplies************************************************.PARAM vcc3p3 = 3.3V.PARAM vcc1p8 = 1.8V.PARAM vcc1p0 = 1.0V

************************************************* Converters

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************************************************.MODEL a2d_std a2d mode=std_logic vth1=0.2 vth2=0.5.MODEL d2a_std d2a mode=std_logic vhi=1.0 vlo=0 trise=1n tfall=1n.MODEL d2a_3p3 d2a mode=std_logic vhi=3.3 vlo=0 trise=1n tfall=1n.MODEL a2d_3p3 a2d mode=std_logic vth1=0.2 vth2=2.5.MODEL d2a_1p8 d2a mode=std_logic vhi=1.8 vlo=0 trise=1n tfall=1n.DEFHOOK d2a_std a2d_std.HOOK nt1.vcc_tsi_3p3v_hv nt1.tnd1.vcc_tsi_3p3v_hv bidir mod=a2d_3p3 mod=d2a_3p3.HOOK nt1.vcc_tsi_1p8v_mv nt1.tnd1.vcc_tsi_1p8v_mv mod=d2a_1p8.HOOK nt1.fireb_mv nt1.tnd1.fireb_mv mod=d2a_1p8

************************************************* Wave Definitions************************************************.DEFWAVE I_1p0v V(nt1.tnd1.vcc_1p0v_lv_r) - V(nt1.tnd1.vcc_1p0v_lv).DEFWAVE I_1p8v V(nt1.tnd1.vcc_1p8v_mv_r) - V(nt1.tnd1.vcc_1p8v_mv).DEFWAVE I_3p3v V(nt1.tnd1.vcc_3p3v_hv_r) - V(nt1.tnd1.vcc_3p3v_hv).DEFWAVE I_vss V(nt1.tnd1.vss_r) - V(nt1.tnd1.vss)

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tb_nander.v************************************************************************* File Name : tb_nander.v** Author : Rich Klinger** Date Created : 05/09/06************************************************************************* Description : This code is the top-level testbench for the nander.**********************************************************************/

`timescale 100 ps/100 ps

module tb_nander;

reg in_ext;reg rstb;reg clk10M;reg din;reg fireb_mv;reg VCC_3P3V_HV;reg VCC_1P8V_MV;reg VCC_1p0V_LV;reg VSS;reg clk2M;wire ndout;

initialbegin in_ext <= 0; rstb <= 1; clk10M <= 0; din <= 0; fireb_mv <= 0; VCC_3P3V_HV <= 0; VCC_1P8V_MV <= 0; VCC_1p0V_LV <= 0; VSS <= 0; clk2M <= 0;end

// Master clock generatoralways @(clk10M) #500 clk10M <= ~ clk10M ;

// test monitor clock. Used in monitor statement at bottom of this file.always @(clk2M) #2000 clk2M <= ~ clk2M ;

initialbegin #100 VCC_3P3V_HV <= 0; #100 VCC_1P8V_MV <= 0; #100 VCC_1p0V_LV <= 0;

#100 rstb <= 0;#100 rstb <= 1;#100 fireb_mv <= 1;

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#2000 in_ext <= 1;#2000 din <= 1;#2000 in_ext <= 0;#2000 din <= 0;#2000 $stop;

end

// verilog instancenander_top nt1(rstb, clk, din, in_ext, ndout, fireb_mv, VCC_3P3V_HV, VCC_1P8V_MV, VCC_1p0V_LV, VSS);

always @(clk2M) $monitor($time, " clk2M = %b", clk2M, " ndout = ", ndout);

endmodule

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nander_top.v************************************************************************* File Name : nander.v** Author : Rich Klinger** Date Created : 05/09/06************************************************************************* Description : This code models the behavior of the nander_top**********************************************************************/`timescale 1 ns/100 ps

module nander_top(rstb, clk, din, in_ext, ndout, fireb_mv, VCC_3P3V_HV, VCC_1P8V_MV, VCC_1p0V_LV, VSS);

input rstb, clk, din, in_ext, fireb_mv, VCC_3P3V_HV, VCC_1P8V_MV, VCC_1p0V_LV, VSS;output ndout;wire data, ndout;

/************************************************************************ Logic**********************************************************************/nander_logic lg1(rstb, clk, din, data);

/************************************************************************ Verilog Behavioral Instances**********************************************************************///sp_nander tnd1(data, in_ext, ndout, fireb_mv, vcc_3p3v_hv, vcc_1p8v_mv, vcc_1p0v_lv, vss);

/************************************************************************ Analog Instances**********************************************************************/\spice.sp_nander(sp_nander) tnd1(data, in_ext, ndout, fireb_mv, vcc_3p3v_hv, vcc_1p8v_mv, vcc_1p0v_lv, vss);

/********************************************************************** End of top-level nander module**********************************************************************/

endmodule //nander

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nander_logic.v

************************************************************************** File Name : nander_logic.v** Author : Rich Klinger** Date Created : 05/09/06************************************************************************** Description : This code contains logic for AdvanceMS example.************************************************************************/`timescale 1 ns/100 ps

module nander_logic (rstb, clk, din, data);

input rstb, clk, din;output data;

reg data;

always @(posedge clk or negedge rstb) if(~rstb) data <= 0; else data <= din;

endmodule //logic

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tb_nander_analog.v************************************************************************* File Name : tb_nander_analog.v** Author : Rich Klinger** Date Created : 05/09/06************************************************************************* Description : This code provides modules used during testing only.** Log notes:**********************************************************************/

/************************************************************************ Analog Instance Declaration used during AdvanceMS simulations**********************************************************************/module sp_nander(in1_lv, in_ext, out_lv, fireb_mv, vcc_3p3v_hv, vcc_1p8v_mv, vcc_1p0v_lv, vss);

input in1_lv, in_ext, fireb_mv, vcc_3p3v_hv, vcc_1p8v_mv, vcc_1p0v_lv, vss;

output out_lv;

endmodule //tb_nander

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sp_nander.cir************************************************************************* File Name : sp_nander.cir** Author : Rich Klinger** Date Created : 05/09/06************************************************************************* Description : Analog Testbench for nander.*************************************************************************

************************************************************************* Analog Testbench - Must be declared as a .subckt in Verilog-on-top sim***********************************************************************.SUBCKT sp_nander in1_lv in_ext out_lv fireb_mv VCC_3P3V_HV_v VCC_1P8V_MV_v VCC_1p0V_LV_v VSS_v************************************************************************* .Includes***********************************************************************.INCLUDE ../analog_src/nander.cir.INCLUDE ../analog_src/pad.cir

************************************************************************* Termination resistors for unused supply inputs.***********************************************************************Rvcc3v vcc_3p3v_hv_v 0 1000kRvcc2v vcc_1p8v_mv_v 0 1000kRvcc1v vcc_1p0v_lv_v 0 1000kRvssv vss_v 0 1000k

************************************************************************* Power Supplies************************************************************************Vcc_3p3v_hvx vcc_3p3v_hvx 0 DC = vcc3p3*Vcc_1p8v_mvx vcc_1p8v_mvx 0 DC = vcc1p8*Vcc_1p0v_lvx vcc_1p0v_lvx 0 DC = vcc1p0*Vssx vssx 0 DC = 0V

** Ramping SuppliesVcc_3p3v_hv vcc_3p3v_hv_r 0 DC = 0V PWL(0,0, 1u,0, 1.1u,vcc3p3)Vcc_1p8v_mv vcc_1p8v_mv_r 0 DC = 0V PWL(0,0, 2u,0, 2.1u,vcc1p8)Vcc_1p0v_lv vcc_1p0v_lv_r 0 DC = 0V PWL(0,0, 3u,0, 3.1u,vcc1p0)Vss vss_r 0 DC = 0V

** Current Sense ResistorRvcc_3p3v_hv vcc_3p3v_hv_r vcc_3p3v_hv 1Rvcc_1p8v_mv vcc_1p8v_mv_r vcc_1p8v_mv 1Rvcc_1p0v_lv vcc_1p0v_lv_r vcc_1p0v_lv 1Rvss vss_r vss 1

************************************************************************** Analog Core circuit - nander.cir***********************************************************************Xnand1 in1_lv in2_hv out_lv fireb_mv vcc_3p3v_hv vcc_1p8v_mv vcc_1p0v_lv vss nander

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************************************************************************** Pad***********************************************************************Xpad1 in_ext in2_hv vcc_1p0v_lv vcc_1p8v_mv vcc_3p3v_hv vss vss apad

.ENDS*************************************************************************sp_nander***********************************************************************

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AdvanceMS Example

nander.cir************************************************************************* File Name : nander.cir** Author : Rich Klinger** Date Created : 05/09/06***********************************************************************

.SUBCKT lv2hv_an FIREWALLB_MV IN_LV OUT_HV VCC_1P0V_LV+VCC_1P8V_MV VCC_3P3V_HV VSS M9 OUTB_HV INBB VSS VSS nhv L=1.00u W=5.00u AD=1.700e-12+AS=1.700e-12 PD=1.068e-05 PS=1.068e-05 M=1 M11 OUT_HV INB VSS VSS nhv L=1.00u W=5.00u AD=1.700e-12+AS=1.700e-12 PD=1.068e-05 PS=1.068e-05 M=1 M8 OUT_HV INB NET181 VCC_3P3V_HV phv L=1.00u W=10.00u AD=3.400e-12+AS=3.400e-12 PD=2.068e-05 PS=2.068e-05 M=1 M7 NET181 OUTB_HV VCC_3P3V_HV VCC_3P3V_HV phv L=1.00u W=10.00u+AD=3.400e-12 AS=3.400e-12 PD=2.068e-05 PS=2.068e-05 M=1 M4 NET169 OUT_HV VCC_3P3V_HV VCC_3P3V_HV phv L=1.00u W=10.00u+AD=3.400e-12 AS=3.400e-12 PD=2.068e-05 PS=2.068e-05 M=1 M5 OUTB_HV INBB NET169 VCC_3P3V_HV phv L=1.00u W=10.00u AD=3.400e-12+AS=3.400e-12 PD=2.068e-05 PS=2.068e-05 M=1 MN2 N5 N0 VSS VSS nlv L=0.08u W=2.40u AD=6.480e-13+AS=6.480e-13 PD=2.940e-06 PS=2.940e-06 M=1 MN1 N0 IN_LV VSS VSS nlv L=0.08u W=0.80u AD=2.160e-13+AS=2.160e-13 PD=1.340e-06 PS=1.340e-06 M=1 MN3 N6 IN_LV VSS VSS nlv L=0.08u W=2.40u AD=6.480e-13+AS=6.480e-13 PD=2.940e-06 PS=2.940e-06 M=1 MP1 N0 IN_LV VCC_1P0V_LV VCC_1P0V_LV plv L=0.08u W=0.91u AD=2.457e-13+AS=2.457e-13 PD=1.450e-06 PS=1.450e-06 M=1 MP2 N26 INB VCC_1P8V_MV VCC_1P8V_MV pmv L=0.28u W=1.60u AD=4.800e-13+AS=4.800e-13 PD=3.800e-06 PS=3.800e-06 M=1 MP3 INB N26 VCC_1P8V_MV VCC_1P8V_MV pmv L=0.28u W=1.60u AD=4.800e-13+AS=4.800e-13 PD=3.800e-06 PS=3.800e-06 M=1 MP6 INBB INB VCC_1P8V_MV VCC_1P8V_MV pmv L=0.28u W=2.04u AD=6.120e-13+AS=6.120e-13 PD=4.680e-06 PS=4.680e-06 M=1 M3 INB FIREWALLB_MV VCC_1P8V_MV VCC_1P8V_MV pmv L=0.28u W=0.96u+AD=2.880e-13 AS=2.880e-13 PD=2.520e-06 PS=2.520e-06 M=1 MN5 INB FIREWALLB_MV N6 VSS nmv L=0.28u W=2.04u AD=6.120e-13+AS=6.120e-13 PD=4.680e-06 PS=4.680e-06 M=1 MN4 N26 FIREWALLB_MV N5 VSS nmv L=0.28u W=2.04u AD=6.120e-13+AS=6.120e-13 PD=4.680e-06 PS=4.680e-06 M=1 MN6 INBB INB VSS VSS nmv L=0.28u W=2.04u AD=6.120e-13+AS=6.120e-13 PD=4.680e-06 PS=4.680e-06 M=1.ENDS

.SUBCKT hv2lv_ls IN_HV OUT_LV VCC_1P0V_LV VCC_3P3V_HV+VCCSUP_1P0V_LV VSS_1P0V_LV VSS VSSSUP_1P0V_LV M1 OUT_LV NET99 VCC_1P0V_LV VCCSUP_1P0V_LV plv L=0.08u W=0.91u+AD=2.457e-13 AS=2.457e-13 PD=1.450e-06 PS=1.450e-06 M=1 M32 OUT_LV NET99 VSS_1P0V_LV VSSSUP_1P0V_LV nlv L=0.08u W=0.66u+AD=1.782e-13 AS=1.782e-13 PD=1.200e-06 PS=1.200e-06 M=1 M0 NET99 NET131 VSS VSSSUP_1P0V_LV nhv L=0.62u W=3.00u+AD=1.020e-12 AS=1.020e-12 PD=6.680e-06 PS=6.680e-06 M=1

20Rich Klinger

AdvanceMS Example

M30 VCC_1P0V_LV NET135 NET99 VSSSUP_1P0V_LV nhv L=0.62u W=3.00u+AD=1.020e-12 AS=1.020e-12 PD=6.680e-06 PS=6.680e-06 M=1 M22 NET131 NET135 VSS VSSSUP_1P0V_LV nhv L=0.62u W=3.00u+AD=1.020e-12 AS=1.020e-12 PD=6.680e-06 PS=6.680e-06 M=1 M23 NET135 IN_HV VSS VSSSUP_1P0V_LV nhv L=0.62u W=3.00u+AD=1.020e-12 AS=1.020e-12 PD=6.680e-06 PS=6.680e-06 M=1 M24 NET131 NET135 VCC_3P3V_HV VCC_3P3V_HV phv L=0.62u W=5.30u+AD=1.802e-12 AS=1.802e-12 PD=1.128e-05 PS=1.128e-05 M=1 M25 NET135 IN_HV VCC_3P3V_HV VCC_3P3V_HV phv L=0.62u W=5.30u+AD=1.802e-12 AS=1.802e-12 PD=1.128e-05 PS=1.128e-05 M=1.ENDS

.SUBCKT nand_hv A B VCC_3P3V_HV VSS X MPB X B VCC_3P3V_HV VCC_3P3V_HV phv L=0.70u W=9.40u AD=3.196e-12+AS=3.196e-12 PD=1.948e-05 PS=1.948e-05 M=1 MPA X A VCC_3P3V_HV VCC_3P3V_HV phv L=0.70u W=9.40u AD=3.196e-12+AS=3.196e-12 PD=1.948e-05 PS=1.948e-05 M=1 MNB NET16 B VSS VSS nhv L=0.70u W=4.00u AD=1.360e-12+AS=1.360e-12 PD=8.680e-06 PS=8.680e-06 M=1 MNA X A NET16 VSS nhv L=0.70u W=4.00u AD=1.360e-12 AS=1.360e-12+PD=8.680e-06 PS=8.680e-06 M=1.ENDS

.SUBCKT nander in1_lv in2_hv out_lv fireb_mv VCC_3P3V_HV VCC_1P8V_MV VCC_1p0V_LV VSS Xls1 fireb_mv in1_lv out1_hv VCC_1P0V_LV VCC_1P8V_MV VCC_3P3V_HV VSS lv2hv_an Xnd1 out1_hv in2_hv VCC_3P3V_HV VSS nd_hv nand_hv Xls2 out1_hv OUT_LV VCC_1P0V_LV VCC_3P3V_HV VCC_1P0V_LV VSS VSS VSS hv2lv_ls.ENDS

21Rich Klinger

AdvanceMS Example

pad.cir************************************************************************* File Name : pad.cir** Author : Rich Klinger** Date Created : 05/09/06***********************************************************************

.SUBCKT apad ANALOG_PAD ANALOG_PIN VCC12 VCCMVT VCCP VSSP VSSSUP DD2 ANALOG_PAD VCCP djpmv AREA=2.601e-10 PERI=1.637e-03 R1 ANALOG_PAD ANALOG_PIN rp M=1 W=10.00u L=10.00u DD1 VSSSUP ANALOG_PAD djnmv AREA=2.601e-10 PERI=1.637e-03.ENDS

22Rich Klinger

AdvanceMS Example

add_waves.doadd wave :tb_nander:in_extadd wave :tb_nander:nt1:in_ext

add wave :tb_nander:dinadd wave :tb_nander:nt1:dinadd wave :tb_nander:nt1:lg1:din

run –all

23Rich Klinger