Advancement in Charge Trap Flash Memory Technology
11
Advancement in Charge Trap Flash Memory Technology Saied Tehrani, CTO Flash Memory Summit – August 13, 2013
Transcript of Advancement in Charge Trap Flash Memory Technology
1 © 2013 Spansion Inc.
Advancement in Charge Trap Flash Memory Technology
Saied Tehrani, CTO
Flash Memory Summit – August 13, 2013
2 © 2013 Spansion Inc.
Why Charge Trap Flash?
Floating Gate Flash
Floating Gate
(Charge Storage)
ONO
Tunnel Oxide
Control Gate
Charge Trap Flash
Charge Trap Layer
3 © 2013 Spansion Inc.
Floating Gate Scaling Limitation
Difficult to fit ONO inter-poly dielectric in Poly1 spacing Cell-to-cell interference becomes
increasingly troublesome
FG NAND Below 20nm
Poly1FG
Poly1FG
ONO ONO
Poly1spacing
Control Gate
25nm FG NAND100
10 2004 2006 2008 2010 2012
Physical limit in Poly1 spacing to accommodate ONO
Poly1 spacing
ONO Thickness X2
Critial Cell Dimensions (nm)
4 © 2013 Spansion Inc.
MirrorBit® Technology
Charge Trap Layer
Program bit 1
Read bit 2
Read bit 1
Program bit 2
Selectable Source / Drain
Selectable Source / Drain
Charge stored in two locations in each cell (doubles bit density)
Non-conducting Charge Trap Layer
Ease of manufacturing and better scalability
Planar, Symmetric Structure
5 © 2013 Spansion Inc.
MirrorBit Core Cell Scaling Trend
0.01
0.1
90nm 65nm 45nm 32nm
Cel
l Siz
e (µ
m2)
Floating Gate
MirrorBit
8Gb
6 © 2013 Spansion Inc.
Embedded Charge Trap (eCT)TM NOR Flash
Charge Trap Layer
Memory Gate
Select Gate (LV)
Based on charge-trap technology used in MirrorBit Integrated with low-power Logic process Optimized for ultra-fast read, and low power
7 © 2013 Spansion Inc.
Heterogeneous Charge Trap (HCT)TM NAND Technology
HCT film is a multi-layered stack optimized for performance and reliability Si content and thickness of each layer within HCT film are critical Shape of HCT also optimized for performance & reliability
Poly
Si
NiSi
HCT
Along Bitline Along Wordline
Poly
Si STI
HCT
8 © 2013 Spansion Inc.
HCT NAND Product Performance
Random Read Time: 25µsSequential Read (async): 20ns
System Read Performance
Page Size: 2KB (Main) + 64B (Spare)Block Size: 128KB + 4KBEndurance: 100K P/E CyclesRetention: 10 Years
HCT NAND Memory
System Write PerformancePage Program Time: 200µsBlock Erase Time: 5ms
4Gb Product
9 © 2013 Spansion Inc.
Charge Trap Technology for 3D NAND
Charge Trap Layer
10 © 2013 Spansion Inc.
Advancement in Charge Trap Flash Memory Technology
Charge Trap Flash Technology is scalable, reliable, and highly manufacturable
Standalone NOR Flash Technology based on Charge Trap and 2bits per cell has been in production for >10 years and continues to scale to smaller nodes while maintaining high level of reliability and performance
Charge Trap embedded Flash Technology integrated with advanced logic for SoC applications is demonstrated, delivering high performance and reliability
Charge Trap NAND Flash Technology is scalable to <1Xnm and can be extended to 3D
11 © 2013 Spansion Inc.
www.spansion.com
Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™ and combinations thereof are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
This document is for informational purposes only and subject to change without notice. Spansion does not represent that it is complete, accurate or up-to-date; it is provided “AS IS.” To the maximum extent permitted by law, Spansion disclaims any liability for loss or damages arising from use of or reliance on this document.
