Advanced Logic Technologies with New Materials and Structures

January 18, 2008

@IEEE ED Bangalore Chapter,at IIS, Bangalore, India

Hiroshi IWAITokyo Institute of Technology

1

First Computer Eniac: made of huge number of vacuum tubes 1946

Problems: Big size, huge power, short life time filament

2

J. E. LILIENFELD Idea of MOSFETs, 1928DEVICES FOR CONTROLLED ELECTRIC CURRENT

Filed March 28, 1928

J.E.LILIENFELD

3

Very bad interface property between the semiconductor and gate insulator

eGe

GeO Electric Shielding

CarrierScattering

Interfacial Charges

Drain Current was several orders of magnitude smaller than expectedNo one could realize MOSFETs. Even Shockley!

4

1960: First MOSFET by D. Kahng and M. Atalla

5

Top View

Al Gate

Source

Drain

Si

Si

断面

Al

SiO2

Si

Exceptionally good interface

Using Si and SiO2

1970:

1st generation of LSIs

2006:

ULSIs

1k bit DRAM Intel 32 G bit Nand Flash

6

History of gate stackShrinking, Shrinking, and Shrinking!and then, Shrinking, Shrinking, and Shrinking!

C: Capacitance V: VoltageC, V ∝ L

Switching speed CV/I Decrease

Power consumption CV2/2 Decrease

Integration density: 1/L2 Increase

1970 2007

25 nm10,000 nmGate lengthGate Oxd Thickness 100 nm 1 nm

7

Downsizing of the components has been the driving force for circuit evolution

1900 1950 1960 1970 2000

VacuumTube

Transistor IC LSI ULSI

10 cm cm mm 10 µm 100 nm10-7m10-5m10-3m10-2m10-1m

8

In 100 years, the feature size reduced by one million times.We have never experienced such a tremendous reduction in human history.

VLSI text book written 1979 predict that 0.25 micro-meter would be the limit because of direct-tunneling current through the very thin-gate oxide.

9

VLSI textbookFinally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide and fluctuations in the positions of impurities in the depletion layers begin to make the devices of smaller dimension unworkable.

10

1111B. H. Lee et al., materials today (2006)

Direct tunneling Limit of SiO2Leakage currentLimit of SiO2

High-k starts

Leakage current Limit of High-k

MOSFET gate oxide thickness trend

EOT: Equivalent Oxide Thickness to that of SiO2

Direct-tunneling effect

Potential Barrier

Wave function

12

Direct tunneling leakage was found to be OK! In 1994

Gate electrode

Si substrateGate oxide Direct tunneling leakage

current start to flow when the thickness is 3 nm.

MOSFETs with 1.5 nm gate oxide

Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.03

0.02

0.01

0.00

0.01

-0.40.0 0.5 1.0 1.5

Vd (V)

Id (m

A / μ

m)

13

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

1.6

1.2

0.8

0.4

0.0

-0.40.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.4

0.3

0.2

0.1

0.0

-0.10.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.08

0.06

0.04

0.02

0.00

-0.020.0 0.5 1.0 1.5

Vd (V)

Gate electrode

Si substrateGate oxide Direct tunneling leakage

current start to flow when the thickness is 3 nm.

IgGate leakage: Ig ∝ Gate Area ∝ Gate length (Lg)

Drain current: Id ∝ 1/Gate length (Lg)

Lg small, Then, Ig smalll, Id large, Thus, Ig/Id small

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

1.6

1.2

0.8

0.4

0.0

-0.40.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

1.6

1.2

0.8

0.4

0.0

-0.40.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.4

0.3

0.2

0.1

0.0

-0.10.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.4

0.3

0.2

0.1

0.0

-0.10.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.08

0.06

0.04

0.02

0.00

-0.020.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.08

0.06

0.04

0.02

0.00

-0.020.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.03

0.02

0.01

0.00

0.01

-0.40.0 0.5 1.0 1.5

Vd (V)

Id (m

A/ μ

m)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.03

0.02

0.01

0.00

0.01

-0.40.0 0.5 1.0 1.5

Vd (V)

Id (m

A/ μ

m)

Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm

Id

14

15Qi Xinag, ECS 2004, AMD

Downsizing limit?Channel length?

10 nm

Gate Oxd

Channel

Electronwavelength

16

5 nm gate length CMOS

Length of 18 Si atoms

Is a Real Nano Device!!

5 nm

17

H. Wakabayashi et.al, NEC

IEDM, 2003

Downsizing limit!Electronwavelength Channel length

Gate oxide thickness10 nm

Gate Oxd

Channel

Tunnelingdistance

3 nm

Atomdistance

0.3 nm18

Prediction now!

Electronwavelength

10 nm

Tunnelingdistance

3 nmMOSFET operationLg = 2 ~ 1.5 nm?Atom

distance0.3 nm

19

Below this, no one knows future!

Prediction now!Gate length

Electronwavelength

Prediction at present

10 nmPractical limitbecause of off-leakagebetween S and D?Lg = 5 nm?

Tunnelingdistance

3 nmMOSFET operationLg = 2 ~ 1.5 nm?Atom

distance0.3 nm

20But, no one knows future!

Maybe, practical limit around 5 nm.When Gate length Smaller,

Subthrehold Leakage Current Larger

Id

SubthreshouldLeakage Current

VgVth (Threshold Voltage)

Subthreshold CurrentIs OK at Single Tr.

But not OKFor Billions of Trs.

ONOFF

Vg=0V

21

Scaling Limit in MOSFET

10-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 2050Year

MPU LgJunction depthGate oxide thickness

Direct-tunneling limit in SiO2

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize

(µm

), V

olta

ge(V

)

Min. V supply

10 nm3 nm

0.3 nm

ULTIMATELIMIT

10-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 205010-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 2050Year

MPU LgJunction depthGate oxide thickness

Direct-tunneling limit in SiO2

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize

(µm

), V

olta

ge(V

)

Min. V supply

10 nm3 nm

0.3 nm

ULTIMATELIMIT

By Robert Chau, IWGI 2003

22 22

So, we are now in the limitation of downsizing?

Do you believe this or do not?

23

There is a solution!To use high-k dielectrics

K: Dielectric Constan

Thick gate high-k dielectricsThin gate SiO2Thick

Small leakageCurrent

Almost the same electric characteristics

However, very difficult and big challenge!

24

Remember MOSFET had not been realizedwithout Si/SiO2!

Historical Trend of New Material for Gate Stack

1st FET

25

LSIPMOS NMOS CMOS

IC

1960 1970 1980 1990 2000 05

MOSFETGate Stackin production

Gate insulator

Gate electrode

SiO2 SiOxNy

DoublePoly SiAl N+Poly Si

Silicide above Poly Si electrode TiSi2 CoSi2WSi2MoSi2 NiSi

Hfbase

DoubleMetal

Ni3Si4MOSFET

DRAM Capacitor

NV Memory

Analog/RF

Al2O3, ZrO2

Stack NO(Si3N4/SiO2)

R&D for high-k

Recent new high-kPure Si Period

NO, AO (Al2O3/SiO2) (O)NO, Si3N4

(O)NO, Ni3Si4Ta2O5 , Al2O3,

Ta2O5 ,

26 26

Too large high-k cause significant short channel effect

SiO2

Too largehigh-k

Gate

DrainSource

Substrate

ε r = 3.9

Gate

DrainSource

Substrate

ε r = 3.9

DrainSource

Substrate

Gateε r = 390

-2 0 2 40

0.01

0.02

0.03

0.04

0.05I d

(mA

)

Vg (V)

Lg =0.04μmVd = 0.1VEOT = 2nm

K = 3.9SiO2

K = 390Too largeHigh-k

gate

ε r = 3.9

Oxidefilm

Magnified100 timesin vertical direction

Vg= 0V, Vd=0.5V

Source Drain

gate

outsideε r = 3.9

oxide

filmε r = 390

Vg= 0V, Vd=0.5VToo largehigh-kSiO2

Penetration of lateral field from Drain through high-k causes significant short channel effects

Choice of High-k

●

● Gas or liquidat 1000 K

●H

○Radio activeHe

● ● ● ● ● ●Li Be B C N O F Ne① ● ● ● ●Na Mg Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ① ● ● ● ●K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ① ① ① ① ● ●Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○Cs Ba ★ Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn○ ○ ○ ○ ○ ○ ○ ○Fr Ra ☆ Rf Ha Sg Ns Hs Mt

○La Ce Pr Nd PmSmEu GdTb Dy Ho Er TmYｂ Lu○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr

★

☆

Candidates

● ●Na Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ● ● ● ●K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ①

○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr

★

☆

②

③

Unstable at Si interfaceSi + MOX M + SiO2①

Si + MOX MSiX + SiO 2

Si + MOX M + MSiXOY

HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability

La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer

27R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996) 27

6

2828

0 V

1.1 V

V > 1 Ve

V > 1 Vh

OxideSi

CB

VB-4

-2

0

2

-6

4

Calculated valueBand Offsets

SiO2

4.4

3.5

1.1

2.4

1.8

0.3

3.0

-0.1

2.3

Si3N4Ta2O5

SrTiO3

BaZrO3

ZrO2

Al2O3

Y2O3

La2O3

ZrSiO4HfSiO4

4.9

2.82.3

2.6 3.4

1.51.5

3.43.3

1.4

3.4

0.8

Ener

gy (e

V)

Si HfO2

1.9

2.1

LaAlO3

J Robertson, J Vac Sci Technol B 18 1785 (2000)Dielectric constant

SiO2; 4Si3N4: ~ 7Al2O3: ~ 9

Y2O3; ~10Gd2O3: ~10

HfO2; ~23La2O3: ~27

HfO2 was chosen for the 1st generationLa2O3 is more difficult material to treat

Energy Barrier Offset of La2O3

0 10 20 30 40 50Dielectric Constant

4

2

0

-2

-4

-6

SiO2

Ban

d D

isco

ntin

uity

[eV]

Si

XPS measurement by Prof. T. Hattori, INFOS 2003

29 29

30

Intel’s announcement, January 26, 2007, and IEDM Dec 2007

Hafnium-based high-k material by ALD: EOT= 1nmSpecific gate metals ( Intel’s trade secret)

Different Metals for NMOS and PMOSUse of 193nm dry lithography

From 65 nm to 45 nm Tech.Tr density: 2 times increaseTr switching power: 30% reduction Tr switching speed: 20% improvementS-D leakage power: 5 times reductionGate oxide leakage: 10 times reduction

45nm processors (Core™2 family processors "Penryn") running Windows* Vista*, Linux* etc.

45nm production in the second half of 2007 30

3131

PMOS

32Reza Arghavani, Ph.D.,Applied Materials ,IEDM 2007 Short Course

High-k with EOT = 0.5 nmMOSFET

p-type substrate

n+ channel n+source SiO2

gatedrain

p-type substrate

n+ channel n+source

High-k

gate

drain

2005 2007 2009 2011

Physical Gate Length (nm) 32 25 20 16

Equivalent Oxide Thickness (nm) 1.2 1.1 0.9 0.5, 0.8(DG)

ITRS 2006

33 33

Now, interest is High-k for EOT < 1nm

Many Problems for thinning EOT

3434

SSi Substrate

SiON IL

HfO2

Gate Metal

IL thicknessdifficult to reduce

Mobility degradation

Interfacial SiO2 or silicate layer growth

EOT IncreaseMobility degradation

O diffusiondegrade interfaces

Si diffusion degrades interfaces

Felmi Level Pinningor gate-metal workfunctioncontrol problem

This inteface propertyalso degrades Mobility

Interface: Interface StatesFixed ChargeDipole

Our resultsEOT = 0.48 nmTransistor with La2O3 gate insulator

35

36 36

Mobility degradation causes for High-k MOSFETs (HfO2, Al2O3 based oxide)Remote scattering is dominant

High-κHigh-κ

Poly-Si gate

- - -

-+

source draine-

channel

Fixed charge

Phase separation Crystallization

Remote surface roughness

Remote phonon

+-Interfacial dipole

Hf+4

O-2

S. Saito et al., IEDM 2003, S. Saito et al., ECS Symp. on ULSI Process Integration 37 37

Reza Arghavani, Ph.D.,Applied Materials ,IEDM 2007 Short Course 38

Gate DielectricResearchDevelop.Qual./Pre-Prod.Conti.Improv.

Oxynitride

Hf(Zr)-base

RE high-k(La2O3,…)

(LaAlO3)

(LaAlO3)

ITRS2003

Ternary

Epitaxial

2004hp90

2010hp45

2007hp65

2008

YearTech. node

Thinning EOT toward 0.5-0.7 nmKeeping good mobility with thinning IL

Searching new materials: La2O3 based / Rare earth oxides

ITRS 200339

Hygroscopic Properties of La2O3

Ln2O3

n-Si(100)

Ln2O3 + H2O → Ln2O3・H2O

Ln2O3・H2O → 2(LnOOH)

LnOOH + H2O → Ln(OH)3

Ln(OH)3

n-Si(100)

Ln2O3

n-Si(100)

Ln2O3 + H2O → Ln2O3・H2O

Ln2O3・H2O → 2(LnOOH)

LnOOH + H2O → Ln(OH)3

Ln(OH)3

n-Si(100)

Ln2O3

n-Si(100)

Ln2(CO3)3Ln2O3

n-Si(100)Ln2O3 + 2CO2→ Ln2(CO3)3

Ln2O3

n-Si(100)

Ln2(CO3)3Ln2O3

n-Si(100)Ln2O3 + 2CO2→ Ln2(CO3)3

40After 30 hours in clean room (temperature & humidity controlled)

41

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

0 0.5 1 1.5 2 2.5 3

EOT ( nm )

Cur

rent

den

sity

( A

/cm

2 )

Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)

[1]

[2]

[3]

[4]

[5][6]

Gate Leakage vs EOT, (Vg=|1|V)

[7]

[8] [9]

[1]

[2]

[3]

[4][5][7][8][9]

[6]La2O3

HfO2

Effect of gate workfunction

N-MOSFET: N-Poly Si gate electrode

Typical Vth = 0.25 ~ 0.6 V

P-MOS FET: P-Poly Si gate electrodeTypical Vth = -0.25 ~ -0.6 V

Vfb difference between N-Poly and P-Poly is 1.15 eV (Ideally)

P-MOSFET with N-Poly gate electrode

42

Vth -1.4 ~ -1.75 too bigdifficult to be adjusted by channel implantation

42

No FLP for La2O3Changing Pt/W ratio of gate electrode

La2O3HfO2

Voltage (V) Voltage (V)

43K.Ohmori, SSDM2006

Reza Arghavani, Ph.D.,Applied Materials ,IEDM 2007 Short Course 44

Electrical Characteristics of La2O3 n-MOSFET

Al/La2O3/p-Si/Al Process- La2O3 300 oC deposition- PDA N2 300 oC 10 min

0 1 2-1-2

0.3

0.25

0.2

0.15

0.1

0.05

0.00

100

10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

Gate voltage (V)

Dra

in c

urre

nt (m

A/µ

m) D

rain current (mA

/µm)Vd=100mV

L/W=10µm/54µm

S=87.4 mV

Vd (V)

Id (µ

A/µm

)

20 1 1.50.50

10203040506070

W/L (µm)54/10

300oC PDAEOT 1.7nm

Vg=-0.25 ~ 1.5 V

Good electrical characteristics can be obtained.K. Kakushima et al. Si Nanoelec. Workshop 2006 45

Effective Mobility of La2O3 MOSFET

High effective mobility of 312 cm2/Vs can be obtained with La2O3

0 0.2 0.4 0.6 0.8 1.00

100

200

300

400

Effective electric field (MV/cm)

Effe

ctiv

e m

obili

ty (c

m2 /V

s)Peak µeff= 312 cm2/Vs

N2 PDA 300 oC 10min

µeff @ 0.8MV/cm = 280 cm2/Vs

EOT=1.7nmL/W=10µm/54µm

K. Kakushima et al. Si Nanoelec. Workshop 2006 46

Interfacial State Density

0

100

200

300

400

500

1.0E+10 1.0E+11 1.0E+12 1.0E+13Dit (cm2e/V)

Peak

Ueff

(cm2 /V

s)

La2O3

O2 PDAN2 PDA

SiO2

0

100

200

300

400

500

1.0E+10 1.0E+11 1.0E+12 1.0E+13Dit (cm2e/V)

Peak

Ueff

(cm2 /V

s)

0

100

200

300

400

500

1.0E+10 1.0E+11 1.0E+12 1.0E+13Dit (cm2e/V)

Peak

Ueff

(cm2 /V

s)

La2O3

O2 PDAN2 PDAO2 PDAN2 PDA

SiO2PDA 300 oC

PDA 400 oCPDA 500 oC

Dit (cm-2eV-1)

0.0E+00

5.0E-09

1.0E-08

1.5E-08

2.0E-08

2.5E-08

3.0E-08

3.5E-08

4.0E-08

-4 -3 -2 -1

Vbase (V)

Icp (A

)

L/W (µm)10/54

f=100kHz

PDA300

PDA400

PDA500

Interface state density increases at higher temperature annealing

K. Kakushima et al. Si Nanoelec. Workshop 2006 47

Pt/La2O3/Pt MIM Capacitor

48

100kHz10kHz1kHz

Cap

acita

nce

dens

ity (f

F/µm

2 )

0

5

10

15

20

25

30

Voltage (V)-2 -1 0 1 2

25.6fF/µm2

Pt

Pt

La2O3

Voltage (V)0 1 2 3 4 5

10-910-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

FG anneal@500oC

Cur

rent

den

sity

(A/c

m2 )

FG anneal@300oC

thickness=8.3nm, k=21

K. Kakushima et al. Si Nanoelec. Workshop 2006

La2O3 : Heat endurance is good

La2O3 Gate Insulator for High Temperature Process

49

High temperature annealing above 500oC

SiOx based interfacial layer formation- Increase in EOT- Higher Dit

Interfacial Layer Suppression using buffer layer

148150152154156

Binding Energy (eV)

As-depo.

Si-2s600ºC La- Silicate

SiO2

Nor

mal

ized

inte

nsity

(a

.u.)

150152154156

TOA=60°

XPS analysis of La2O3/Si

148

La2O3

Si SiSc2O3

ScSiO

La2O3

Free Energy (kJ/mol)Sc2O3 ΔG= -1901 + 0.287 * TY2O3 ΔG= -1895 + 0.281 * TLa2O3 ΔG=-1785 + 0.277 * T K. Kakushima et al. Si Nanoelec. Workshop 2006

-2 -1 0 1

2.0

1.5

1.0

0.5

0

2.5

Cap

acita

nce

dens

ity (µ

F/cm

2 )

Gate voltage (V)

La2O3 (5.5nm)EOT=1.22nm

La2O3/Sc2O3 (2.1nm/2.1nm)EOT=1.03nm

RTA 900oC 2sec in N2

0

10-6

10-5

10-4

10-3

10-2

10-1

10-0

Cur

rent

den

sity

(A/c

m2 )

10-7

10-8

0.5 1.0 1.5 2.0

RTA 900oC 2secN2

La2O 3(5.5nm)

La2O 3/Sc 2O 3

(2.1nm/2.1nm)

Gate voltage (V)

Sc2O3 Buffer Layer for High Temperature Process

Leakage current suppression without degrading the CV curve

50High temperature stability can be obtained with Sc2O3 buffer layer

K. Kakushima et al. Si Nanoelec. Workshop 2006

Now, interest is High-k for EOT < 1nm

Many Problems for thinning EOT

5151

SSi Substrate

HfO2

Gate Metal

IL thicknessdifficult to reduce

Mobility degradation

Interfacial SiO2 or silicate layer growth

EOT IncreaseMobility degradation

O diffusiondegrade interfaces

Si diffusion degrades interfaces

Felmi Level Pinningor gate-metal workfunctioncontrol problem

This inteface propertyalso degrades Mobility

Interface: Interface StatesFixed ChargeDipole

What will be issues for next 25 years?Down to 2032?

ITRS Roadmap? There is no roadmap after 2020.

52

More Moore and More than MooreMoore’s Law & More

Beyond theYear of 2020,No roadmap

Question what is the other side of the cloud?

ITRS 2005 Editionhttp://strj-jeita.elisasp.net/pdf_ws_2005nendo/9A_WS2005IRC_Ishiuchi.pdf

53

World until 2020:Scaling down approach will continue.

Two issuesNew materials beyond HfSiON for

EOT = 1 ~ 0.5 nmMultigate/Fin-FET structure

World beyond 2020:Totally, new paradigm after reachingthe downsizing limit.

54

World beyond 2020:

Totally, new paradigm after reachingthe downsizing limit.

What will be?

55

Question: Will CMOS end in 2020?

56http://www.rcns.hiroshima-u.ac.jp/21coe/pdf/5th_WS/2-4-2_Hiramoto.pdf

After 2020

There is no decrease in gate length around at 10 ~ 5 nm.

4 reasons.

57

After 2020

4 reasons for no downsizing anymoreor No decrease in gate length

1. No increase of On-current (Drain current)because of already semi-ballistic conduction.

2. Increase of Off-current (Subthreshold current)

3. No decrease of gate capacitance because ofparasitic components such as sidewall

4. Increase in production cost.58

After 2020

What will be the world with no gate length reduction?

59

ITRS said before

around 2020,

Ge/III-V Channel FETs, Nanowire FET, CNT FETs would be a good candidates

after 2020,

CMOS based devices would dieand will be replaced by new functional devices

such as RTD, SET, Spin, Molecular, Atom60

My view

around 2020,

Ge/III-V Channel FETs, CNT FETs would be still too early for 2020. They are good candidates after.

after 2020,

CMOS based devices still continue for the main stream

61

We could keep the Moore’s law after 2020Without downswing the gate length

What is Moore’s law.to increase the number (#) of Tr. In a chip

Now, # of Tr. in a chip is limited by power.key issue is to reduce the power.to reduce the supply voltage is still effective

To develop devices with sufficiently high drain current under low supply voltage is important.

62

Keep increase of the number of components.Cost per components decreases!

Gordon Moore

http://www.intel.com/technology/mooreslaw/index.htm 63

Selection of MOSFET structure for high conduction:Nano-wire or Nano-tube FETs is promissing

3 methods to realize High-conduction at Low voltage１．Use 1D ballistic conduction

２．Increase number of quantum channel

３．Increase the number of wire or tube per area3D integration of wire and tubes

For suppression of Ioff, the Nanowire/tube is also good.

64

1D conduction per one quantum channel:G = 2e2/h = 77.5 µS/wire or tuberegardless of gate length and channel material

That is 77.5 mA/wire at 1V supply

This an extremely high value

However, already 20 mA was obtained experimentally in Samusung.

65

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

Bulk

DG

dia~3nm

dia~10nm

ITRS (SOI)

ITRS (DG)

ITRS(Bulk)

Si Nanowire

Ion (uA/um)

Ioff

(nA

/um

)

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

Bulk

DG

dia~3nm

dia~10nm

ITRS (SOI)

ITRS (DG)

ITRS(Bulk)

Si Nanowire

Ion (uA/um)

Ioff

(nA

/um

)

66

Increase the Number of quantum channels

Energy band of Bulk Si

Eg

By Prof. Shiraishi of Tsukuba univ.

Energy band of 3 x 3 Si wire

4 quantum channels can be used

Eg

67

Maximum number of wires per 1 µm6nm pitchBy nano-imprint method6nm

165 wires /µmFront gate type MOS

68

Surrounded gate type MOS 33 wires/µm

High-k gate insulator (4nm)Si Nano wire (Diameter 2nm)

Metal gate electrode(10nm)

Surrounded gate MOS

30nm

30nm pitch: EUV lithograpy

Increase the number of wires towards vertical dimensionSiSiGeSi

(c) Selective Etching

(b) Dry Etching(a) Si/SiGe/Siepitaxial wafer

(d) H2 Annealing

(e) Gate Oxide (f) Gate, S/D Formation

SiSiGeSi

(c) Selective Etching

(b) Dry Etching(a) Si/SiGe/Siepitaxial wafer

(d) H2 Annealing

(e) Gate Oxide (f) Gate, S/D Formation

SiSiGe

SiSiGe

...

Selective EtchingDry EtchingSi/SiGe multistacked wafer

H2 Annealing

69

70

Estimation of Ion and Ioff of 1D conduction MOSFETsFor optimum prediction: At this moment, too much optimistic and more accurate calculation is necessary, but…

1.0E-4

1.0E-3

1.0E-2

1.0E-1

1.0E+0

1.0E+1

1.0E+2

1.0E+3

100 1000 10000 100000

Vd=0.7V165WiresVd=0.5V

165WiresVd=0.7V33 WiresVd=0.5V

33 WiresVth=0.3V

Vth=0.4V

ITRS Roadmap

Ion (mA/µm)

Ioff

(nA

/µm

)

103

101

10-1

10-3

1 10 100

Front gate

Surrounded

gate

Bulk SOI FinFET

S Factor=60mV/dec

Ion

Ioff

Gate voltage (V)

Dra

in c

urre

nt (L

OG

)

2 decades

5（Vth=0.3V）7（Vth=0.4V）

0 VsupplyVth

71

2015 2020 2025 2030 20352015 2020 2025 2030 2035

Cloud

Beyond the horizon

2010

?More Moore

ITRS Beyond CMOS

? ? ?? ? ? More Moore ??

ITRS

PJT(2007~2012)

2007

Horizon

Extended CMOS: More Moore + CMOS logic

Ribbon

Tube

Extended CMOS

Si Fin, Tri-gate

Si Nano wire

III-V及びGe Nano wire

製品段階

開発段階

研究段階

Production

Research

Development

Natural direction of downsizing

Diameter = 2nm

Si Channel

Nanowire

Tube, Ribbon

Selection

-

Problem：Mechanical Stress, Roughness

1D - High conduction

More perfect crystal

CNT

Graphene

Diameter = 10nm Problem：Hiigh-k gate oxides, etching of III-V wire

Further higher conductionBy multi quantum channel Selection

Our new roadmap

High conductionBy 1D conduction

Thank you for your attention!

72