Lecture 4 Combinational Logic Implementation Technologies

ECE C03 Lecture 4 1

Lecture 4Combinational Logic Implementation

Technologies

Prith Banerjee

ECE C03

Advanced Digital Design

Spring 1998

ECE C03 Lecture 4 2

Outline

• Review of Combinational Logic Technologies• Programmable Logic Devices (PLA, PAL)• MOS Transistor Logic• READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4,

5.5 5.6, 5.7, 6.2

ECE C03 Lecture 4 3

Programmable Arrays of Logic Gates

• Until now, we learned about designing Boolean functions using discrete logic gates

• We will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structure

• Specific functions can be programmed• Can use programmable logic arrays (PLA) or

programmable array logic (PAL)

ECE C03 Lecture 4 4

PALs and PLAs

Pre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gates

Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array of AND gates Product

terms

Dense array of OR gates

Outputs

ECE C03 Lecture 4 5

Why PALs/PLAs Work

Example:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

Equations

Personality Matrix

Key to Success: Shared Product Terms

1 = asserted in term0 = negated in term- = does not participate

1 = term connected to output0 = no connection to output

Input Side:

Output Side:

Outputs Inputs Product t erm

Reuse of

t erms

A 1 - 1 - 1

B 1 0 - 0 -

C - 1 0 0 -

F 0 0 0 0 1 1

F 1 1 0 1 0 0

F 2 1 0 0 1 0

F 3 0 1 0 0 1

A B B C A C B C A

ECE C03 Lecture 4 6

Example of PALs and PLAs

All possible connections are availablebefore programming

ECE C03 Lecture 4 7

Example of PALs and PLAs (Contd)

Unwanted connections are "blown"

Note: some array structureswork by making connections

rather than breaking them

ECE C03 Lecture 4 8

Alternative Representations

Short-hand notationso we don't have todraw all the wires!

Notation for implementingF0 = A B + A' B'F1 = C D' + C' D

ECE C03 Lecture 4 9

Design Example

ABC

A

B

C

A

B

C

ABC

ABC

ABC

ABC

ABC

ABC

ABC

F1 F2 F3 F4 F5 F6

F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A xor B xor C

F6 = A xnor B xnor C

Multiple functions of A, B, C

ECE C03 Lecture 4 10

Differences Between PALs and PLAs

PAL concept — implemented by Monolithic Memories constrained topology of the OR Array

A given column of the OR arrayhas access to only a subset of

the possible product terms

PLA concept — generalized topologies in AND and OR planes


Design Example: BCD-to-Gray Code Converter

Truth Table K-maps

W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'

Minimized Functions:

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

W 0 0 0 0 0 1 1 1 1 1 X X X X X X

X 0 0 0 0 1 1 0 0 0 0 X X X X X X

Y 0 0 1 1 1 1 1 1 0 0 X X X X X X

Z 0 1 1 0 0 0 0 1 1 0 X X X X X X

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 X 1

0 1 X 1

0 1 X X

0 1 X X

K-map for W

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 0

0 1 X 0

0 0 X X

0 0 X X

K-map for X

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 0

0 1 X 0

1 1 X X

1 1 X X

K-map for Y

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 X 1

1 0 X 0

0 1 X X

1 0 X X

K-map for Z


Programmed PAL

4 product terms per each OR gate

A B C D

0

0

0

0

0

0


Code Converter: Discrete Gates

4 SSI Packages vs. 1 PLA/PAL Package!

B

\ B C

C

A

D

\ D

D W

X

Y B

B

B

B

C

C

A

D

\ A

\ C

\ B

\B \C

\A

\ D

2

2

1 1: 7404 hex inverters 2,5: 7400 quad 2-input NAND 3: 7410 t ri 3-input NAND 4: 7420 dual 4-input NAND

4

4

3

3

5

Z

1

3

2 1

2

D 1

1

4

2


Another Example: Magnitude Comparator

EQ NE LT GT

ABCD

ABCD

ABCD

ABCD

AC

AC

BD

BD

ABD

BCD

ABC

BCD

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

K-map for EQ

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 1 1

1 0 1 1

1 1 0 1

1 1 1 0

K-map for NE

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 0 0

1 0 0 0

1 1 0 1

1 1 0 0

K-map for L T

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 1 1

0 0 1 1

0 0 0 0

0 0 1 0

K-map for GT


Non-Gate Logic

AND-OR-InvertPAL/PLA

Generalized Building BlocksBeyond Simple Gates

So far we have seen:

Kinds of "Non-gate logic":

• switching circuits built from CMOS transmission gates

• multiplexer/selecter functions • decoders

• tri-state and open collector gates

• read-only memories


Steering Logic: SwitchesVoltage Controlled Switches

Gate

Oxide

Source DrainSilicon Bulk

Channel Region

Metal Gate, Oxide, Silicon Sandwich

Diffusion regions: negatively charged ions driven into Si surface

Si Bulk: positively charged ions

By "pulling" electrons to the surface, a conducting channel is formed

"n-Channel MOS"

n-type Si

p-type Si


Switching or Steering Logic

Voltage Controlled Switches

Logic 0 on gate,Source and Drain connected

Gate

Source Drain

Gate

Source Drain

nMOS Transistor

pMOS Transistor

Logic 1 on gate,Source and Drain connected


Logic Gates with Steering Logic

Logic Gates from Switches

+5V

A A

+5VA B

A B

+5VA B

A + B

Inverter NAND Gate NOR Gate

Pull-up network constructed from pMOS transistors

Pull-down network constructed from nMOS transistors


Inverter with Steering Logic

Inverter Operation

+5V

"1" "0"

+5V

"0" "1"

Input is 1Pull-up does not conductPull-down conductsOutput connected to GND

Input is 0Pull-up conductsPull-down does not conductOutput connected to VDD


NAND Gate with Steering Logic

NAND Gate Operation

A = 1, B = 1Pull-up network does not conductPull-down network conductsOutput node connected to GND

A = 0, B = 1Pull-up network has path to VDDPull-down network path brokenOutput node connected to VDD

+5V"1" "1"

"0"

+5V"0" "1"

"1"


NOR Gate with Steering Logic

NOR Gate Operation

+5V"0" "0"

"1"

+5V"1" "0"

"0"

A = 0, B = 0Pull-up network conductsPull-down network brokenOutput node at VDD

A = 1, B = 0Pull-up network brokenPull-down network conductsOutput node at GND


CMOS Transmission Gate

nMOS transistors good at passing 0's but bad at passing 1's

pMOS transistors good at passing 1's but bad at passing 0's

perfect "transmission" gate places these in parallel:

In Out

Control

Control

In Out

Control

Control

In Out

Control

Control

Switches Transistors Transmission or"Butterfly" Gate


Selection/Demultiplexing

S

S

I 0

I 1

S

S

Z

Selector: Choose I0 if S = 0 Choose I1 if S = 1

S

S

0

I

1

S

S

Z

Z

Demultiplexer: I to Z0 if S = 0 I to Z1 if S = 1


Use of Multiplexers or Demultiplexers

So far, we've only seen point-to-point connections among gates

Mux/Demux used to implement multiple source/multiple destination interconnect

A

B Z

Y

Multiplexers Demultiplexers

A

B Z

Y

Multiplexers Demultiplexers


Well-formed Switching LogicProblem with the Demux implementation: multiple outputs, but only one connected to the input!

The fix: additional logic to drive every output to a known value

Never allow outputs to "float"

0

I

S

S

Z

S

1Z

"0"

S

S

S

"0"


Complex Steering Logic ExampleN Input Tally Circuit: count # of 1's in the inputs

Conventional Logicfor 1 Input Tally

Function "0"

Zero

I1

One"0"

"1"

Zero

One

"0"

"0"

"1"

I1

Straight Through

Diagonal

Switch Logic Implementationof Tally Function

I 01

Zero 1 0

One 0 1

1

I1 Zero

One


Complex Steering LogicOperation of the 1 Input Tally Circuit

"0"

Zero

One"0"

"1"

"0"

Zero

One

"0"

"0"

"1"

"0"

Input is 0, straight through switches enabled


Complex Steering LogicOperation of 1 input Tally Circuit

"0"

Zero

One"0"

"1"

"1"

Zero

One

"0"

"0"

"1"

"1"

Input = 1, diagonal switches enabled


Complex Steering Logic ExampleExtension to the 2-input case

Conventional logic implementation

I 1

0 0 1 1

Zero

1 0 0 0

One

0 1 1 0

T wo

0 0 0 1

I 2

0 1 0 1 One

I 1

I 2

T wo

Zero


Complex Steering Logic ExampleSwitch Logic Implementation: 2-input Tally Circuit

"0"

Zero

I1

One"0"

"1"

"0"

Zero

One

I2

"0" Two

Cascade the 1-input implementation!

Zero

One

"0"

"0"

"1"

I1

Zero

One

"0"

I2

Two"0"


Complex Steering LogicOperation of 2-input implementation

Zero

One

"0"

"0"

"1"

"0"

"0"

Zero

One

"0"

"0"

"1"

"0"

"0"

"0"

"0"

"0"

"0"

"1"

"1"

"0""0"

"0"

"1"

Zero

One

"0"

"0"

"1"

"0"

"0"

Zero

One

"0"

"0"

"1"

"0"

"0"

"1"

"0"

"0"

"0"

"1"

"0"

"0"

"1""1"

"1"


Summary

• Review of Combinational Logic Implementation Technologies

• Programmable Logic Devices (PLA, PAL)• MOS Transistor Logic• NEXT LECTURE: Combinational Logic

Implementation with Multiplexers, Decoders, ROMS and FPGAs

• READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7

Lecture 4 Combinational Logic Implementation Technologies

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