Advanced Evaluation Techniques and Hardware-In-The-Loop Simulation

Darcy Bullock, P.E.ProfessorPurdue University

Requested Topics

What is Hardware-in-the-Loop (HITL)Why would you use itHistorical PerspectiveFuture Challenges

What is HITL

Testing and Evaluation of control equipment/algorithms with a simulated plant

What is HITL

Goal

Typical

HITL

SimulatedController

SimulatedPlant

Control Equipment

SimulatedPlant

Control Equipment

Real World Traffic

Why would you want to use HITL

So you can make mistakes (and learn from them) in the lab, not the field. Then when you deploy, there should be fewer surprises.So you have a controlled environment in which to experiment and quantify benefits.So you have a facility for students to try things and learn from their mistakes.Probe the “corners” of a control system without worrying about the consequences of failure

Functional Evaluation

Hmm.

What if we could control a suitcase tester with a computer.

Monitor 24 volt phase outputsGround loop detector inputs as directed.

Performance Based Evaluation

Still Do Suite Case Testing

SystemSetupw/Master

ClosedLoop

Netw ork

Closed Loop Managem ent Software

Clo

sed

Loop

Com

mun

icat

ion

Inte

rcon

nect

Cab

le

RS

-232

fro

mC

lose

d L

oop

Sof

twar

eto

Sys

tem

Mas

ter

RS

-232

fro

mC

OR

SIM

to

Sim

ulat

ion

Inte

rfac

e N

etw

ork

RS

-422

CID

Net

wor

k

CO RSIM Network S im ulation

Controller InterfaceDevice (CID)

Netw ork

RealW orldModel

Alternative to HITL

Suitcase tester Ok feature individual tester Virtually impossible to evaluate

interaction of various features on a single controller much less a “system” of controllers

“Full Up Testing”…. Plug everything together and hope they work

Historical Perspective

HITL has been used extensively by other industries for several decades.1985 at University of Vermont when Prof Bob Dawson explained his simulation system for testing/developing the control system on a PDP-11 controlling the gravel washing/production system.

Gate Control Logic

1986 worked on a speed sieve design for gate control at the IBM Essex Junction Plant1987 senior design project worked with EE student and.. he built the control hardware.. I built a simulator in Modula II.

1993

Moved to LSU in Baton Rouge, LATom Urbanik invites me to participate with his team on the IVHS Research Center ProposalDeveloped HITL concept for Smart Diamond Testing

Dec 1993 Smart Diamond Testing Concept

1994 Smart Diamond Test Plan

1994 Smart Diamond Equipment Concept

Further Developments

TexSIM developed for Smart Diamond Monty willl discuss next

CORSIM extended for hardware in the loop

Controller Interface Device(CID) ~1997

1997-Present CID Uses

Testing ACS Lite algorithmsAlgorithm developmentController feature testingLaboratory Based Instruction

1997 – Present Hardware

TTI PlatformIdaha PlatformUniv. of Minnesota PlatformNaztec/Eagle PlatformPortland PLC PlatformEmergence of a Software Platform (Univ of Arizona, Siemens, Univ of Utah)

Purdue HITL Laboratory

Project SetupChoose a real system to design and simulateObtain plans, volumes, etc. from DOTSystems that are being constructed, need to be upgraded, or were recently upgraded are ideal

Project Selections

S B L T N B W B L T E B N B L T S B E B L T W B1 2 3 4 5 6 7 8

M a i n S t r e e t T h r o u g h 1 0 sS i d e S t r e e t T h r o u g h 7 sA l l L e f t T u r n s 5 s

Y e l l o w C l e a r a n c e

R e d C l e a r a n c e

P e d e s t r i a n C l e a r a n c e

P e d e s t r i a n W a l k 7 s e c o n d s

M a x 1 G r e e n M a x 1 = 1 . 3 * S y n c h r o S p l i t

V e h i c l e E x t e n s i o nF o r 3 s e c o n d V e h E x t : V e h E x t = 3 s e c - G a p A l l o w

T p = p e r c e p t i o n t i m e ( u s u a l l y 1 s e c . )

V v = a v e r a g e v e h i c l e s p e e d o n a p p r o a c h ( m p h )

a = d e c e l e r a t i o n r a t e ( 1 0 f e e t / s 2 )W = a d j a c e n t a p p r o a c h w i d t h ( f e e t )L = a v e r a g e v e h i c l e l e n g t h ( u s u a l l y 2 0 f e e t )c = l a n e w i d t h ( f e e t )V w = a v e r a g e w a l k i n g s p e e d ( u s u a l l y 4 f e e t / s 2 )

M i n i m u m G r e e n

N o d e 1 6

P a r a m e t e r C a l c u l a t i o n

2a

V * 1 .47 T Yellow v

p

vV * 1.47

L W Red

wV

.5c - c) * Lanes of (# Clr Ped

vAllo w V * 1 .4 7

(feet)Len g th D etecto r L G ap

Project: Design ProcessCalculate timing parameters

5 5 5 510 107 7

3.0 3.0 3.0 3.04.0 4.03.5 3.5

1.5 1.5 1.5 1.52.0 2.02.0 2.0

20 20 20 2050 5040 40

3.0 3.0 3.0 3.02.5 2.52.5 2.5

15 1515 15

7 77 7

Project: Design ProcessObtain cycles, offsets, and splits from Synchro or Highway Capacity Software

Project: Real-Time Simulation

Controllers are configured with the calculated timings and coordination timings

Project: Real-Time Simulation

Simulation model is built using proposed geometries and vehicle volumes and imported into CORSIM

ITRAF CORSIM

I/O MappingVehicle sensors are mapped to the corresponding phases by the students

DetectorCards

Controller

ControllerMapping

“Final Lab Exam”1 controller plugged into 1 CID for each intersectionAll CIDs plugged in to 1 PC running CORSIMAll controllers plugged in to 1 PC running remote software

Closed Loop Monitoring Screens

PC set up to monitor the system remotely Change

controller parameters

View signal and detector status

For future HITL Challenges

Commercially viable CIDs that supports both TS2 Type 1 and Type 2 I/O AND aWell supported integration with an accepted simulation model (CORSIM)Blurring of software/hardware in the loopFormally addressing the timing latency issue between simulation clock and controller.