ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.
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Transcript of ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.
![Page 1: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/1.jpg)
ADVANCED DIGITAL DESIGNDESIGN EXERCISE I
Metastability Measurement and Analysis
![Page 2: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/2.jpg)
What you get from us
• A working late transition detector• Implementation of [PS13 and PS15]• But without the case separation• Only one FIFO is present
• Python based PC software• Automates the measurement• Prints a CSV trace to standard out
![Page 3: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/3.jpg)
Environment
• Altera Cyclone-IV FPGA• Design software: Quartus• Includes all necessary design tools
• PC software• Python program for collection of CSV traces• Analysis with program of choice (Excel, Python, MATLAB, ...)
![Page 4: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/4.jpg)
Your Task (LTD Measurement)
• Implement the case separation from [PS13, PS15]• Measure two different clock duty cycles
• One where only the master can be seen• One where master and slave are present
• Record enough data point• Per resolution time• Resolution time range
![Page 5: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/5.jpg)
Your Task (LTD MTBF)
• Analyze your measurements (MTBF vs. resolution time)• Calculate the different TAU values (master and slave, if
applicable) for all cases and simulation runs• Estimate T0 (if applicable) for all cases and simulation
runs• Plot each case in a separate plot and visualize the
above calculated parameters• Comparison plots of
• All cases in a single run• All runs for a single case
![Page 6: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/6.jpg)
Your Task (LTD Distribution)
• Analyze your measurements (TBU distribution vs. resolution time)• Plot each case in a separate plot (rising, falling, …)• Use a box-whiskers plot• Compare the mean value (MTBU) with the standard
deviation and the smallest/largest measured value for each resolution time
• What are the implications on system reliabiltiy?
![Page 7: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/7.jpg)
Your Task (Oscilloscope)
• Measure the output of a metastable flip flop using an oscilloscope
• Create a color-grade timing plot (using the oscilloscope) showing all measured traces• Use the large scope in the lab for color grading
• Adapters for the oscilloscope inputs will be in the lab
• Generate a histogram of all observed output delays
![Page 8: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/8.jpg)
LTD Example Result
![Page 9: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/9.jpg)
LTD Example Comparison
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LTD Example Box Plot
![Page 11: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/11.jpg)
LTD Example 3D Histogram
![Page 12: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/12.jpg)
References
• PS13 - T. Polzer and A. Steininger - An Approach for Efficient Metastability Characterization of FPGAs through the Designer - 19th International Symposium on Asynchronous Circuits and Systems, 2013
• PS15 - T. Polzer and A. Steininger - Measuring the Distribution of Metastable Upsets over Time - Euromicro Conference on Digital System Design, 2015
![Page 13: ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.](https://reader035.fdocuments.in/reader035/viewer/2022062315/5697bfe91a28abf838cb6a36/html5/thumbnails/13.jpg)
ADVANCED DIGITAL DESIGNDESIGN EXERCISE I
Metastability Measurement and Analysis