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4 Choosing the Right DSP Processor

4.1 Digital Signal Processing

Digital signal processing is a method of processing real world signals (represented by a sequence of

numbers) using mathematical techniques to perform transformations or extract information.

We don't speak in a digital signal. A digital signal is a language of 1s and 0s that can be processed by

mathematics. We speak in real-world, analog signals. Analog signals are real world signals that we

experience everyday - sound, light, temperature, and pressure. A digital signal is a numerical representation

of the analog signal. It may be easier and more cost effective to process these signals in the digital world. Inthe real world, we can convert these signals into digital signals through our analog-to-digital conversion

process, process the signals, and if needed, bring the signals back out to the analog world through the

digital-to-analog converter (Figure 4-1).

Figure 4-1: Digital signal processing logic.

The result is crystal clear sound, with no annoying echoes. That's a basic explanation of what a DSP does. It

takes a digital signal and processes it to improve the signal. The improvement may be clearer sound,

sharper images, or faster data. And that ability to improve signals is making new breakthroughs such as

Internet music and broadband to the home possible.

These real-time processors make up the fastest-growing segment of the semiconductor market and are

particularly well suited to handle the demands of processing information, whether as the engine of

communications applications, by providing the processing platform for the convergence of the internet and

wireless applications, or by enabling breakthroughs in medical imaging or performance audio.

4.2 Choosing the Technology

If a universal microprocessor solution existed with which every design could be realized, the electronics

industry wouldn't be a very competitive place. However, typically in most electronic designs, more than one

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processor technology can be used to implement the required functions. The trick is, of course, to choose the

one that best delivers the performance, size, power consumption, features, software and tools to get the job

done fast - without breaking the budget. After almost two decades of development, digital signal processors

continue to take the place of competitive processors. Digital signal processors are, after all, at the center of

signal processing.

4.2.1

Digital Signal Processors (DSP)A digital signal processor (DSP) is a type of microprocessor - one that is incredibly fast and powerful. A DSP

is unique because it processes data in real time. This real-time capability makes a DSP perfect for

applications that cannot tolerate any delays. For example, did you ever talk on a cell phone where two

people couldn't talk at once? You had to wait until the other person finished talking. If you both spoke

simultaneously, the signal was cut--you didn't hear the other person. With today's digital cell phones, which

use DSP, we can talk normally. The DSP processors inside cell phones process sounds so rapidly we hear

them as quickly as we can speak - in real time.

Here are just some of the advantages of designing with DSPs over other microprocessors:

Single-cycle multiply-accumulate operations

Real-time performance, simulation and emulation

Flexibility

Reliability

Increased system performance

Reduced system cost

4.2.2 Field Programmable Gate Arrays (FPGA)

Field-Programmable Gate Arrays have the capability of being reconfigurable within a system, which can be a

big advantage in applications that need multiple trial versions within development. They also offer greater

raw performance per specific operation because of the resulting dedicated logic circuit. However, FPGAs are

significantly more expensive and typically have much higher power dissipation than DSPs with similar

functionality. As such, even when FPGAsare the chosen performance technology in designs such as wireless

infrastructure, DSPs are typically used in conjunction with FPGAs to provide greater flexibility, better

price/performance ratios, and lower system power.

4.2.3Application Specific IC (ASIC)

Application-specific ICs can be tailored to perform specific functions extremely well, and can be made quite

power efficient. However, since ASICS are not field-programmable, their functionality cannot be iteratively

changed or updated while in product development. As such, every new version of the product requires a

redesign and trips through the foundry, an expensive proposition, and an impediment. Programmable DSPs,

on the other hand, can be updated without changing the silicon, merely change the software program,

greatly reducing development costs, and availing aftermarket feature enhancements with mere code

downloads. Consequently, more often than not, when we seeASICs in real time signal processing

applications, they are typically employed as bus interfaces, glue logic, and/or functional accelerators for aprogrammable DSP-based system.

4.2.4 General Purpose Procesoors (GPP)

In contrast to ASICs that are optimized for specific functions, general-purpose microprocessors (GPPs) are

best suited for performing a broad array of tasks. However, for applications in which the end product must

process answers in real time, or must do so while powered by consumer batteries, GPPs comparatively poor

real time performance and high power consumption all but rules them out. More and more, these processors

are being seen as the dinosaurs of the industry, too encumbered with PC compatibility and desktop features

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to adapt to the changing real time market place. As the world embraces tiny hand-held wireless-enabled

products that require power dissipation measured inmilliwatts-not the watts that these processors consume

- DSPs are the programmable technology of choice. That trend is bound to continue as digital Internet

appliances get smaller, faster and more portable.

4.3 Choosing the Processor

The right DSP processor for a job depends heavily on the application. One processor may perform well for

some applications, but be a poor choice for others. With this in mind, one can consider a number of features

that vary from one DSP to another in selecting a processor. These features are discussed below.

4.3.1Arithmetic Format

One of the most fundamental characteristics of a programmable digital signal processor is the type of native

arithmetic used in the processor. Most DSPs use fixed point arithmetic, while other processors

using floating-point arithmetic. Floating-point arithmetic is a more flexible and general mechanism than

fixed-point. With floating-point, system designers have access to wider dynamic range (the ratio between

the largest and smallest numbers that can be represented). As a result, floating-point DSP processors are

generally easier to program than their fixed point cousins, but usually are also more expensive and have

higher power consumption. The increased cost and power consumption result from the more complex

circuitry required within the floating-point processor, which implies a larger silicon die. The ease-of-useadvantage of floating-point processors is due to the fact that in many cases the programmer doesnt have to

be concerned about dynamic range and precision. In contrast, on a fixed-point processor, programmers

often must carefully scale signals at various stages of their programs to ensure adequate numeric precision

with the limited dynamic range of the fixed-point processor. Most high-volume, embedded applications use

fixed point processors because the priority is on low cost and, often, low power. Programmers and algorithm

designers determine the dynamic range and precision needs of their application, either analytically or

through simulation, and then add scaling operations into the code if necessary.

For applications that have extremely demanding dynamic range and precision requirements, or where ease

of development is more important than unit cost, floating-point processors have the advantage. Its possible

to perform general-purpose floating point arithmetic on a fixed-point processor by using software routines

that emulate the behavior of a floating point device. However, such software routines are usually very

expensive in terms of processor cycles. Consequently, general-purpose floating-point emulation is seldomused. A more efficient technique to boost the numeric range of fixed-point processors is block floating point,

wherein a group of numbers with different mantissas but a single, common exponent are processed as a

block of data. Block floating-point is usually handled in software, although some processors have hardware

features to assist in its implementation.

4.3.2 Data Width

All common floating-point DSPs use a 32-bit data word. For fixed-point DSPs, the most common data word

size is 16 bits. Motorolas DSP563xx family uses a 24-bit data word, however, while ZoransZR3800x family

uses a 20-bit data word. The size of the data word has a major impact on cost, because it strongly

influences the size of the chip and the number of package pins required, as well as the size of external

memory devices connected to the DSP. Therefore, designers try to use the chip with the smallest word size

that their application can tolerate.

As with the choice between fixed and floating point chips, there is often a trade-off between word size and

development complexity. For example, with a 16-bit fixed-point processor, a programmer can perform

double-precision 32-bit arithmetic operations by stringing together an appropriate combination of

instructions. (Of course, double-precision arithmetic is much slower than single-precision arithmetic.) If the

bulk of an application can be handled with single-precision arithmetic, but the application needs more

precision for a small section of the code, the selective use of double-precision arithmetic may make sense. If

most of the application requires more precision, a processor with a larger data word size is likely to be a

better choice.

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The organization of a processors memory subsystem can have a large impact on its performance. As

mentioned earlier, the MAC and other DSP operations are fundamental to many signal processing

algorithms. Fast MAC execution requires fetching an instruction word and two data words from memory at

an effective rate of once every instruction cycle. There are a variety of ways to achieve this,

including multiported memories (to permit multiple memory accesses per instruction cycle), separate

instruction and data memories (the Harvard architecture and its derivatives), and instruction caches (to

allow instructions to be fetched from cache instead of from memory, thus freeing a memory access to beused to fetch data).

Another concern is the size of the supported memory, both on- and off-chip. Most fixed-point DSPs are

aimed at the embedded systems market, where memory needs tend to be small. As a result, these

processors typically have small-to-medium on-chip memories (between 4K and 64K words), and small

external data buses. In addition, most fixed-point DSPs feature address buses of 16 bits or less, limiting the

amount of easily-accessible external memory.

Some floating-point chips provide relatively little (or no) on-chip memory, but feature large external data

buses. For example, the Texas Instruments TMS320C30 provides 6K words of on-chip memory, one 24-bit

external address bus, and one 13-bit external address bus. In contrast, the Analog Devices ADSP-21060

provides 4 Mbits of memory on-chip that can be divided between program and data memory in a variety of

ways. As with most DSP features, the best combination of memory organization, size, and number of

external buses is heavily application-dependent.

4.3.5 Ease of Development

The degree to which ease of system development is a concern depends on the application. Engineers

performing research or prototyping will probably require tools that make system development as simple as

possible. That said, items to consider when choosing a DSP are software tools (assemblers, linkers,

simulators, debuggers, compilers, code libraries, and real-time operating systems), hardware tools

(development boards and emulators), and higher-level tools (such as block-diagram based code-generation

environments). A fundamental question to ask when choosing a DSP is how the chip will be programmed.

Typically, developers choose either assembly language, a high-level languagesuch as C or Adaor a

combination of both. Surprisingly, a large portion of DSP programming is still done in assembly language.

Because DSP applications have voracious number-crunching requirements, programmers are often unable to

use compilers, which often generate assembly code that executes slowly. Rather, programmers can beforced to hand-optimize assembly code to lower execution time and code size to acceptable levels. Users of

high-level language compilers often find that the compilers work better for floating-point DSPs than for

fixed-point DSPs, for several reasons. First, most high-level languages do not have native support for

fractional arithmetic. Second, floating-point processors tend to feature more regular, less restrictive

instruction sets than smaller, fixed-point processors, and are thus better compiler targets. Third, as

mentioned, floating point processors typically support larger memory spaces than fixed-point processors,

and are thus better able to accommodate compiler-generated code, which tends to be larger than hand

crafted assembly code.

VLIW-based DSP processors, which typically use simple, orthogonal RISC-based instruction sets and have

large register files, are somewhat better compiler targets than traditional DSP processors. However, even

compilers for VLIW processors tend to generate code that is inefficient in comparison to hand-optimized

assembly code. Hence, these processors, too, are often programmed in assembly languageat least to

some degree. Whether the processor is programmed in a high-level language or in assembly language,

debugging and hardware emulation tools deserve close attention since, sadly, a great deal of time may be

spent with them. Almost all manufacturers provide instruction set simulators, which can be a tremendous

help in debugging programs before hardware is ready. If a high-level language is used, it is important to

evaluate the capabilities of the high-level language debugger: will it run with the simulator and/or the

hardware emulator? Is it a separate program from the assembly-level debugger that requires the user to

learn another user interface? Most DSP vendors provide hardware emulation tools for use with their

processors. Modern processors usually feature on-chip debugging/emulation capabilities, often accessed

through a serial interface that conforms to the IEEE 1149.1 JTAG standard for test access ports. This serial

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interface allows scan-based emulationprogrammers can load breakpoints through the interface, and then

scan the processors internal registers to view and change the contents after the processor reaches a

breakpoint.

Scan-based emulation is especially useful because debugging may be accomplished without removing the

processor from the target system. Other debugging methods, such as pod-based emulation, require

replacing the processor with a special processor emulator pod. Off-the-shelf DSP system development

boards are available from a variety of manufacturers, and can be an important resource. Development

boards can allow software to run in real-time before the final hardware is ready, and can thus provide an

important productivity boost. Additionally, some low-production-volume systems may use development

boards in the final product.

4.3.6 Multiprocessor Support

Certain computationally intensive applications with high data rates (e.g., radar and sonar) often demand

multiple DSP processors. In such cases, ease of processor interconnection (in terms of time to

design interprocessorcommunications circuitry and the cost of linking processors) and interconnection

performance (in terms of communications throughput, overhead, and latency) may be important factors.

Some DSP familiesnotably the Analog Devices ADSP-2106xprovide special-purpose hardware to ease

multiprocessor system design. ADSP-2106x processors feature bidirectional data and address buses coupled

with six bidirectional bus request lines. These allow up to six processors to be connected together via acommon external bus with elegant bus arbitration. Moreover, a unique feature of the ADSP-2106x processor

connected in this way is that each processor can access the internal memory of any other ADSP-2106x on

the shared bus. Six four-bit parallel communication ports round out the ADSP-2106xs parallel processing

features.

4.3.7 Power Consumption and Management

DSPs are increasingly being used in portable applications (such as cellular phones and portable audio

players) where power consumption is a major concern. As a result, many processor vendors are reducing

processor supply voltages and adding power management features to give programmers greater influence

over processor power consumption. Power management features available on some DSPs include:

Reduced voltage operation: Many vendors offer low-voltage (3.3-, 2.5-, or 1.8-volt) versions of their DSP

processors. These processors consume far less power than five-volt equivalents at the same clock rate.

Sleep or idle modes: Most DSPs feature modes that turn off the processors clock to all but certain

sections of the processor, reducing power consumption. In some cases, any unmasked interrupt will bring

the processor back from sleep mode, while in other cases, only a few designated external interrupt lines will

wake the processor. Some processors provide multiple sleep modes with different power savings and

wakeup latencies.

Programmable clock dividers: Some DSPs allow the processors clock frequency to be varied under

software control to use the minimum clock speed required for a particular task.

Peripheral control: Some DSPs allow the programmer to disable peripherals that are not in use.

Regardless of power management features, it is often difficult for design engineers to obtain meaningful

power consumption figures forDSPs. This is because a DSPspower consumption may vary by as much as a

factor of three depending on the instructions it executes.

Unfortunately, most vendors publish only typical or maximum power consumption numbers, usually

without specifying what constitutes a typical program. One exception is Texas Instruments, which provides

application notes that detail power consumption vs. instruction type and processor configuration.

4.3.8 Cost

Obviously, processor cost is a major concern for products that are to be produced in volume. For such

applications, designers try to use the lowest cost DSP that meets the requirements of the application, even

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To enable the design of power-sensitive systems, and to find the device that best suits the design, the

TMS320C5000 DSP platform includes over 20 devices with the optimal combination of performance,

peripheral options, small packaging and the power-efficient performance. This combination gives designers

an edge in today's portable Internet and wireless communications. With power consumption as low as

0.45 mA/MHz and performance up to 600 MIPS, the C5000 DSP platform is optimized for portable media

and communication products like digital music players, GPS receivers, portable medical equipment, feature

phones, modems, 3G cell phones, and portable imaging.

4.5.1 Platform highlights

Performance up to 900 MIPS

Ultra-low-power down to 0.33mA/MHz - enabling incredible new potential for power-

sensitive portable systems

A wide-range of devices with a rich array of peripherals allows designers to accurately target system

needs

Complete code-compatibility across all devices, allows reuse of existing code to greatly reduce

development burden

A complete development environment and support

4.5.2 Code compatible generations

The TMS320C5000 platform consists of two fully code-compatible device generations:

TMS320C54x:The C54x generation consists of over 17 code compatible devices. With a broad range of

performance and peripheral options, low-power operation and innovative architecture and instruction set,

the C54x generation gives designers effective ways of achieving high-performance, low-power operation and

low system cost.

TMS320C55x: The TMS320C55x generation contains the industrys most power-efficient DSPs and redefines

the potential of applications ranging from portable Internet appliances to high-speed wireless

communications. The rapidly-growing generation delivers ultra-low power performance through advanced

power management techniques that automatically power down inactive peripherals, memory and corefunctional units increasing battery life for portable applications.

4.5.3 Signal Processing Libraries and Peripheral Drivers

To enable to dramatically reduce the code development time, platform-specific libraries; the Signal

Processing and the Chip Support libraries contain a collection of high-level, optimized DSP function modules

and help to achieve performance higher than standard ANSI C code.

4.6 TMS320C2000 Platform Overview

The TMS320C2000 family of digital signal controllers with its performance and peripheral integration, offers

flash memory, ultra-fast A/D converters, and robust CAN modules and ease of use. The high-precision

control DSPs are as follows.

The TMS320C28xgeneration of digital signal controllers are the industry's first 32-bit DSP-based

controllers with on-board Flash memory and performance up to 150 MIPS. They target industrial control,

optical networking, and automotive control applications. The C28x core is a high performance control

optimized controller and offers up to 150 MIPS of computational bandwidth to handle numerous

sophisticated control algorithms in real-time, such assensorless speed control, random PWM, and power

factor correction.

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The TMS320C24x generation of digital signal controllers offers 20 to 40 MIPS of DSP performance along

with MCU control and with integrated Flash memory and are idea for implementing sophisticated control

algorithms in cost sensitive and space constraint applications.

Table 4-1: C2000 Fixed-point DSPs

DSPGeneration DSP Type Features Price*

C24x 16-bit dataFixed-Point

SCI, SPI, CAN, A/D, event manager,watchdog timers, on-chip Flash/ROMmemory, 20-40 MIPS

$1.95-$15

C28x 32-bit dataFixed-Point

SCI, SPI, CAN, 12-bit A/D,McBSP,watchdog timers, on-chip Flashmemory, up to 150 MIPS

$4.95 - $15

Target applications of TMS320C2000 are as follows:

1. Industrial: automation, drives,

2. Automotive: Electronic power steering, integrated starter alternator, brushless motors and pumps

3. Appliances/White Goods: Drive motors, Water Pumps, HVAC

4. Other : Hand-held power tools, Power Supplies, Optical Networking,

5. Motor Types : Single phase, Three phase, Sensored, Sensorless, AC Induction, Brushless DC,

Permanent Magnet Synchronous, Switched Reluctance,

6. Smart Sensing and Measurement: Powerline Communication Systems, Ballast Control Systems, Radar

Applications

4.7 TMS320C6000 Platform Overview

Raising the bar in performance and cost efficiency, the TMS320C6000 DSP platform offers fast DSPs running

at clock speeds up to 1 GHz. The platform consists of the TMS320C64x and TMS320C62x fixed-point

generations as well as the TMS320C67x floating-point generation. Optimal for broadband infrastructure,

performance audio and imaging applications, the C6000 DSP platform's performance ranges from 1200 to

8000 MIPS for fixed-point and 600 to 1800 MFLOPS for floating point.

4.7.1 Platform highlights

Optimized for highest performance and ease-of-use in high-level language programming with three device

generations. Fixed-point performance ranges from 1200 to 8000 MIPS and floating-point performance from

600 to 1350 MFLOPS. Memory, peripherals and co-processor combinations tailored to meet the needs of

targeted broadband infrastructure, performance audio and imaging applications. Complete softwarecompatibility across all C6000 devices, allows reuse of existing object code to greatly reduce development

burden

4.7.2 Code compatible generations

The TMS320C6000 platform consists of three fully code-compatible device generations:

TMS320C64x: The C64x fixed-point DSPs offer the industry's highest level of performance to address the

demands of the digital age. At clock rates of up to 1 GHz, C64x DSPs can process information at rates up to

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8000 MIPS with costs as low as $19.95. In addition to a high clock rate, C64x DSPs can do more work each

cycle with built-in extensions. These extensions include new instructions to accelerate performance in key

application areas such as digital communications infrastructure and video and image processing.

TMS320C62x: These first-generation fixed-point DSPs represent breakthrough technology that enables new

equipments and energizes existing implementations for multi-channel, multi-function applications, such as

wireless base stations, remote access servers (RAS), digital subscriber loop (xDSL) systems, personalized

home security systems, advanced imaging/biometrics, industrial scanners, precision instrumentation and

multi-channel telephony systems.

TMS320C67x: For designers of high-precision applications, C67x floating-point DSPs offer the speed,

precision, power savings and dynamic range to meet a wide variety of design needs. These

dynamic DSPs are the ideal solution for demanding applications like audio, medical imaging, instrumentation

and automotive. A detailed list of DSPs are given in Table 4-2

4.7.3 C Compiler

The C6000 DSP platform has a high-performance C engine with a compiler that leverages the architecture to

sustain performance while speeding design development time for high-performance applications. C

compiler/optimization tools gives the ability to balance code size and performance to meet the needs of the

application and is available free of charge.

C6000 Signal Processing Libraries and Peripheral Drivers: To enable to dramatically reduce the code

development time, platform-specific libraries; the Signal Processing and the Chip Support libraries contain a

collection of high-level, optimized DSP function modules and help to achieve performance higher than

standard ANSI C code.

Table 4-2: C67x Floating Point DSPs.

Family Name : TMS320C67x DSP Generation

Part NumberData/Program Memory (bits)

Approx.1KU Price(US$) Description

TMS320C6713-300

4KBytes L1D Data Cache;

4KBytes L1P Program Cache;64KBytes L2 Cache;192KBytes L2 SRAM

38.75

Floating-Point Digital SignalProcessor

TMS320C6713-225

4KBytes L1D Data Cache;4KBytes L1P Program Cache;64KBytes L2 Cache;192KBytes L2 SRAM

29.14

TMS320C6713-200

4KBytes L1D Data Cache;4KBytes L1P Program Cache;64KBytes L2 Cache;192KBytes L2 SRAM

22.18

TMS320C6713-167

4KBytes L1D Data Cache;4KBytes L1P Program Cache;64KBytes L2 Cache;192KBytes L2 SRAM

22.18

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To develop high-precision applications, TMS320C67x DSPs are suitable since they provide the speed,

precision, power savings and dynamic range to meet a wide variety of application needs. The structure of

C67x is shown in Figure 4-2. These dynamic DSPs are suitable for demanding applications such as medical

imaging.

Key Features

Up to 1350 MFLOPS at 225 MHz

100% code-compatible with 32-bit instructions, single and double precision

C6000 DSP platform advanced VLIW architecture

Two inter-integrated circuit (I2C) bus interfaces

Two multi-channel buffered serial ports (McBSPs)

Up to 256 Kbytes of on-chip memory

16-channel DMA controller

Up to eight 32-bit instructions executed each cycle

Eight independent, multipurpose functional units and thirty-two 32-bit registers

Advanced DSP C compiler and assembly optimizer maximize efficiency and performance

IEEE floating-point format

Packaging: 27/35-mm BGA and 28-mm TQFP options

Figure 4-2: The C67x DSPs two-level cache memory structure.

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Applications

Digital imaging

Medical ultrasound

Portable ultrasound equipment

CT scanners

Magnetic resonance imaging (Figure 4-3)

Figure 4-3: Magnetic Resonance Imaging implementation of TMS320C67 DSP.

4.9 Compiler Interface

As with modern DSPs, a C-compiler is provided to program and simulate the TMS32067x processor, so

called Code Composer Studio. Using a compiler speeds and enhances the development process, and gives

the ability to create and test real-time, embedded signal processing applications. C-compiler extends the

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capabilities to include full awareness of the DSP target by the host and real-time analysis tools. Itsuser

interface is shown in Figure 4-4.

Figure 4-4: User interface of C-compiler, Code Composer Studio.