ADS Advanced Design System
description
Transcript of ADS Advanced Design System
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2012 EEsof
2012/10/23
Volume 1
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Time Title Speaker Title Speaker Title Speaker
0830-0900
Juergen Hartung
Agilent
Move toTracks(10)
Rick Poore Ming-Chih Lin
Agilent Agilent
Shuang Cai
Agilent Aldec
1130-1150
Hsieh-Hung Hsieh Heidi Barnes
PhD,TSMC Agilent
1230-1330
JS Wu Craig Wang Keven Chang
WINSEMI Silicon Motion Agilent
Jason Chen Eric Kuo Abby Shih
Agilent Gemtek Agilent
1440-1500
Juergen Hartung Jack Hu Yoshiyuki Yanagimoto
Agilent TomTom Agilent
Nick Chin
JETCONN
Jason Chen Ming-Chih Lin
Agilent Agilent
1650-1700
A8: Real World CMOS PADesign for MobileApplications withAdvanced SimulationTechnologies
B8: SI, PI and EMI in HighSpeed Digital Design withADS
Survey & Lucky Draw
Break & Product Fair
1500-1530
A6: Complete mm-WaveFront-to-Back RFICDesign Flow
B6: Using ADS Momentumto Differentiate SignalIntegrity Issue Happeningon Board Level or ChipLevel C6: GaN Doherty Amplifier
Design Using X-Parameters
1530-1600
B7: Consideration of High-Speed Connector's SignalIntegrity with EMPro andADS
1600-1650
Lunch
1330-1400 A4: WIN PDK in ADSEnvironment IntroductionB4: The Signal Integrityand Power IntegrityAnalysis by ADS
C4: System-Level Design& Verification for FlexibleOFDM with SystemVue
Break & Product Fair
1150-1230
A3: ComprehensiveMilimeter Wave Solutionsfor TSMCs 60GHz CMOSReference Design Kit
B3: The Agilent EEsofIntegrated EDA DesignFlow for High SpeedDigital Designers: Pre-Layout, Post-Layout,Measurement
1400-1440A5: Addressing the RFNeeds in Nano-ScaleWireless Platforms
B5: Power IntegrityAnalysis for High SpeedPCB Design Using ADS
C5: Automating On-WaferMeasurements with theNew Agilent IC-CAPWaferPro
0950-1040
A1: Integrated Electro-Thermal Solution DeliversThermally Aware CircuitSimulation
B1: Validating ofCommunication SystemDesign in C, Matlab, HDLCodes with SystemVue
1040-1130
A2: A complete Designer-Oriented Device ModelVerification Solution forAdvanced Technology
B2: FPGA Simulator Workwith SystemVue
Registration and Welcome
0900-0940 Comprehensive RF Microwave Solutions for Wireless Applications
Track A(RF and Mixed Signal IC Design) Track B(Wireless and Digital system design) Track C(Test measurement implementation withSimulation technology)
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Comprehensive RF Microwave Solutions for
Wireless Applications
Dr. Juergen HartungRFIC Product Marketing & Foundry Program ManagerAgilent EEsof
October 2012
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Agenda
Introduction RF/MW Design Challenges Agilent EEsof RF/MW Solution
Device Modeling MMIC Silicon RFIC 3D RF Components RF Modules
Whats New in ADS 2012 Summary & Outlook
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RF/MW Design Challenges The Tablet Example
DataWi-Fi 802.11a/b/g/npossible: 802.11ac
Personal ConnectivityBluetooth v4.0possible: 802.11ad/WiGIG
LocationA-GPSpossible: Galileo, Beidou, GLONASS
Communications4G LTEAlso: LTE-Advanced, MIMO
HSPA, HSPA+DC-HSDPAAlso: GSM/EDGE, WCDMA, Multi-Standard Radio (MSR)
o Increasing Integration Multiple different complex systems placed in close proximityo Increasing design complexity and compactiono Concurrent design teams across companieso Verification across design domains (IC/package/board)
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Increasing RF content in a Tablet
Tablet includes 7 PA modules:
TriQuint Quad-Band GSMAvago Band 4 LTE
Avago Band 17 LTE
Skyworks Band 5 UMTS/HSPA
Skyworks Band 8 UMTS/HSPA
Avago Band 2 UMTS/HSPA
Murata/Panasonic Dual-Band
Skyworks 77468-16W-CDMA/HSDPA/HSPA+PA and duplexer module
Murata/Peregrine SP6T Rx diversity switch module
TriquintGSM PA module
AvagoBand 4 PA module
RF Modules require further integration!
Pictures are courtesy of chipworks
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Integration-dependent design challenges
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Smaller, cheaper, more integration, lower power consumption
More functionality on chip
Additional chips III-V technologies
or Silicon RFIC
SMT components or integrated on IPD chip
Embedded passives
New packaging techniques explored (TSV, 3DIC, PoP, etc.)
Small-Scale Chips + Module Single Large-Scale Silicon Chip (SoC)
if it can be done in silicon, it WILL be done in silicon
Higher levels of integration, lower cost Low breakdown voltage, Low device
gain, High loss on-chip inductors, linearity issues, poor RF models
Picture is courtesy of chipworks
RF/MW Design Segments Application perspective
RF/MMICDesigner PA, LNA
RF SiP / ModuleDesigner PAM, TxRx
PackageDesigner QFN, BGA
RF Board Designer * Radio module
Antenna Designer SMD Ant, A/D Ant
SMD Component Designer L, C, Filter, Active Devices
System Integrator Tablet, Handset, Radar, Base station,
RF SoC Designer * Transceiver IC
Modeling Engineer GaAs, Si, SiGe,GaN, LDMOS
Connector Designer SMA, USB, HDMI
Silic
on
GaA
s
*) Pictures are courtesy of chipworks
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RF/MW Design Segments Flow perspective
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RFIC
MMIC
RF ModuleRF SiP
RF Board
Design/Implementation Challenges per Segment
Accurate device models for emerging technologies
1
IC design enablement beyondbroad and qualified PDK support
2
Integration challenges with multi-technology designs4
Complete characterization ofcomponent level designs 3
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1-4
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1 Accurate Device Models for Emerging Technologies
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NeuroFET Model(Extract in IC-CAP, Simulate in ADS)
Artificial Neural Network Measurement-based FET Model Complete Solution: data acquisition, extraction and simulation in ADS)
Equations and derivatives are infinitely continuous Accurate 2nd, 3rd, Nth order effects Robust RF & DC convergence Symmetric: switch, mixer & amplifier applications (Vds
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Design/Implementation Challenges per Segment
Accurate device models for emerging technologies
1
IC design enablement beyondbroad and qualified PDK support
2
Integration challenges with multi-technology designs4
Complete characterization ofcomponent level designs 3
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MMIC/RFIC Design Enablement
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2
1-6
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Complete ADS Desktop Design FlowAgilent EEsof Chip/Module/Board Design
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Most widely used MMIC Design Platform!
MMIC
ADS 2011 PDK Support GaAs / GaN
H01U-xx H02U-xx MP15-01 PL15-xx PP10-xx PP15-xx PP25-xx PP50-xx PS50-xx PH50-xx PD50-xx >40
TQTRx TQHiP TQHBT3 TQPED TQP13 TQP15 TQP25 TQRLC TQBihemt
G28V3 G28V4 G40V4 G50V3
InGaP HBT - P2 InGaP HBT D1 InP SHBT1 InP DHBT2 GaN HEMT0.25umGaN HEMT
0.50um
under dev.
THz SchottkyDiode
ED02AH D01PH D01MH D007IH DH15IB
FD30 FD25
HP07 PH25 PPH25X HB20M HB20P BES100
Paper: WIN PDK for ADS, by JS Wu (WINSEMI)
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Getting started with MMIC DesignMMIC Design Seminar Material
Seminar Videos Presentations & Demos ADS projects Hands-on Workshops X-Parameters
http://www.agilent.com/find/eesof-mmic-seminar
Page 15
ADS2011 Complete MMIC-Module-MultiTechDesign - JS
ADS 2012 Electro-Thermal Simulator
Applications: high power RFIC / MMIC design
Deliver thermally aware circuit simulation results by including effects of on-chip temperature rise
Include effects of package and PCB Easy to set up and use from within the
ADS environment Works with all simulation types:
DC, AC, SP, HB, Transient, Envelope
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Integrated Thermal Solver
ADS LayoutADS Schematic
Paper: Integrated Electro-Thermal Solution Delivers Thermally Aware Circuit Simulation, by Rick Poore
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MMIC/RFIC Design Enablement
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ADS for Silicon RFIC Applications
Si RF Components Front-end modules (PA, Mixer, LNA-Mixer) or Antenna switches in
CMOS-SOI starting to displace discrete GaAs power components
Si-MMICs Silicon components and transceivers for millimeter wave products,
like Optical Networks ( 10 to 40Gb/s), Automotive Collision Avoidance, 60GHz WLAN
IPD Integrated Passive Device (IPD) silicon process technology for
the production of passive devices such as baluns, filters, couplers, and diplexers that are used in portable, wireless and RF applications
LDMOS RF power transistors used for basestation, broadcast /
ISM and aerospace & defense applications
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Small-scale RFIC
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ADS 2011 Extending towards Silicon RFIC Design
Schematic Entry
Simulators System Circuit EM
Data Display
Layout
DRC/LVS
DFM support
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Major (& continued) improvements with ADS 2011
Agilent Technologies Advanced Design System Selected by Sivers IMA for Front-to-Back Silicon RFIC Implementation
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We are expanding our peak-performance millimeter wave product portfolio toward silicon-based, proprietary MMIC designs to leverage the
advantages of higher integration and reduced cost,said Christer Stoij, chief technology officer at Sivers IMA.
We selected ADS for the complete front-to-back implementation of corresponding devices because it delivers proven RF circuit
simulation, integrated EM solvers and RF-relevant backend support. ADS is designed for our type of application, allowing us to introduce new unique products for E-band and V-band radio links, with full control of the
millimeter wave architecture.
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ADS 2011 RFIC Design Flow Status
Inputs from System-level
Schematic Entry
Circuit Design & Simulation
Layout
DRC/LVS
GDSII or SOC integration
EM Extraction
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Proven ADS front-end solution for RFIC Major advantages through integrated EM ADS layout provides all relevant capabilities
Automatic Metal Fill to be added Assura & Calibre DRC support for sign-off
ADS DRC covers most recurring checks ADS LVS natively supported without need for dedicated rule files
Calibre LVS supports complements offering EM-based extraction through Momentum
Parasitic Extraction support to be added
Paper: Complete mm-Wave front-to-back RFIC Flow, by Juergen Hartung
ADS 2011 PDK Support SiGe / BiCMOS / IPD
Full Front-to-Back PDKs Front-end PDKs
under dev.
SG25H3 SG13S
SG25H1 SG13G2 SGB25V
CMRF7SF CSOI7RF BiCMOS5PAeBiCMOS8HP
TSL018 CA18HB
SBC18H3
SBC18HA SBC18H2 SBC18HXL
IPD 0.18umCM013RF 018CMOS
CM090rf
CM055SIGE018
CMOS065 RF H9SOI RF
BiCMOS6GBiCMOS9MW H9SiGe
BiCMOS7RFunder dev.BiCMOS9MW
CA18QC
BiCMOS8HP
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CSOI7RF
under dev.
under dev.CS13Q1
High-Q IPD
New
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ADS 2011 RFIC Design Flow Licensing & Bundles
Inputs from System-level
Schematic Entry
Circuit Design & Simulation
Layout
DRC/LVS
GDSII or SOC integration
EM Extraction
ADS PlatformADS Core
(incl. Schematic Entry, Linear Simulation, Optimization, Monte
Carlo, Data Display, )HB, Tran, Envelope Elements
ADS Layout Elementincl. DRC & LVS,
Connectivity-driven layout, )
Momentum Element
ADS Core
HB
Layout
Momentum
W2205Bundle
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ADS Core
Circuit Sim
Layout
Momentum
W2214Bundle
New
ADS 2012 New Via Simplification for faster EM
Layers are generated for EM only Can be viewed in 3D Viewer Can be used in combination with standard layers for EM simulation
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MMIC/RFIC Design Enablement
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Agilent EEsof RFIC solutions within Virtuoso
Inputs from System-level
Schematic Entry
Layout
DRC/LVS
Parasitic Extraction
GDSII or SOC integration
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GoldenGate RFIC Design and Verification
SystemVue Verification
GoldenGate FCE
Momentum Simulator
BroadbandSPICEModel
Generator
S-parameter
Component Options
QFN Designer
Circuit Simulation GoldenGate
Inductor & Passive Component Design
Package & Bond wire modeling
RF-ESL Analysis & Design support
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New GoldenGate 2012.10 release
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TSMC 60 GHz RDK Example Covers complete RF Design Flow Top-down ESL architecture verification
Verify at every level vs. consistent 802.11ad TX/RX references
RFIC circuit simulation & verification Full characterization of complete RF transceiver
prior to tape-out
EM analysis & verification Enable EM analysis early and often through
integrated solvers
Add off-chip effects & components in overall verification
Addressing integration issues early in the design cycle
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Paper: Addressing the RF needs in nano-scale Wireless Platforms, by Jason Chen
Paper: TSMC 60 GHz reference design kit, by Hsieh-Hung Hsieh (TSMC)
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Design/Implementation Challenges per Segment
Accurate device models for emerging technologies
1
IC design enablement beyondbroad and qualified PDK support
2
Integration challenges with multi-technology designs4
Complete characterization ofcomponent level designs 3
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EMPro 3D EM Modeling Environment
Interactive, Intuitive, Efficient, 3DEM design Environment
Full Wave 3D EM FEM and FDTD Simulation Technologies
Parameterize 3D EM components for co-simulation & optimization in ADS
Transfer ADS Layouts to EMPro for additional 3D-EM simulation
Full scripting (Python) and parameterization capability
Windows & Linux
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Paper: The best 3DEM Tool for ADS, by Agilent
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New Release: EMPro 2012Electromagnetic Professional SoftwareKey New Features: New level of integration with Advanced
Design System Common database allows 3D
components built in EMPro to be placed on ADS schematics and layout directly.
New low-frequency analysis algorithm Improves accuracy
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NEW: FEM DC/Low Frequency w/iterative solver
Rollback to 1st order, direct solver.1.5 hour per freq
Legacy solver (wo LF enhancement) cannot converge below 0.1 GHz.5 hours @ 1MHz and aborted.
Iterative solver converges beyond 1 kHz, 35-50 iterations, 10 min per freq
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Design/Implementation Challenges per Segment
Accurate device models for emerging technologies
1
IC design enablement beyondbroad and qualified PDK support
2
Integration challenges with multi-technology designs4
Complete characterization ofcomponent level designs 3
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Interoperable RF Module / SiP Co-Design Flow
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4
Integration Challenges with Multi-Technologies
Amalfi AM7802 PA Front End Module
Thermal Considerations
Multiple ICs on different fabricationtechnologies
Behavioral model for PA IC(X-parameters)
Passive EM Simulation ofEntire LaminateModel Package,
solder bumps, bond wires
Model connector
Chip, module, board interactions
Enable end-to-end simulation
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Paper: Real world CMOS PA design form mobile applications with advanced simulation technologies, by Cheng-Cheng Xie
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Integration Challenges with Multi-Technologies
Amalfi AM7802 PA Front End Module
Thermal Considerations
Multiple ICs on different fabricationtechnologies
Behavioral model for PA IC(X-parameters)
Passive EM Simulation ofEntire LaminateModel Package,
solder bumps, bond wires
Model connector
Chip, module, board interactions
Enable end-to-end simulation
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Continues changes requires Interoperable Flows
Typical PA Module Possible next steps
and new constraints like board-driven chip (re-)design.
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ADS 2012: Side-by-Side EM Simulation Setup & FEM Analysis
analyze electromagnetic interactions between ICs of differing technologies and interconnects, wire bond and flip-chip solder bumps in typical in multi-chip RF PA modules.
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IC Interoperability through OpenAccess
Agilent is a member of Si2, OA Coalition and IPL Alliance
ADS 2011 moved to OpenAccess as industry-standard database
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Virtuoso Export To EMPro
Transfers shapes, materials, ports from Virtuoso into EMPro 3D modeler
Allows using both FEM and FDTD solvers
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Board/PKG Interoperability through ODB++
Board/Package Enterprise
ToolsODB++ ADFI ADS
High Capacity
Layout Pre-Processor
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Amkor Package Design Kit for ADSPredict Packaged Performance in Minutes
Configure QFN package
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Vendor Component Library
GSM/DCS band filters use many SMT parts from Murata and TDK
All SMT parts are 0201 type
Download and use ADS component library from the vendors website
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Whats New in ADS 2012 Main focus areas
New Technologies Side-by-Side FEM & DC/LF Solution Electro-Thermal Simulation NeuroFET Model
Usability Easily Share workspaces (Archive/Unarchive) Docking Windows Search & Navigator 3D EM Components Almost unbelievable Integration Layout Flight-lines replace wires in layout
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ADS 2012 User Interface Improvements
Component Search
Net NavigatorLayer Visibility
Comp Information Comp Information
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New Docking Windows
Can float the windowOr easily drag window into place
Can float the windowOr easily drag window into place
Can stack windows
Can tab the windows
Or easily drag window into place
Can stack windows
Can tab the windows
Or easily drag window into place
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New Navigator Tool Displays all the objects in a design
Traces, paths, rectangles, polygons, circles, pins, components, cell instances, etc.
Shows all the nets in a design Shows all the objects through the entire design
hierarchy Cross selection/highlighting between design and
Navigator Auto Zoom feature automatically windows in to the
target objects Works in both Layout and Schematic Easily locate objects, even in complex designs
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New Navigator Tool
Cross selection between Navigator and design
Cross selection between Navigator and design
Expand to see full design hierarchyExpand to see full design hierarchy
Easily filter what is visible in Navigator
Easily filter what is visible in Navigator
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Powerful New Search Utility
Great for Finding specific objects in large, complex designs Quickly make edits to objects fitting a specific criteria
Features Easily locate specific design objects Searches through the entire design hierarchy Type search strings in directly, or use search wizard Intuitive search language supports Boolean search strings Auto zoom opens required cell, zooms then selects object Use the search results to easily visit and edit specific objects
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Whats New in ADS 2012 New Capabilities
User Interface & Design Management
Docking & Tabbed Windows & Dialog Boxes Component Search: Find objects in the design hierarchy Net Navigator to confirm nodal connectivity Flexible Archive & Unarchive: share parts of your workspace Dozens of additional Schematic & Layout UI refinements Support for 3rd party Design Management/Version Control Tools
(Cliosoft)
Layout
Flight-wires replaces wires in layout Improved and Flexible Connectivity modes
Multi-layer Interconnect creation copy and oversize simple & complex structures
Lock components to fixed position Dimension-Line Improvements Direct mouse entry of array spacing ADS Desktop LVS Improvements Layout Command Line Editor
Cookie Cutter Remove all wires in layout
Simulation Improvements
Faster Linear Speed Automation of Linear Network Collapser in Linear Controller
Improved Convergence/Sweep behavior Ignore and Continue if encounters a convergence issue
Parallel Computing Faster Transient GPU Simulation Manager to setup and control parallel sims
With Transient/Convolution 8-pack license
Power Amplifier Design Applications Enhancements to the Load Pull DesignGuide: Added mismatch
simulation to indicate device or amplifier sensitivity to load VSWR or phase angle.
Enhancements to the Amplifier DesignGuide: Extensive update makes it easy to see amplifier performance at a specific output power or a specific amount of gain compression.
Connection Manager Instrument Support
ADS Support for PNA-X N524x series and the new PNA N522X
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Improvements to Layout ConnectivityOverview
Connectivity better reflects users intent User selectable connectivity modes Better display of missing or incorrect connections More user control over connectivity Easier editing of connectivity information
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New Flight WiresNew Flight Wires New Navigator docking window provides easy browsing of nets Highlight complete nets Highlight individual objects attached to netShow complete physical interconnect associated with a net
New Navigator docking window provides easy browsing of nets Highlight complete nets Highlight individual objects attached to netShow complete physical interconnect associated with a netRetain individual shapes
or merge objectsRetain individual shapes
or merge objects
New Copy and Oversize UtilityNew Copy and Oversize Utility
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ADS 2012 Support for Version Control SoftwareCliosoft SOS via ADS
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ADS 2012 High Speed Digital Mid-channel repeater and opto link channel
simulation based on IBIS AMI New on Sept CPL!
W2312 Transient Convolution Distributed Computing Eight-packs September CPL
W2324 High Capacity Layout Pre-processor IBIS 5.1 and IBIS 5.2 support Via drawing utility Enhanced Net Explorer S-parameter port names and differential pairings,
enhanced symbol generation Built-in DesignGuides, DesignKit, and Examples
(SI and PI) HSPICE Compatibility s_element support
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Paper: The Agilent EEsof Integrated Design Flow for High Speed Digital Designer, by Heidi Barnes
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Key RF/MW Technology Investments
Circuit SimulationMulti-TechnologyPerformanceConvergenceNonlinear StabilityParallel Computing
Physical ModelingIntegration3D Multi-layer PlanarFull 3D EMMulti-TechnologyThermal
ModelingDevice (III-IV, Si)NeuroFET/GaNBehavioral ModelingX-ParametersModel VerificationPackagingInterconnect3D passives
Complete FlowLayout Manufacturing FlowDesktop DRC & LVSPackaging
InteroperabilityOpenAccessInteroperable PDKsIntegration with IC/PCB frameworks
Wireless VerificationLTE-A Library802.11ac/ad/n LibraryRadar Library
Usability InnovationsCircuit SimulationEM-Circuit Co-SimulationInterconnect DesignDesign ManagementOptimization Cockpit
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Summary Comprehensive RF Microwave Solutions for Wireless Applications
Advanced RF design and simulation support with industry-leading RF simulation speed and capacity
Best-in-class modeling solutions for passives, interconnects, packaging and active devices
Unique RF & mm-Wave design support
Access to scalable system-level solutions from algorithm development through RF architecture exploration
Interoperable solutions for RFIC / SiP / Module / Board co-design
Leverage the most complete RF EDA portfolio for your next-generation products!
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Key benefits Best-in-class RF fidelity among todays baseband/PHY environments,
which allows baseband designers to virtualize the RF and eliminate excessmargin
Superior integration with test accelerates real-world maturity and streamlines your model-based design flow, from architecture to verification
World-class reference IP puts Agilent instrument-grade interoperability andLayer
1 compliance inside your block diagram, before you have hardware Unified, open, polymorphic modeling simplifies tool flow, reduces
department costs and supports a customizable, vendor-neutral environment
Priced for networked workgroups to maximize design re-use and capitalize on baseband and RF synergies
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1Integrated Electrothermal Solution Delivers Thermally-Aware
Circuit SimulationRick PoorePrincipal Engineer, R&DAgilent Technologies
Marc PetersenProduct ManagerAgilent Technologies
Agenda
Introduction Thermal Problems in RFIC/MMIC Design Solutions: Traditional Approaches Solutions: A New Approach
Case Study MMIC PA Design Example Electro-Thermal Simulation Thermal and Electrical Results
Conclusion and Q&A
2Copyright Agilent Technologies 2012
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The Problem: Thermal Effects Impact RFIC/MMIC DesignThermal Effects Impact RFIC/MMIC Design
High Power Devices + High Level of Integration+ High Level of Integration = On-Chip Temperature Rise
IC performance depends on device temperature
Device temperature depends on: Power dissipation Layout position IC / packaging material thermal properties
This is a nonlinear problem Thermal conductivities vary with temperature!
????
3Copyright Agilent Technologies 2012
Traditional Approach:Self-Heating Models Many transistor models now include
self-heating effects Requires accurate extraction of thermal
parameters RTH, CTH Does not include thermal coupling
between transistors Does not include impact on nearby
passive components Does not include impact of packaging
4Copyright Agilent Technologies 2012
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Traditional Approach:Stand-alone Thermal Solvers Requires user to manually transfer
layout and expand to 3-D heat sources locations power dissipation values computed device temperaturesand perform any required iteration
5Copyright Agilent Technologies 2012
Traditional Approach:Equivalent RC Thermal NetworkExtract thermal RC network from FEM data, add to schematic Must be re-extracted for any layout
change Requires device models to have
thermal nodes Large device count make cause slow
extraction of RC network Large thermal networks may cause
significant slowdown Does not account for nonlinear thermal
properties
6Copyright Agilent Technologies 2012
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7Thermal Equation
The thermal problem
c and N are both functions of temperature and spatial location (material)g is a function of temperature, time and spatial location (electrical devices)
7Copyright Agilent Technologies 2012
A New Approach Full Electro-Thermal Simulation
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Iteration loop isdone automaticallyuntil powers andtemperatures areself-consistent
Circuit SimulatorRead temperatures
Solve electrical equationsWrite power dissipation
Thermal SimulatorRead power dissipationSolve thermal equation
Write temperaturesPDISS
TDEVICES
Thermaltechnology
files
Copyright Agilent Technologies 2012
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Electro-Thermal Simulation Results
More accurate circuit simulation results, showing performance degradation due to temperature rise
3D temperature maps, providing design insight, leading to more robust layout designs
Device temperature data, to uncover potential reliability issues and failures
9Copyright Agilent Technologies 2012
Thermal Solver Technology
Provided by Gradient Design Automation Focused on IC thermal simulation
Full-chip (high capacity) 3-D FEM temperature simulation with device- and wire-level resolution
Linux-based Proven for large digital and mixed-
signal applications Used by major IC companies
On Semi, TI, AMD, Works with any IC process
GaAs, Si, SiGe, GaN,
http://www.gradient-da.com/resources/technical-papers.php
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Mixed-Signal IC
45nm Digital Block with 800k Transistors
Copyright Agilent Technologies 2012
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Agenda
Introduction Thermal Problems in RFIC/MMIC Design Solutions: Traditional Approaches Solutions: A New Approach
Case Study MMIC PA Design Example Electro-Thermal Simulation Thermal and Electrical Results
Conclusion and Q&A
11Copyright Agilent Technologies 2012
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Case Study: Two Stage LTE PA
12Copyright Agilent Technologies 2012
Two-Stage LTE PAGaAsFET; uses EEsof DemoKitGain >25 dBPout > 25 dbm with Pin >1 dbm
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Case Study: Two Stage LTE PAGain >25 dB; Pout > 25 dBm @ Pin >1 dBm
13Copyright Agilent Technologies 2012
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Two Stage LTE PA
14Copyright Agilent Technologies 2012
6- InitialDesign_layout3aa.gif
6- InitialDesign_layout3bb.gif
Stage 1 FET4 fingers100 um widePDC=900 mW
Stage 2 FET6 fingers200 um widePDC=2100 mW
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Two Stage LTE PA LayoutThermal analysis using Rth calculations
15Copyright Agilent Technologies 2012
Simple calculation of thermal resistanceRTH for each transistor
Assume power is dissipated uniformly throughout the transistors channel
FET1 channel: 100 x 46.6 um: RTH = 168 K/W Power dissipation = 900 mW
'T=RTH PDISS=168 K/W x 0.9W = 151qC T1=25+151=176qCFET2 channel: 200 x 79.9 um: RTH = 98 K/W
Power dissipation = 2100 mW'T=RTH PDISS=98 K/W x 2.1W = 206qC T2=25+206=231qC
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Two Stage LTE PA LayoutElectro-thermal simulation
16Copyright Agilent Technologies 2012
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Electrothermal Simulation Setup
17Copyright Agilent Technologies 2012
Step 1 Add an Electrothermal Controller to the schematic page
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Electrothermal Simulation Setup
18Copyright Agilent Technologies 2012
Step 2 Open the Electrothermal Controller and specify a few parameters as shown below
Thermaltechnology
Thermalboundary
conditions
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Electrothermal Simulation Setup
19Copyright Agilent Technologies 2012
Step 3 Click the Simulate button and electro-thermal simulation starts
Simulate
Thermal profiles, plots and data output results are automatically displayed at the end of simulation
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Thermal Profile @ Pin=0dBm
20Copyright Agilent Technologies 2012
Simulation time = 6 minutes
8 point input power sweep:
from -10 dBmto +4 dBm
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Thermal Profile Max @ DC
21Copyright Agilent Technologies 2012
Simulation time = 56 seconds
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Thermal Profile Max @ DC
22Copyright Agilent Technologies 2012
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Electro-thermal Device Temperatures
23Copyright Agilent Technologies 2012
Initial hand calculation with RTH predicted TFET1=176C and TFET2=231CElectrothermal results TFET1=135C and TFET2=158-181C
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Electro-thermal On vs Off3 dB loss in gain
24Copyright Agilent Technologies 2012
Electro-thermal ONElectro-thermal OFF
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Electro-thermal On vs OffHB Pin/Pout
25Copyright Agilent Technologies 2012
Electro-thermal ONElectro-thermal OFF
Pin Vs Pout
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Electro-thermal On vs OffHB Power Dissipation Vs Pin
26Copyright Agilent Technologies 2012
Electro-thermal ON
Electro-thermal OFF
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Electro-thermal On vs OffHarmonics
27Copyright Agilent Technologies 2012
Electro-thermal ONElectro-thermal OFF
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Modify the Layout of FET2Spread the fingers and place ground/thermal vias
28Copyright Agilent Technologies 2012
Initial Design Modified Design
FET2 temperatures were too high for reliability RF performance no longer met specs Modify the layout of FET2 to spread the heat out and cool the devices
TFET1 =135qC TFET2 =158-181qC TFET1 =135qC TFET2 =107-115qC Tmax
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Modified Stage 2 FET LayoutSpread out fingers and place ground/thermal vias
29Copyright Agilent Technologies 2012
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Thermal Profile of Modified Layout @ Pin=0dBm
30Copyright Agilent Technologies 2012
Initial DesignTFET2 = 158-181qCModified DesignTFET2 = 107-115qCFET1 Temp now dominates at135qC
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Thermal Profile Max @ DC of Modified Layout
31Copyright Agilent Technologies 2012
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Thermal Profile of Modified Layout
32Copyright Agilent Technologies 2012
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Electro-thermal Device Temperatures
33Copyright Agilent Technologies 2012
Original layout TFET1=135C and TFET2=158-181CModified layout TFET1=135C and TFET2=107-115C
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Modified Design - Dashed Traces
34Copyright Agilent Technologies 2012
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Modified Design - Dashed Traces
35Copyright Agilent Technologies 2012
Initial Design Electro-thermal OFFInitial Design Electro-thermal ONModified Design Electro-thermal ON
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Modified DesignHB power dissipation
36Copyright Agilent Technologies 2012
Initial Design Electro-thermal OFFInitial Design Electro-thermal ONModified Design Electro-thermal ON
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Modified Design
37Copyright Agilent Technologies 2012
Initial Design Electro-thermal OFFInitial Design Electro-thermal ONModified Design Electro-thermal ON
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Case Study: Two Stage LTE PAMounted on a QFN Package
38Copyright Agilent Technologies 2012
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Mounting the IC onto a Package
39Copyright Agilent Technologies 2012
Layer summary:725 m plastic package k=1.0
5 m metal stack on chip100 m GaAs substrate k(25)=46150 m copper lead frame k=401
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Thermal Profile of Modified Design and Package
40Copyright Agilent Technologies 2012
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Thermal Profile of Modified Design and PackageThermal profiles of all layers IC and package
41Copyright Agilent Technologies 2012
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Electro-thermal Device Temperatures
42Copyright Agilent Technologies 2012
Original layout TFET1=135C and TFET2=158-181CModified layout TFET1=135C and TFET2=107-115CModified, packaged TFET1=141C and TFET2=116-120C
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Thermal Profile of Modified Design and PackageSimulation results S-parameters
43Copyright Agilent Technologies 2012
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Thermal Profile of Modified Design and PackageSimulation results S21
44Copyright Agilent Technologies 2012
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Thermal Profile of Modified Design and PackageSimulation results Pin / Pout
45Copyright Agilent Technologies 2012
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Thermal Profile of Modified Design and PackageSimulation results HB power dissipation
46Copyright Agilent Technologies 2012
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Thermal Profile of Modified Design and PackageSimulation results fundamental and harmonics
47Copyright Agilent Technologies 2012
Agenda
Introduction Thermal Problems in RFIC/MMIC Design Solutions: Traditional Approaches Solutions: A New Approach
Case Study MMIC PA Design Example Electro-Thermal Simulation Thermal and Electrical Results
Conclusion and Q&A
48Copyright Agilent Technologies 2012
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Summary: ADS Electro-thermal Solution
Applications: high power RFIC / MMIC design
Deliver thermally aware circuit simulation results by including effects of on-chip temperature rise
Include effects of package and PCB Easy to set up and use from within
the ADS environment Works with all simulation types:
DC, AC, SP, HB, Transient, Envelope Available in ADS 2012
QUESTIONS?
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Integrated Thermal Solver
ADS LayoutADS Schematic
Copyright Agilent Technologies 2012
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A complete designer-oriented device model verification solution for
advanced technology
1
Cai ShuangSenior Application EngineerAgilent EEsof
October 2012
Agenda
Copyright 2012 Agilent Technologies2
Increasing process complexity a challenge to models Complete solutions for model verification
MQA (Model Quality Assurance) de-facto industry standard SPICE model validation platform
AMA (Advanced Model Analysis) layout dependent effects model validation platform
Whats New in MQA2012.07 and AMA 2012.07 Summary & Outlook
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Design Requirement for PDK
Copyright 2012 Agilent Technologies3
Industry standard model required Physical model and scalable model required Process variation awareness required for ensuring the yield Mismatch model for AMS design required
Model Challenge with Advanced Technology
Copyright 2012 Agilent Technologies4
Stress, Lithography and Well Proximity Effect have made models more complex
Comprehensive QA and verification on the Models are required in order to ensure design success
Foundry often encrypts the model principle for proximity models and make it more difficult for verifying the models
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When a model/library has been obtained from the foundry,it should be checked against- consistency (simulation convergence, model explosion etc.)- physical behavior- performance in different simulators- etc.
This means:Creating a lot of netlistsHandling of huge amount of data Intelligent flagging of issuesDetailed reporting & documentation
and this requires acomprehensive, flexible and customizable tool
Model QA Challenges And Requirements
5
Complete QA Solutions
Copyright 2012 Agilent Technologies6
MQA/AMA helps designers to remove uncertainties for sub-45nm technologies
MQA/AMA is flexible enough to be adjusted to any design flow and compatible to all popular EDA tools
MQA/AMA integrates the entire flow and all the related tools for PDK verification purposes
MQA/AMA can be easily adjusted for future challenges
Agilent has developed an automated yet flexible platform to access foundry proximity models with a click of button
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Accelerating Analog Silicon
Agenda
- Modeling Challenges
- Introduction to MQA (Model Quality Assurance)
- Introduction to AMA (Advanced Model Analysis)
7
End-to-end Silicon Device Modeling Flow
Copyright 2012 Agilent Technologies8
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Agilents Validation Tools
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ModelValidation
Physical Validation
Design Variability
MQA
AMA
What is MQA?
10
MQA the industry standard assurance tool that assists modeling experts and model users to perform comprehensive model QA with an knowledge-based, rule-driven approach.
It qualifies device models/libraries of ever growing complexity.It is an automated device model verification and documentation
tool that modeling engineers at IDMs/Foundries use to perform comprehensive
model QA and to release verified model files/libraries. Fabless Design Houses use to evaluate and accept the model libraries
from Foundries.
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What is MQA?
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OS, Simulators, Input Format
Copyright 2012 Agilent Technologies12
Supported operating systems Windows XP, Windows Vista, Windows 7 Linux
Supported simulators All major EDA simulators: HSPICE, SPECTRE, Eldo, SPICE3, ADS,
Golden Gate (2012H2), AFS, Titan.. Input format
Data Native MBP/MQA data format IC-CAP mdm format (2012H2)
Model Of all supported simulators
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MQA Rule-Based, Knowledge-Driven Model QA
A rule-based, knowledge-driven automatic platform for SPICE model quality assurance through device- and circuit-level figures of merit
Knowledge Device physics, technology impact on
circuit design, model-simulator interaction, key FOMs
Rules Text files to describe FOMs, PVT
coverage, expectations, graphing options, flagging criteria
Automation Plotting, analysis, flagging, reporting,
documentation
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MQA de-facto Industry Standard Acceptance Tool Minimizes costly late-stage
design surprises Comprehensive acceptance QA Design-specific checks
Increased efficiency for all design teams Consolidated QA efforts Model library version control Bridge between foundry and design
house
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MQA Ideal Solution for Library Benchmarking
Exploding varieties of libraries CAD-centric benchmarking
Cross-simulator equivalence check
Cross-model (ex., BSIM4 vs. PSP) equivalence check
Addresses key technology benchmarking challenges What has changed from previous
library release? What has improved or worsened
from 32nm to 28nm? How identical is the 2nd source
foundry to the primary foundry?
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MQA Lib Explorer
Powerful Lib Parser Parse large model libraries
Corner View / Model View
Model Analysis / Benchmark
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Apply MQA as
Qualification tool Knowledge based and rule driven Validate model file/library and measurement data
Documentation tool Overlay with measurement data Easy to customize report
Design interface (foundry interface) tool Comparison Sharing the new technology characterization
Model QA result sharing tool Bridge between foundry and design house Communication between different groups
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MQA Default Rule Sample:
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Accelerating Analog Silicon
Time Cost (2807 plots, 21 tables)
56.7%
66.7%
89.8%
Slow & Error-prone
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Example: Rule Check Idsat vs. LExample: Rule Check Idsat vs. L
[common]appliedmodel = binning, global, macro
[Group: 4:Title=Model Scalability]
[Label: 4001:title= Check Idsat vs. L] *for NMOS[Condition:(devtype=1)and(application=1 or application=2 or application=3)][Loops: X=L(start=g_lmin,stop=g_lmax,perdec=10): P=W (start=g_wmin,stop=g_wmax, num=3): P1=Vgs(vgg) : P2=Vds(vdd) : P3=Vbs(0): P4=T(tmin, tnom, tmax)][Target: y=Idsat][Check: 01:Check Trend: CheckTrend2D (p,x,y,"times=1","incAtFirst=-1"): error: Trend is not right][Check: 02:Check Kink: CheckKink2D (p,x,y): error: Kink occurs]
A rule (ASCII, customizable) is typically organized like this:1. ID and title for selection in the GUI.2. Conditions, which determine when it is valid,
i.e. when it will be executed.3. Loops, which defines the variations like bias, W/L/T sweeping,
etc.4. Target, which defines target, normally it will be Y-axis on plot.5. Check functions, to define which MQA checks to be applied,
also to define the warning message if check failed.
A rule (ASCII, customizable) is typically organized like this:1. ID and title for selection in the GUI.2. Conditions, which determine when it is valid,
i.e. when it will be executed.3. Loops, which defines the variations like bias, W/L/T sweeping,
etc.4. Target, which defines target, normally it will be Y-axis on plot.5. Check functions, to define which MQA checks to be applied,
also to define the warning message if check failed.
Inside the .rule FileA Rule file in MQA is a ASCII text file which defines how MQA performs certain checks on certain objectsunder certain conditions
tests
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Accelerating Analog Silicon
Example of MQA Check functions, called by a Rules file:CrossCheckCheckTrend
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Accelerating Analog Silicon
After all isset up,
execute theMQA test
and obtaina detailedreport
the problem isautomatically indicated !
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MQA Demos Multi-library comparison using Lib Explorer Multi-targets Table RF Applications:9S parameter 9Harmonic Balance
Statistical Applications:9NP correlation + Monte Carlo9Mismatch
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MQA Summary
As the first commercial SPICE model validation solution, MQA is the de-facto industry standard tool for SPICE model validation, comparison and documentation.
Broad customer acceptance: MQA has been widely adopted by 100+ customers around the world. Dominate in the validation market.
Comprehensive checking routines built-in. e.g. BSIM4: default 110 rules from 17 rule-groups
Support all mainstream models and simulators. Compare differences between model versions, SPICE simulators,
and foundry technologies. Powerful and Flexible Reporting Function. Easy to share QA
results.
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Accelerating Analog Silicon
Agenda
- Overview
- Introduction to MQA (Model Quality Assurance)
- Introduction to AMA (Advance Model Analysis)
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Why AMA?A MOS transistors drive capability is no longer primarily determined by its width and length. Rather, it is heavily influenced by the layout of its surrounding structures, which has become known collectively as layout dependent effects (LDEs). Stress, Lithography and Well Proximity Effects have made models more complex. Need solution to:
Verify foundry Models Access Variability using foundry input Remove Uncertainty before tape out.
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Why AMA?
Modeling approach: LVS + Macro SPICE model
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Schematic
Layout
LVS
Modified Netlist
LVS
Hea
vyM
acro Heavy
SPICE
Schematic
Layout
ExtractedNetlist
SPICE
LVS
BSIM
Customized instance
Macro Model
Layout instance correlate model parameters through equations
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45nm/32nm Special Effects
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Layout Dependent Variations
Foundry Solutions for Addressing Variability
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Proximity Models Stress Lithography Well Proximity
Proximity Model Means LVS heavy Macro SPICE model heavy LVS+Macro SPICE model 1. Verify foundry Models
2. Access Variabilityusing foundry input
Need Solution to
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What AMA does
Model QA with layout dependent parameter consideration. Sweep layout parameters and generate Test Structure automatically. Extract layout parameters Check SPICE model electrical performance vs. layout parameters. Pin-point issues or abnormal behaviors due to LDEs before Tape-Out
Built-in Modules and Flow
AMAs architecture
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SPICE Model
Netlist
SPICE
Corner modelStatistical modelMismatch
CharacterizationComparisonDocumentation
AssuraCalibreHercules
GenericRule File
Layout DB
AMA
LVS Decks PCELL or Generator
User layout or from stand cell
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Built-in Modules and FlowLayout Generation PCell mode SKILL Template mode Layout mode
Layout Extraction Mentor Graphic Calibre Synopsys Hercules & StarRCXT Cadence Assura & QRC
SPICE Simulation HSPICE or Spectre
Data Analysis
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LayoutGeneration
LayoutExtraction
SPICE simulation
Data Analysis
AMA Sample Result
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AMA directory structure
bin: contains key executable of AMA.lib: contains library files for program, such as ".so"
and ".jar" files. skill: contains SKILL files to initiate AMA program from Virtuoso.
etc: contains default settings files. icf: contains Instance Connection Files. checker: contains testing cases to check connectivity to 3rd
party tools. checkfunctions: contains built-in check functions. skill: contains built-in SKILL template files to create layout.lic: contains license related configuration files.help: contains user manual and built-in context-
sensitive help files.
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Rule File Generator
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This rule file is more complicated than MQAs and since it involves layout generation, we provide a separate module to generate rule files.
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Rule File Generator-Layout Source
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Test Bench can have the following three sources: From Foundry PCELL From SKILL based layout generator From existing or user layout
Sample Rule Syntax
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[Group: 1:Title=MOS Devices] [Condition:1] [Path: $AMAHOME/etc/tb/mos/nmos/xxxx65ng_nch.il] * user has the option to link to foundry PCELL. [SPICE: HSPICE$AMAHOME/examples/hb3v3.lib:tt:nmos] * for circuit, model is defined within circuit definition. [Loops : A1(values for A1) : A2(values for A2) : A3(values for A3)
[Target: Idsat, Vth, Ioff] [Check: 01:Check Trend: CheckTrend2D (a1,a2,a3,"times=1","incAtFirst=-1"): error: Trend issue] [Compare: CompPlot(a1,a2,a3): error: TBD]
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Example: Lithography rounding effects for 32nm
A predictive 32nm Model is usedA Litho-aware extraction deck of a 45nm technology is used (we expect more rounding effect at 32nm).
Example: Lithography rounding effects for 32nmAn AMA run is executed and is finished in less than 30 seconds. One can clearly see that the variability due to layout parameter B (OD rounding height) is almost 20% at certain A value, and if A exceeds certain value say 0.1um, OD rounding effects becomes negligible (the number may not make sense, but you get the idea).
W=60nmL=32nm
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Example: Lithography rounding effects for 32nm
And we have observed using the input from foundry, the followingplot is observed, and it obviously doesnt make sense, so user can define a criteria and let the tool pick up the issue automatically and feedback to foundry.
Example: WPE effect
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Example: WPE effect (cont.)
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AMA Summary
AMA is the extension of MQA to qualify the layout dependent effects model for cutting-edge technologies.
Built-in complete workflow for model-LVS co-validation. Technology based and rule driven. Open interface to support popular physical verification tools
and SPICE simulators. Accurately predict design margin due to process/design
variability before tape-out. Flexible to be adjusted (extended) to other applications.
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Whats New
MQA 2012.07 Java Version Update Support of Project-level Parallelism Seamless Data Flow for ICCap .mdm data format Enhanced Support of ADS (HPEESOFSIM) Support for III-V Technologies
AMA 2012.07 Expanded CDF Support
StarRCXT, Assura Support
Support of Layout Mode in Rule Generator
For more: http://edocs.soco.agilent.com/display/mqa201207/MQA+Release+Notes
Accelerating Analog Silicon
MQA/AMA in a nut shell:A tool to test simulation or measurement results under all kinds of conditions
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Drawn by: Franz Sischka
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Roadmap
Database preparation to deal with huge amount of data. More flexible parallelization to further speed-up. Continue to contribute to the seamless integration of
simulation modules with focus on the interplay and interfacing of EDA tools in order to: Enhance design effectiveness Reduce development cycle times Reduce costs
Build unified platform for modeling verification to combine MQA and AMA functionalities and more.
Accelerating Analog Silicon
Thank you for your attention !
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www.agilent.com.tw
http://210.244.49.188/library
0800-047866
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324 20 (03) 492-9666
8026251(07) 535-5035
2012Issued date : 2012 / 10
Printed in Taiwan 2012/10
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