A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body....

1

A.7 Concurrent Assignment Statements

• Used to assign a value to a signal in an architecture body.

• Four types of concurrent assignment statements– Simple signal assignment– Selected signal assignment– Conditional signal assignment– Generate assignments

2

A7.1 Simple signal assignment

Signal_name <= expression;

• Single-bit logic expression– f <= (x1 AND x2) OR x3;

• Multi-bit logic expression– C <= A AND B; -- A, B and C are 4-bit arrays

• Arithmetic expression– Sum <= X + Y; -- Sum, X and Y are 4-bit arrays

5

A7.3 Selected Signal Assignment

• Be used to set the value of a signal to one of several alternatives based on a selection criterion.

• SyntaxWITH expression SELECT

Signal_name <= expression WHEN constant_value {, expression WHEN

constant_value}

SIGNAL x1, x2, Sel, f : STD_LOGIC;

WITH Sel SELECT

f <= x1 WHEN ‘0’,

x2 WHEN OTHERS; -- 1, Z – and so on

6

• In such assignment, all possible values of the select input sel must be explicitly listed in the code. – The keyword others (all possible values not

already listed) provide an easy way to meet this requirement.

– Each WHEN clause must specify a criterion that is mutually exclusive of the one in all other WHEN clause.

Figure 6.28. VHDL code for a 4-to-1 multiplexer (Part a).

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux4to1 ;

ARCHITECTURE Behavior OF mux4to1 ISBEGIN

WITH s SELECTf <= w0 WHEN "00",

w1 WHEN "01",w2 WHEN "10",w3 WHEN OTHERS ;

END Behavior ;

7

8

A7.4 Conditional Signal Assignment

• Similar to the selected signal assignment, be used to set a signal to one of several alternative value– The conditions listed after each WHEN clause need not

to be mutually exclusive.– The condition are given a priority from the first listed to

last listed.

• SyntaxSignal_name <= expression WHEN logic_expression ELSE

{expression WHEN logic_expression ELSE}

expression;

10

A7.5 Generate statement

• Two variants:– FOR GENERATE: a convenient way to repeat

either a logic expression or a component instantiation

– IF GENERATE (seldom needed)

generate_label:

FOR index_variable IN range GENERATE

statement;

{statement;}

END GENERATE;

14

A.9 Sequential Assignment Statements

• The order of the statements in the code can affect the semantics of the code.– Using a PROCESS statement to enclose sequential

statements from concurrent statements

• Three variants of the sequential assignment statements (can appear only inside a process)– IF statement– CASE statement– LOOP statement

15

• Similar to an architecture.• Scope of VARIABLEs declaredinside the process can be usedonly by the code within theprocess.

16

A9.2 IF STATEMENT

IF Sel = ‘0’ THEN f <= x1;ELSE f <= x2;END IF;

E.g. 2-to-1 multiplexer

17

A9.3 CASE statement

CASE Sel IS WHEN ‘0’ =>

f <= x1; WHEN OTHERS =>

f <= x2;END CASE;

E.g. 2-to-1 multiplexer

18

A9.4 Loop statements

19

A9.7 Using a variable in a PROCESS

1. Multiple assignments for the signalCount within the process.Only the last assignment will have any affect.Count <= 0 will be over-riden by assignments In the loop.

2. Count <= Count + 1; describes a circuitwith feedback, which will result in Oscillations and the circuit will not be Stable.

20Figure A.24. The FOR-LOOP from Figure A.23 using a variable.

21

Figure A.25. The circuit generated from the code in Figure A.24.

Figure 6.30. VHDL code for a 2-to-4 binary decoder.


ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGINEnw <= En & w ;WITH Enw SELECT

y <= "1000" WHEN "100","0100" WHEN "101","0010" WHEN "110","0001" WHEN "111","0000" WHEN OTHERS ;

END Behavior ;

22

Figure 6.31. Specification of a 2-to-1 multiplexer using a conditional signal assignment.


ENTITY mux2to1 ISPORT ( w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;END mux2to1 ;


f <= w0 WHEN s = '0' ELSE w1 ;END Behavior ;

23

Figure 6.32. VHDL code for a priority encoder.


ENTITY priority ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;

END priority ;

ARCHITECTURE Behavior OF priority ISBEGIN

y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE"01" WHEN w(1) = '1' ELSE"00" ;

z <= '0' WHEN w = "0000" ELSE '1' ;END Behavior ;

24

Figure 6.33. Less efficient code for a priority encoder.


ENTITY priority ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;


END priority ;


WITH w SELECTy <= "00" WHEN "0001",

"01" WHEN "0010","01" WHEN "0011","10" WHEN "0100","10" WHEN "0101","10" WHEN "0110","10" WHEN "0111","11" WHEN OTHERS ;

WITH w SELECTz <= '0' WHEN "0000",

'1' WHEN OTHERS ;END Behavior ;

25

Figure 6.34. VHDL code for a four-bit comparator.

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY compare ISPORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

AeqB, AgtB, AltB : OUT STD_LOGIC ) ;END compare ;

ARCHITECTURE Behavior OF compare ISBEGIN

AeqB <= '1' WHEN A = B ELSE '0' ;AgtB <= '1' WHEN A > B ELSE '0' ;AltB <= '1' WHEN A < B ELSE '0' ;

END Behavior ;

26

Figure 6.35. The code from Figure 6.34 for signed numbers.

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;

ENTITY compare ISPORT ( A, B : IN SIGNED(3 DOWNTO 0) ;

AeqB, AgtB, AltB : OUT STD_LOGIC ) ;END compare ;

ARCHITECTURE Behavior OF compare ISBEGIN

AeqB <= '1' WHEN A = B ELSE '0' ;AgtB <= '1' WHEN A > B ELSE '0' ;AltB <= '1' WHEN A < B ELSE '0' ;

END Behavior ;

27

Figure 6.36. Code for a 16-to-1 multiplexer using a generate statement.

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.mux4to1_package.all ;

ENTITY mux16to1 ISPORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;

s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux16to1 ;

ARCHITECTURE Structure OF mux16to1 ISSIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGING1: FOR i IN 0 TO 3 GENERATE

Muxes: mux4to1 PORT MAP (w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;

END GENERATE ;Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;

28

Figure 6.37. Hierarchical code for a 4-to-16 binary decoder.


ENTITY dec4to16 ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ;

END dec4to16 ;

ARCHITECTURE Structure OF dec4to16 ISCOMPONENT dec2to4

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END COMPONENT ;SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGING1: FOR i IN 0 TO 3 GENERATE

Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) );G2: IF i=3 GENERATE

Dec_left: dec2to4 PORT MAP ( w(i DOWNTO i-1), En, m ) ;END GENERATE ;

END GENERATE ;END Structure ;

29

Figure 6.38. A 2-to-1 multiplexer specified using an if-then-else

statement


ENTITY mux2to1 IS PORT (w0, w1, s : IN STD_LOGIC ;



PROCESS ( w0, w1, s )BEGIN

IF s = '0' THENf <= w0 ;

ELSEf <= w1 ;

END IF ;END PROCESS ;

END Behavior ;

30


ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ;



PROCESS ( w0, w1, s )BEGIN

f <= w0 ;IF s = '1' THEN

f <= w1 ;END IF ;

END PROCESS ;END Behavior ;

Figure 6.39. Alternative code for a 2-to-1 multiplexer using an if-then-else statement.

Figure 6.40. A priority encoder specified using the if-then-else statement.

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY priority IS PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;


END priority ;


PROCESS ( w )BEGIN

IF w(3) = '1' THENy <= "11" ;

ELSIF w(2) = '1' THEN y <= "10" ;

ELSIF w(1) = '1' THENy <= "01" ;

ELSEy <= "00" ;

END IF ;END PROCESS ;z <= '0' WHEN w = "0000" ELSE '1' ;

END Behavior ;

31


PROCESS ( w )BEGIN

y <= "00" ;IF w(1) = '1' THEN y <= "01" ; END IF ;IF w(2) = '1' THEN y <= "10" ; END IF ;IF w(3) = '1' THEN y <= "11" ; END IF ;

z <= '1' ;IF w = "0000" THEN z <= '0' ; END IF ;


Figure 6.41. Alternative code for the priority encoder.

Figure 6.42. Code for a one-bit equality comparator.


ENTITY compare1 ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END compare1 ;

ARCHITECTURE Behavior OF compare1 ISBEGIN

PROCESS ( A, B )BEGIN

AeqB <= '0' ;IF A = B THEN

AeqB <= '1' ;END IF ;


32

Figure 6.43. An example of code that results in implied memory.


ENTITY implied ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END implied ;

ARCHITECTURE Behavior OF implied ISBEGIN

PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;

END IF ;END PROCESS ;

END Behavior ;

33

A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body....

Documents

Transcript of A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body....