A User’s Experience with SystemVerilog · A User’s Experience with SystemVerilog Jonathan...
Transcript of A User’s Experience with SystemVerilog · A User’s Experience with SystemVerilog Jonathan...
A User’s Experience withSystemVerilog
Jonathan Bromley and Michael SmithDoulos Ltd
Ringwood, U.K. BH24 1AW
[email protected]@doulos.com
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Jonathan Bromley
Michael SmithObjectives
• Practical use of SystemVerilog– Synopsys tools (VCS, Design Compiler)
• Aim for no-compromise SystemVerilog methodology– New data types wherever appropriate– Use variables everywhere - no nets!– Interfaces for better abstraction of interconnect– Transaction-driven test fixture, assertion checking
• Awareness of the landscape– Work around tool limitations - it’s very early days yet!– Note upcoming SystemVerilog 3.1a changes/enhancements
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Jonathan Bromley
Michael SmithOutline
• Overview of design and test fixture
• Using SystemVerilog in the design
• Challenges in bus modelling
• Using SystemVerilog in verification
• Challenges in transaction-based verification
Design under test (DUT)
CORDICrotatorAPB
slaveinterface
Input dataregisters
data
APBmaster
interface
APBperipheral
bus
Test stimulusgenerator
Referencemodel ofrotatorstimulus
results from DUT
Resultschecker
control
outputs
expectedresults
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Jonathan Bromley
Michael SmithDesign and Test Fixture
Design under test (DUT)
CORDICrotator
APBslave
interface
Input dataregisters
data
APBmaster
interface
APBperipheral
bus
Test stimulusgenerator
Referencemodel ofrotatorstimulus
results from DUT
Resultschecker
control
outputs
expectedresults
Legend:Legend:
SynthesisableSystemVerilog
SystemVerilogtest fixture
C software
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Jonathan Bromley
Michael Smith
Practical Problems ThatMake It Interesting
• Design needs 16 clock cycles to perform a calculation– start/ready handshake flags appear in bus-visible registers
• Test fixture must mimic software behaviour– Set up inputs– Hit start– Poll until ready– Read outputs
clock
start
inputs
ready
outputs
calculation takes16 clock cycles
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Jonathan Bromley
Michael SmithAPB Bus
• APB is a simple synchronous bus– Intended for small numbers of slow peripherals– Only one master– Only two kinds of bus cycle:– Every transfer takes
2 clock cycles
• Part of AMBA specification(ARM Ltd)
• Tailored for on-chipapplications
PCLK
PSEL
PWRITE
PADDR
PWDATA
PENABLE
PRDATA
read cycle write cycle
Read Write
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Jonathan Bromley
Michael SmithVerilog-2001 At Last!
• Life is better…– signed values, signed arithmetic– localparam– ANSI-style port declarations
• We have avoided recommending Verilog-2001 in training…– patchy tool support
• …but support is now complete in many tools
• Irritations…– can’t define localparam within generate block– multi-dimensional array ports ???
– multi-dimensional arrays– generate– named parameter association
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Jonathan Bromley
Michael SmithSynthesisable SystemVerilog
typedef struct packed { logic [15:10] Opcode; logic [9:0] Operand;} T_Instr;
typedef struct packed { logic [15:1] Junk; logic Ready;} T_StatusWord;
module ... T_Instr Instr; T_StatusWord Stat; logic [15:0] Databus; ... assign Databus = Adr[0] ? Instr: Stat;
typedef struct packed { logic [15:10] Opcode; logic [9:0] Operand;} T_Instr;
typedef struct packed { logic [15:1] Junk; logic Ready;} T_StatusWord;
module ... T_Instr Instr; T_StatusWord Stat; logic [15:0] Databus; ... assign Databus = Adr[0] ? Instr: Stat;
• Data types to match the problem
• packed struct, union for differentregisters on common bus
• Structural driver on variable– full power of variable data type system
available throughout a design
• Note: can’t mix structural andprocedural drivers on fields of apacked object
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Jonathan Bromley
Michael SmithSynthesisable SystemVerilog
• Inquiry function $bits()forparameterisation via types– Makes VHDL users very happy!
• Where to put this typedef?– SV3.1a will offer packages
module ... localparam Width = $bits (T_Instr); T_Instr Instr; logic [Width-1:0] Databus; ... assign Instr = Databus;
module ... localparam Width = $bits (T_Instr); T_Instr Instr; logic [Width-1:0] Databus; ... assign Instr = Databus;
$bits
typedef struct packed { logic [15:10] Opcode; logic [9:0] Operand;} T_Instr;
typedef struct packed { logic [15:10] Opcode; logic [9:0] Operand;} T_Instr;
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Jonathan Bromley
Michael Smith
module Top; Rst_Itf R1; Device D1(R1.RTL); Rst_Itf R2; Device D2(R2.RTL);
module Top; Rst_Itf R1; Device D1(R1.RTL); Rst_Itf R2; Device D2(R2.RTL);
Interfaces for Design
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
• Interface port is like a handle to a module instance
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
R2R1
D2D1
R1.Reset R2.Reset
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Jonathan Bromley
Michael Smith
module Top; Rst_Itf R1; Device D1(R1.RTL); Rst_Itf R2; Device D2(R2.RTL);
module Top; Rst_Itf R1; Device D1(R1.RTL); Rst_Itf R2; Device D2(R2.RTL);
Interfaces for Design
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
module Device ( Rst_Itf.RTL Wires); always @( Wires.Reset ) ...
module Device ( Rst_Itf.RTL Wires); always @( Wires.Reset ) ...
• Interface port is like a handle to a module instance
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
R2R1
D2D1
Cross-module references -synthesis issues?
Cross-module references -synthesis issues?
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Jonathan Bromley
Michael Smith
module Top; Rst_Itf R1; Device D1(R1.RTL); Rst_Itf R2; Device D2(R2.RTL);
module Top; Rst_Itf R1; Device D1(R1.RTL); Rst_Itf R2; Device D2(R2.RTL);
Interfaces for Design
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
interface Rst_Itf; logic Reset; modport RTL (input Reset); ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
module Device ( Rst_Itf.RTL Wires); always @(Wires.Reset) ...
R2R1
D2D1
modport controls visibility and direction -not yet respected in VCS7.1
modport controls visibility and direction -not yet respected in VCS7.1
Cross-module references -synthesis issues?
Cross-module references -synthesis issues?
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Jonathan Bromley
Michael SmithInterfaces in the Test Fixture
• Opportunity for transaction-level modelling via import task
jb: provide V95/SV3.1 parallel examplesjb: provide V95/SV3.1 parallel examples
module Top;
Rst_Itf R;
TestCase T(R.Beh);
Device D(R.RTL);
endmodule
module Top;
Rst_Itf R;
TestCase T(R.Beh);
Device D(R.RTL);
endmodule
interface Rst_Itf;
logic Reset;
task Pulse(input time T); ... endtask
modport Beh ( import task Pulse; );
modport RTL (input Reset);
endinterface
interface Rst_Itf;
logic Reset;
task Pulse(input time T); ... endtask
modport Beh ( import task Pulse; );
modport RTL (input Reset);
endinterface
module TestCase (Rst_Itf.Beh RstGen); initial begin RstGen.Pulse(20); ...
module TestCase (Rst_Itf.Beh RstGen); initial begin RstGen.Pulse(20); ...
module Device (Rst_Itf.RTL Wires); always @(posedge Wires.Reset) ...
module Device (Rst_Itf.RTL Wires); always @(posedge Wires.Reset) ...
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Jonathan Bromley
Michael SmithInterfaces in the Test Fixture
• Opportunity for transaction-level modelling via import task
jb: provide V95/SV3.1 parallel examplesjb: provide V95/SV3.1 parallel examples
module Top;
Rst_Itf R;
TestCase T(R.Beh);
Device D(R.RTL);
endmodule
module Top;
Rst_Itf R;
TestCase T(R.Beh);
Device D(R.RTL);
endmodule
interface Rst_Itf;
logic Reset;
task Pulse(input time T); ... endtask
modport Beh ( import task Pulse; );
modport RTL (input Reset);
endinterface
interface Rst_Itf;
logic Reset;
task Pulse(input time T); ... endtask
modport Beh ( import task Pulse; );
modport RTL (input Reset);
endinterface
module TestCase (Rst_Itf.Beh RstGen); initial begin RstGen.Pulse(20); ...
module TestCase (Rst_Itf.Beh RstGen); initial begin RstGen.Pulse(20); ...
module Device (Rst_Itf.RTL Wires); always @(posedge Wires.Reset) ...
module Device (Rst_Itf.RTL Wires); always @(posedge Wires.Reset) ...
Just like traditional BFM -but don’t need to know its
instance name in the hierarchy
Just like traditional BFM -but don’t need to know its
instance name in the hierarchy
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Jonathan Bromley
Michael SmithAssertions
• Coverage - did it happen?– automatic, inflexible in SV3.1– 3.1a adds coverpoint
PCLK
PSEL
PWRITE
PADDR
PWDATA
PENABLE
PRDATA
read cycle write cycle
property WriteDataStable; @(posedge PCLK) ((PENABLE && PWRITE) |-> $stable(PWDATA));endproperty
property WriteDataStable; @(posedge PCLK) ((PENABLE && PWRITE) |-> $stable(PWDATA));endproperty
• Natural way to describe bus activity, transactions• Permanently active checker
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Jonathan Bromley
Michael SmithSample Project Revisited
Design under test (DUT)
CORDICrotator
APBslave
interface
Input dataregisters
data
APBmaster
interface
APBperipheral
bus
Test stimulusgenerator
Referencemodel ofrotatorstimulus
results from DUT
Resultschecker
control
outputs
expectedresults
Legend:Legend:
SynthesisableSystemVerilog
SystemVerilogtest fixture
C software
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Jonathan Bromley
Michael SmithEasier C Interface
Design under test (DUT)
CORDICrotatorAPB
slaveinterface
Input dataregisters
data
APBmaster
interface
APBperipheral
bus
Test stimulusgenerator
Referencemodel ofrotatorstimulus
results from DUT
Resultschecker
control
outputs
expectedresults
extern "C" void vlog_CORDIC_model ( input int reduceNotRotate, input int angleIn, input int xIn, input int yIn, output int angleOut, output int xOut, output int yOut );
// Evaluate expected resultvlog_CORDIC_model( reduce, angle, x, y, exp_angle, exp_x, exp_y);
extern "C" void vlog_CORDIC_model ( input int reduceNotRotate, input int angleIn, input int xIn, input int yIn, output int angleOut, output int xOut, output int yOut );
// Evaluate expected resultvlog_CORDIC_model( reduce, angle, x, y, exp_angle, exp_x, exp_y);
No PLI linkage tables!No PLI linkage tables!
This is VCS 7.1’s “DirectC” -SystemVerilog3.1 has similar DPI
This is VCS 7.1’s “DirectC” -SystemVerilog3.1 has similar DPI
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Jonathan Bromley
Michael SmithEasier C Interface
Design under test (DUT)
CORDICrotatorAPB
slaveinterface
Input dataregisters
data
APBmaster
interface
APBperipheral
bus
Test stimulusgenerator
Referencemodel ofrotatorstimulus
results from DUT
Resultschecker
control
outputs
expectedresults
void vlog_CORDIC_model ( scalar reduceNotRotate, int angleIn, int xIn, int yIn, int* angleOut, int* xOut, int* yOut) {
double a, x, y, xR, yR, s, c;
// Get trig values from Verilog info x = verilog_to_trig(xIn); y = verilog_to_trig(yIn);
if (reduceNotRotate == scalar_1 ) { // Determine rotation to reduce y to 0 a = -atan2(y, x);
void vlog_CORDIC_model ( scalar reduceNotRotate, int angleIn, int xIn, int yIn, int* angleOut, int* xOut, int* yOut) {
double a, x, y, xR, yR, s, c;
// Get trig values from Verilog info x = verilog_to_trig(xIn); y = verilog_to_trig(yIn);
if (reduceNotRotate == scalar_1 ) { // Determine rotation to reduce y to 0 a = -atan2(y, x);
Plain C code -no need for PLI calls toget argument values!
Plain C code -no need for PLI calls toget argument values!
C helper functionsC helper functions verilog_to_trig
#define scalar_0 0#define scalar_1 1#define scalar_z 2#define scalar_x 3
#define scalar_0 0#define scalar_1 1#define scalar_z 2#define scalar_x 3
scalar_1
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Jonathan Bromley
Michael SmithInterfaces and Modports
Design under test (DUT)
CORDICrotatorAPB
slaveinterface
Input dataregisters
data
APBmaster
interface
APBperipheral
bus
Test stimulusgenerator
Referencemodel ofrotatorstimulus
results from DUT
Resultschecker
control
outputs
expectedresults
APB my_apb();
CORDIC DUT(my_apb.RTL_slave);
Tester t(my_apb.TF_master);
APB my_apb();
CORDIC DUT(my_apb.RTL_slave);
Tester t(my_apb.TF_master);
Instances in test fixtureInstances in test fixture
module Tester(APB.TF_master Bus); initial begin : TestSequence logic [15:0] status; ... Bus.read(16’hFFE3, status); ... end
module Tester(APB.TF_master Bus); initial begin : TestSequence logic [15:0] status; ... Bus.read(16’hFFE3, status); ... end
interface APB;
logic PCLK, PSEL, ...
modport RTL_slave ( input PCLK, input PSEL, ... );
modport TF_master ( import task read, import task write );
task read ( input [15:0] adrs, output [15:0] data ) ... endtask
endinterface
interface APB;
logic PCLK, PSEL, ...
modport RTL_slave ( input PCLK, input PSEL, ... );
modport TF_master ( import task read, import task write );
task read ( input [15:0] adrs, output [15:0] data ) ... endtask
endinterface
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Jonathan Bromley
Michael SmithInterfaces, Modports and APB
APBmaster
PRDATA
APBslave #1
PCLK,PADDR,PWRITE,PWDATA,PENABLE
PSEL#1
PRDATA#1
APBslave #N
PSEL#N
PRDATA#N
PSEL
Slave selectaddress bits
Readbackmultiplexer
PSELdecoder
All these modportsare different
All these modportsare different
This functionalitycan easily go in
each slave
This functionalitycan easily go in
each slave
How to distributethis functionality?How to distributethis functionality?
modport should modelthe slave’s hardware
interface
modport should modelthe slave’s hardware
interface
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Jonathan Bromley
Michael SmithInterfaces, Modports and APB
APBmaster
PRDATA
APBslave #1
PCLK,PADDR,PWRITE,PWDATA,PENABLE
PSEL#1
PRDATA#1
APBslave #N
PSEL#N
PRDATA#N
PSEL
Slave selectaddress bits
Readbackmultiplexer
PSELdecoder
All these modportsare different
All these modportsare different
This functionalitycan easily go in
each slave
This functionalitycan easily go in
each slave
SystemVerilog 3.1a hasgeneratable modports
SystemVerilog 3.1a hasgeneratable modports
How to distributethis functionality?How to distributethis functionality?
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Jonathan Bromley
Michael SmithConclusions
• SystemVerilog 3.1 is useful now…– incremental improvements such as .*– typedef, struct, union, packed– $bits()
– simple interfaces
• Constrained-random stimulus is important…– not investigated in this example
• We look forward to the full functionality of interfaces• DirectC is good, DPI will give same benefits AND standardisation• Assertions are powerful and convenient
– but we need SV3.1a cover, coverpoint to match capabilities ofspecialised testbench automation tools
Synthesis?Synthesis?
Synthesis?Synthesis?