Session 7 Systemverilog

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SystemVerilog For Verification Training Session 7 Sameh El-Ashry Hardware Design Verification Engineer Mentor-Graphics Egypt

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Session 7 Systemverilog

Transcript of Session 7 Systemverilog

Page 1: Session 7 Systemverilog

SystemVerilog For Verification Training

Session 7

Sameh El-Ashry

Hardware Design Verification Engineer

Mentor-Graphics Egypt

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9 Oct 2015

Randomization & Constraints (2)

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Constraint Block

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Constraint Block Examples

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Constraint Block : Overriding

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Constraint Block : Iteration

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Dynamic Constraint Changes

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Dynamic Constraint Changes in SV

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Constraint Block : Implication ( ->, if else )

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Constraint Block : dist - 1

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Constraint Block : dist - 2

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randomize()

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randomize() with

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randomize() Inline Control

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Non-OO Randomization

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Random Variable Control

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Constraint Control

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Pre and Post Randomization

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Random Case

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Random Sequences

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Weighted Random Sequences

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Random Sequence Conditionals

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Random Sequence Jumps

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Lab for Session 6(Lab -)

Instructions:

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(Lab) Simulation output

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Thank You !

Presented by Sameh El-Ashry

[email protected]

https://eg.linkedin.com/pub/sameh-el-ashry/3b/560/22b

https://eg.linkedin.com/pub/sameh-el-ashry/3b/560/22b
https://eg.linkedin.com/pub/sameh-el-ashry/3b/560/22b
https://eg.linkedin.com/pub/sameh-el-ashry/3b/560/22b
https://eg.linkedin.com/pub/sameh-el-ashry/3b/560/22b
https://eg.linkedin.com/pub/sameh-el-ashry/3b/560/22b

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