A SURVEY OF RADIATION HARDENING BY DESIGN (RHBD ... · Key words: Displacement Damage (DD),...

http://www.iaeme.com/IJECET.asp 75 [email protected]

International Journal of Electronics and Communication Engineering & Technology

(IJECET)

Volume 7, Issue 1, Jan-Feb 2016, pp. 75-86, Article ID: IJECET_07_01_008

Available online at

http://www.iaeme.com/IJECETissues.asp?JType=IJECET&VType=7&IType=1

Journal Impact Factor (2016): 8.2691 (Calculated by GISI) www.jifactor.com

ISSN Print: 0976-6464 and ISSN Online: 0976-6472

© IAEME Publication

A SURVEY OF RADIATION HARDENING

BY DESIGN (RHBD) TECHNIQUES FOR

ELECTRONIC SYSTEMS FOR SPACE

APPLICATION

Rakesh Trivedi

Ph.D. Research Scholar, EC Department,

Nirma University, Ahmedabad, Gujarat, India

Usha S Mehta

Professor, EC Department, Nirma University,

Ahmedabad, Gujarat, India

ABSTRACT

Considering the extensive usage of electronic systems in Spacecraft and

harsh radiation environment in the Space, radiation effects on electronic

systems and development of radiation hardening electronic systems have been

a topic of research. Researchers are trying to solve this problem at various

abstraction levels, starting from fabrication technology to packaging and at

system level. This paper covers an exhaustive survey on Radiation Hardening

by Design. This survey has covered the research work from nearly 80’s to

current state of art.

Key words: Displacement Damage (DD), Radiation, Radiation Hardening by

Design (RHBD), Single Event Effect (SEE), Total Ionizing Dose (TID).

Cite this Article: Rakesh Trivedi and Usha S Mehta. A Survey of Radiation

Hardening by Design (RHBD) Techniques for Electronic Systems for Space

Application. International Journal of Electronics and Communication

Engineering & Technology, 7(1), 2016, pp. 75-86.

http://www.iaeme.com/IJECET/issues.asp?JType=IJECET&VType=7&IType=1

1. INTRODUCTION

A radiation source in space includes Solar flares, Coronal mass ejections, Solar wind,

Galactic cosmic rays, Van Allen radiation belts, solar particle events etc. This

radiation environment consists of particles such as photons, electrons, neutrons, and

heavy ions. Widely, two major effects are with respect to radiation effects are 1)

Rakesh Trivedi and Usha S Mehta


Cumulative Effect 2) Single Event Effect (SEE). The classification of radiation effects

shown in Fig. 1

Figure 1 Various Radiation effects induced in electronic devices

SEE: Single Event Effect

TID: Total Ionizing Dose

DD: Displacement Damage

SET: Single Event Transient

MBU & MCU: Multiple-Bit Upset and

Multiple-Cell Upset

SEFI: Single Event Functional Interrupt

SEL: Single Event Latch-up

SEB: Single Event Burnout

SEGR: Single Event Gate Rupture

The charge particles can hit the ICs, results in non-destructive or destructive

effects depends on the charge intensity and strike location. Particle hit leads to

erroneous performance. When a particle hit introduces IC malfunctioning but does not

damage it permanently called soft-error. Whereas any permanent damage to device

due to particle hit is regard as a hard-error. Cumulative effect is long-term effect and

changes parameters of the device. Further, it divided in to two effects. One is TID

effect, which is a result of the hole trapping in gate oxide region. When any energetic

particle hit on gate of the MOSFET or at STI (Shallow Trench Isolation) region at this

condition holes are trapping inside gate oxide or STI region, which damage the

structure of the both, gate oxide as well as isolation oxide. Due to hole trapping in

gate oxide, changes the threshold voltages of the device and due to hole trapping in

isolation oxide between two devices increasing leakage current. Another effect is

Displacement Damage (DD) effect which occurs when any energetic particle displace

atoms in silicon or insulator and creates electrically active defects. DD effect also

known as TNID (Total Non-Ionizing Dose).

SEE effect is further subdividing in to six effects. In Single Event Upset effect,

upset the storage node charge in memory due to particle strike and change the logic

level. SEU are observing in storage elements like Flip-Flop, latches SRAM cells. If

SEU effect occurring multiple storage nodes in memory, it is known as MBU &

MCU. Due to SEU effect in processor, FPGAs etc. functionally of the circuits

disturbs. This effect called SEFI. Single Event Transient is an energy pulse due to

strike on sensitive node of the circuit. Sensitive nodes are off nMOS or pMOS

transistors in the circuits. Single Event Transient (SET) effect is observing in

Combinational logic circuits. If the duration of SET pulse are more than the clock

frequency of the circuit may disturb the function of the circuits or upset the memory if

SET pulse is occurs at clock edge. SEL is triggering of the thyristor (PNPN structure)

mainly exiting in CMOS circuits due to radiation. SEB effect is occurs in power

MOSFET devices when source is forward biased and drain-source current is higher

than the breakdown voltage of the parasitic structures. SEGR effect occurs when

particle damages the gate oxide insulation of the power MOSFET. A TID, DD, SEL,

SEB and SEGR effect creates permanent damage to the devices so these types of

A Survey of Radiation Hardening by Design (RHBD) Techniques For Electronic Systems for

Space Application


effects are categorised under hard error. SEU, SEFI, MBU & MCU are affects device

or circuits temporary so these effects are categorised under Soft error.

The rest of the paper is organised as Section 2 discusses different Radiation

Hardening by Design techniques, followed by conclusion.

2. RADIATION HARDENING BY DESIGN

This section presents mitigation techniques to be applying at design level to reduce

the effect of radiation. Storage elements like Flip-Flops, Latches, and SRAMs are

more sensitive elements than combinational circuits. Radiation Hardening by design

can done by two ways: 1) By Layout modification 2) By circuit design modification

2.1. Hardness by Layout Design

In order to mitigate effects like TID, SEL and SEE, two-layout design techniques are

in used 1) Enclosed Layout Transistor 2) Guard Ring. While Enclosed Layout

Transistor mitigates TID effect, SEL effects can handled better by using Guard Rings.

Layout Design modification can be brought in many different manner. The

Fig. 2(a) and Fig.2 (b) shows conventional and enclosed nMOS transistor layout.

Enclosed Layout Transistor (ELT) is not the only member of this category. Ringed

source and ringed inter-digitated design are two such layout techniques for mitigating

TID effects. All these three layout techniques focus on preventing leakage current

between source and drain. Fig.2(c) and Fig.2 (d) shows layout for Ringed Source and

Ringed inter–digitated Transistors, respectively [1].

Figure 2 (a) Conventional two edge nMOS and (b) Enclosed Layout Transistor nMOS (c)

Ringed Source Transistor (d) Ringed inter-digitated Transistor

Although, they provide compact design as compared to ELT, sometimes they are

not immune to TID effects. The most commonly used layout technique for TID

prevention is ELT, which is briefly describing as follow:

2.1.1. Enclosed Layout Transistor

In the beginning, this type of layout design proposed to prevent gate leakage current

in conventional CMOS process. However, after detailed mathematical analysis

performed by A. Giraldo [1] [2] for effective aspect ratio calculations, this layout

technique is being increasingly used to prevent radiation effects in nuclear and space

environment. [3]. Fig. 3(a) shows enclosed gate layout transistor where, the gate is

surrounded from outside by Drain (or Source) and enclosed Source (or Drain).



Figure 3 (a) Enclosed Gate Layout of Transistor (b) Guard Ring in nMOS Transistor

The effective aspect ratio of ELT transistor can well estimate by below formula

[1] [2] [3]:

(1)

Where, c, d, d' = d – c / √2 and α is as shown in Fig. 3(a). Leff is effective gate

length, etching, and diffusion. The parameter α has been take into account for

identifying borderline between transistors T1 and T2 in Fig. 3(a). Typical value of α is

0.05 and has been found to be technology independent. The parameter K that

multiplies the second term in (1) is geometry dependent. For long channel devices (L

greater than 0.5 μm), the K value is 4. When the channel width of transistors is being

shorter (L equal or less than 0.5 μm), the value of K is gradually decreases from 4 to

3.5, since the polysilicon strip starts to hide T2 [3]. The constant polysilicon strip

width denoted by A is independent of the gate length L and is equal to minimum gate

width. The first part of (1) corresponds to the four linear edge transistors (T1), the

second part seven to eight angle corner transistors (T2), the third part to the three liner

corner transistors (T3) [4][5]. From experiments it has been found that threshold

voltage shift for ELT is less than 5mV for 70kGy (SiO2) of total radiation. In

addition, it has been show that threshold voltage variation decreases with increase in

gate length L [4] [5].

2.1.2. Guard Ring

Latch up in CMOS due to parasitic thyristor formation, it can leads to device

destruction. Due to this conducting parasitic thyristor a low resistance path forms

between VDD and VSS, which established a significant high current flow, and leads

to device breakdown. The solution to this problem is that a high resistance path

should exist between two supply voltages, which will decrease the current value.

One way to reduce amount of current is to decrease the gain of parasitic

transistors. This can be done by increasing the distance between the adjacent

MOSFETS. The limitation of this technique is it decreases circuit density. Fig. 3(b)

shows the layout of MOSFET with a guard ring. For efficient prevention of SEL,

nMOS should guarded by a p+ ring and pMOS with n+ ring. Guard rings helps to


Space Application


prevent inter device leakage. It has reported that devices implementing guard rings

show a very high tolerance to SEL (LET > 90 (MeV – cm2) / mg) [5].

2.2. Hardness by Circuit Design

For the study of circuit, behaviour against SEU is recognizing sensitive nodes in the

circuit. SEU sensitive nodes are OFF transistors in the circuit. Here, it has tried to

mitigate Single Event Effects and especially Single Event Upset using techniques like

1) adding transistor redundancy to existing logic, 2) charge sharing between devices.

However, primary focus for preventing SEUs at Circuit Design level has been adding

extra redundant logic to existing logic while using same commercial process

technologies. Some of those techniques are discussing below:

2.2.1. Rockett Memory Cell

Rockett has presented first radiation-hardened latch in 1988 [6]. 6-P channel

transistors surround this standard 6-transistor memory element.

Figure 4 (a) SEU hardened Memory Cell by Rockett (IBM) [6] (b) SEU-Hardened Memory

Cell by Whitaker (NASA) [7]

This design leads to a 16 transistor radiation-hardened latch with input buffer,

widely known as Rockett Memory Cell and shown in Fig. 4(a).

2.2.2. Whitaker Memory Cell

A second solution published first in 1991 [7] and improved in 1992 [8], represents an

original memory cell. The storage bits are located in two different places providing a

redundancy and maintaining a source of uncorrupted data after an SEU. Here,

Whitaker modifies topology of Rockett Memory Cell with use of 12 transistors

instead of 16.Fig. 4(b) shows Whitaker Memory Cell.

2.2.3. Improved Whitaker Memory Cell by Liu

The static power of the Whitaker Memory cell is high. M. Norley Liu [9] improved

over previous cell topology by using of 14 transistors arrangement as shown in Fig.

5(a).



Figure 5 (a) Improved Whitaker Memory Cell by Liu [9] (b) SEU hardened AND/NOR gate

to design an R-S latch [10]

2.2.4. RS Latch based Memory Cell by J.Canaris

J. Canaris proposed a Logic family, which is SEU tolerant. So, using AND-NOR or

OR-NAND gates, a Latch can be designed [10]. This is show in Fig. 5(b).Previously

designed Memory cells had drawbacks number of transistors is more, static power

consumption is high, and recovery time after upset is high. These all drawbacks are

eliminate to an extent/removed and proposed as HIT (Heavy Ion Tolerant) Memory

Cell.

2.2.5. HIT Memory Cell

HIT Memory Cell designed to improve static power consumption and high recovery

time after upset. It designed using 12 transistors [11] (Fig.6 (a)).

HIT Memory cell had no any direct path between VDD to VSS which was a

problem found in previously defined memory cell. Therefore, lower static power

consumption is guarantee in this memory cell compared with previously defined

memory cell.

Figure 6 (a) HIT Memory Cell [11] (b) DICE Storage Cell [12]


Space Application


2.2.6. DICE (Dual Inter clocked Storage Cell)

DICE [12] is composed of two cross-coupled inverter lathes. Feedback to each cell

comes from a previous cell. However, nMOS and pMOS are not connecting to the

same input. Radiation induced upset at node A can recovered from state at node Cin

Fig. 6(b). The limitation of this design is that simultaneous upsets at any two nodes

(e.g. nodes A and C in Fig. 6(b)) cannot recover. A variant to the standard DICE

implementation has proposed in [13] as Dual DICE, which incorporates interleaving

between two DICE cells in order to make them more resistant to SEU, caused by

charge sharing.

2.2.7. Temporal DICE Flip Flop Design

To address problem of two simultaneous strikes induced upsets in DICE, J. E.

Knudsen and L. T. Clark, shown that all four inputs should be made independent to

prevent SET while DICE is transparent as well as a delay mechanism along with a

majority voter should be setup to decrease SEU more effectively [14].

Figure 7(a) Master Temporal Latch and Slave DICE D Flip Flop (TDFF) [14] (b) Quatro

Storage Cell [17]

The temporal latch shown in Fig. 7(a) employs a triple redundant feedback

mechanism, which separates the signal in time. This makes it immune to both SET

and SEU effects [14] [15] [16]. In Fig. 7(a) is showing a temporal latch, which

employs delay blocks marked with δ. This shows that the cell is SET hardened up to

the duration of one δ delay.

2.2.8. Quatro Latch

The Quatro latch is an eight transistors storage cell with the similar basic design

compared to a DICE latch but different interconnection topology [17]. The four

storage nodes in Quatro cell are namely A, B, C, and D (Fig. 7(b)).

Table I shows that over DICE-FF, Quatro-FF is an improvement in area, power,

and maximum clock to Q delay while keeping operational characteristics unchanged.



TABLE I The DICE Storage Cell [17]

Design Area Power Max C-Q delay PDP

D-FF 1 1 1 1

DICE-FF 2.95 1.8 1.4 2.5

Quatro-FF 2.5 1.4 1.6 2.2

2.2.9. Gate Sizing

The radiation environment in space is uniform in space and time, which indicates that

radiation on a chip, is proportional to its active area. When any particle strikes on

sensitive node, it generates a current pulse at that node. For a logic upset, generated

current pulse needs to be of sufficient value. The current is given by equation (2) [18].

I i n(t)=

Q

(τα− τ β)(e

− t

τα− e

− t

τβ )

(2)

Where Q is the charge generated (positive or negative) deposited as result of the

particle strike, τα is the collection time constant of the junction, and τβ is the ion-track

establishment time constant. τα and τβ are constants that depends on process-related

factors. Consider 2 input NAND gate driving a lumped capacitance Cp at its output N

in Fig. The total capacitance at N is [18]

C t o t a l= Cun i t(WL )+ C p

(3)

(a)

(b)

Figure 8 (a) 2-input NAND gate (b) SEU effects (Q, (W/L), (τα, τβ)). [18]


Space Application


So, if (W/L) of the node is increase then Capacitor is charged with more charges.

As the size of any gate increase means driving strength of any gate is increase than

current produce by the particle strike on sensitive node is decrease. So if particle

strike on output node of 2-input NAND gate in Fig. 8(a) than voltage generate by that

particle decreases with increasing W/L ratio of the gate shown in Fig. 8 (b).

The idea of the authors [18] is that increased output capacitance of any gate can

make it is less sensitive to particle hit than a normal gate. This technique was

applicable to only older technology. As in the advance technologies, initial value of

output capacitance is fF. If this technique applied to advance technologies then

increased capacitance values required to satisfy the transient effect become high [19]

[20]

2.2.10. Radiation Hardened Memory Cells

Previously discussed cells have partially SEU immunity and dependent on polarity on

single node or required more power. As CMOS technology scaling down, angled

particle strike becoming more severe [21] [22].In [23], an 11 T SRAM cell has

proposed [also shown in Fig. 9(a)].

Compared with DICE, as claimed by the authors, this circuit (called 11 T) offers

(little) smaller area and considerable lower Power Delay Product (PDP). To have a

better robustness against Single Event Multiple Effects (SEME), the authors of [23],

proposed another SRAM cell in [24] [also shown in Fig. 9(b)]. They showed that, this

latter circuit (called 13 T) can tolerate the effect of Single Event Multiple

Effect(SEME) better than their proposed circuit in [23].As the authors reported in

[24], their circuit has lower delay, higher power consumption and larger area as

compared with DICE.

In [25], new SEU hardening Incorporating an extreme low power bit-cell design

(SHIELD) proposed. The authors of [26] compare proposed design with proposed

design in [12] in terms of technology scaling and effect on it shown in Fig. 9 (c).

Figure 9 (a) Proposed in [23] (b) Proposed in [24] (c) The SHIELD SRAM [25] [26]

In [27][28] novel Radiation Hardened Memory cell which has 12- Transistor and

it is capable of fully SEU immunity and also can tolerant multi bit upset as shown in

Fig. 10(a). This technique is show better result against different radiation hardening

techniques [27].



Figure 10(a) Proposed RHM (Radiation Hardened Memory) cell [28] (b) Proposed 13-T

RHM in [29]

In authors of [29] applied similar approach as applied by [24] and authors [24]

shows low design overhead, higher robustness to radiation effects in present of

SEMEs. Fig. 10(b) shows proposed 13-T RHM in [29].

2.2.11. Device based SEU Clamping Circuit

Equation (2) shows current produced by strike of particles on sensitive node with the

help of equation method proposed by [30]. The idea of this method is used same gate

with higher threshold than normal gate in circuit. Consider the circuit in Fig. 11;

assume that out node is at logic 0.

When energetic particle strike on out node, it causes a rising pulse on out node but

out node, voltage does not increase because protecting gate is at -0.4V.When the

voltage at protecting node outp starts to rise, the nMOS device turns on, thus

clamping the protected node.

If the particle strike on outp than voltage at protected node is unchanged because

protected node initially at much lower voltage (-0.4V) and as the voltage at protecting

node increases, the clamping nMOS device turns off and if voltage of the protecting

node rises above 0.4V than the clamping pMOS device turns on.

Figure 11 Device based SEU Clamping Circuit [30]

In a similar manner, the clamping pMOS device helps to protect a gate from

falling pulse due to a radiation event.


Space Application


3. CONCLUSIONS

Considering the present need of low power, low cost radiation hardened systems;

RHBD will be helpful to resolve the issue. In this regard, this paper has tried to cover

the entire spectrum of various approaches for Radiation Hardening Design level. As

radiation hardening by process is a costly approach, one would prefer to focus on

Radiation Hardening by Design.

REFERENCES

[1] A.Giraldo, A. Paccagnella, A. Minzoni, Aspect ratio calculation in n-channel

MOSFETs with a gate-enclosed layout, Solid-State Electronics, vol. 44, 1st June

2000, pp. 981-989.

[2] A.Giraldo, Evaluation of Deep Submicron Technologies with Radiation Tolerant

Layout for Electronics in LHC Environments, Ph.D. Thesis at the University of

Padova, Italy, December 1998.

[3] Anelli G, Campbell M, Del Mastro M, Faccio F, Giraldo A, Heijne E, Jarron P,

Kloukinas K, Marchioro A, Moreira P, Snoeys W, Radiation tolerant VLSI

circuits in standard deep submicron CMOS technologies for the LHC

experiments: practical design aspects, Nuclear Science, IEEE Transactions on,

vol. 46, issue 6, pp. 1690-1696

[4] Li Chen, Douglas M. Gingrich, Study of N-Channel MOSFETs with an

Enclosed-Gate Layout in a 0.18 m CMOS Technology, Nuclear Science, IEEE

Transactions On, vol. 52, no. 4, Aug 2005.

[5] L. Chen, Radiation tolerant design with 0.18-micron CMOS technology, Ph.D.

dissertation, Dept. Elect. Comput. Eng., Univ. Alberta, Edmonton, AB, Canada,

2004.

[6] L.R. Rockett, An SEU-hardened CMOS data latch design, Nuclear Science, IEEE

Transactions on, Vo1.35, No.6, 1682-1687, December 1988.

[7] J. W. Gambles, K. J. Hass, S. R. Whitaker, Radiation hardness of ultra low power

CMOS VLSI, 11th NASA Symposium on VLSI Design, May 2003.

[8] S. Whitaker, J. Canaris, K. Liu, SEU hardened memory cells for a CCSDS Reed

Solomon encoder, Nuclear Science IEEE Transaction on, Vo1.38. No.6, pp.

1471-1477, December 1991.

[9] M.N. Liu, S. Whitaker, Low power SEU immune CMOS memory circuits,

Nuclear Science, IEEE Transactions on, Vol. 39, no 6, pp. 1679-1684, December

1992.

[10] J.Canaris, An SEU immune logic family, Proceedings of the third NASA

symposium on VLSI design, Moscow, ID, pp. 2.3.1-2.3.12, October 1991.

[11] D. Bessot, R. Velazco, Design OF SEU-Hardened CMOS Memory Cells: The

HIT Cell, Radiation and its Effects on Components and Systems (RADECS),

Second European Conference on 13-16 Sep 1994.

[12] T. Calin, M. Nicolaidis, and R. Velazco, Upset Hardened Memory Design for

Submicron CMOS Technology, Nuclear Science, IEEE Transactions on, Vol 43,

No. 6, December 1996, pp. 2874-2878.

[13] Mahta Haghi, Dr. Jeff Draper, The 90 nm Double-DICE Storage Element to

Reduce Single-Event Upsets, Circuits and Systems, 2009. MWSCAS '09. 52nd

IEEE International Midwest Symposium on 2-5 Aug. 2009.

[14] J. E. Knudsen, L. T. Clark, An area and Power Efficient Radiation Hardened by

Design Flip-Flop, Nuclear Science, IEEE Transactions on, vol. 53, no. 6, Dec

2006.



[15] D.G. Mavis, P.H. Eaton, Soft error rate mitigation techniques for modern

microcircuits, Reliability Physics Symposium Proceedings, 40th Annual, 7-11

April 2002, pp. 216-225.

[16] D.G. Mavis, P.H. Eaton, Temporally redundant Latch for Preventing Single

Event Disruptions in Sequential Integrated Circuits, U. S. Patent 6 127 864, 2000.

[17] S. Jagannathan, T. D. Loveless, B. L. Bhuva, S.-J. Wen, R. Wong, M. Sachdev,

D. Rennie, and L. W. Massengill, Single-Event Tolerant Flip-Flop Design in 40-

nm Bulk CMOS Technology, Nuclear Science, IEEE Transactions on, vol. 58,

no. 6, Dec. 2011.

[18] Quming Zhou, KartikMohanram, Gate Sizing to Radiation Harden Combinational

Logic, Computer-aided Design of Integrated Circuit ad Systems, IEEE

Transactions on, vol. 25, no. 1, January 2006.

[19] Kastensmidt, F.L.; Assis, T.; Ribeiro, I.; Wirth, G.; Brusamarello, L.; Reis, R.;

Transistor sizing and folding techniques for radiation hardening, Radiation and

Its Effects on Components and Systems (RADECS), 2009 European Conference

on , vol., no., pp.512-519, 14-18 Sept. 2009

[20] Mavis, D.G.; Eaton, P.H.; Sibley, M.D, SEE characterization and mitigation in

ultra-deep submicron technologies, IC Design and Technology, 2009. ICICDT

‘09. IEEE International Conference on , vol., no., pp.105-112, 18-20 May 2009

[21] D. R. Blum and J. G. Delgado-Frias, Hardened by design techniques for

implementing multiple-bit upset tolerant static memories, in Proc. ISCAS, 2007,

pp. 2786–2789.

[22] J. D. Black, P. E. Dodd, and K. M. Warren, Physics of multiple node charge

collection and impacts on single-event characterization and soft error rate

prediction, Nuclear Science, IEEE Transactions on, vol. 60, no. 3, pp. 1836–

1850, Jun. 2013.

[23] S. Lin, Y. B. Kim, and F. Lombardi, A 11-transistor nanoscale CMOS memory

cell for hardening to soft errors, Very Large Scale Integrity. System, IEEE Trans

on, vol. 19, no. 5, pp. 900–904, May. 2011.

[24] S. Lin, Y. B. Kim, and F. Lombardi, Analysis and design of nanoscale CMOS

storage elements for single-event hardening with multiple-node upset, Device

Mater. Rel., IEEE Trans. on, vol. 12, no. 1, pp. 68–77, Mar. 2012

[25] Pescovsky, O. Chertkow, L. Atias, and A. Fish, SEU hardening: Incorporating an

extreme low power bit-cell design (SHIELD), in Proc. IEEE S3S ’14, 2014, pp.

1–2.

[26] Lior Atias, Adam Teman, and Alexander Fish, Single Event Upset Mitigation in

Low Power SRAM Design, IEEE 28-th Convention of Electrical and Electronics

Engineers in Israel, 2014

[27] Jing Guo, Liyi Xiao, Zhigang Mao, Novel Low-Power and Highly Reliable

Radiation Hardened Memory Cell for 65 nm CMOS Technology, Circuits and

Systems-I IEEE Trans. on , Vol. 61, No. 7, July 2014

[28] Jing Guo, Liyi Xiao, Tianqi Wang, Shanshan Liu, Xu Wang, Zhigang Mao, Soft

Error Hardened Memory Design for Nanoscale Complementary Metal Oxide

Semiconductor Technology, Reliability IEEE Trans. on, Vol. 64, No. 2, June

2015

[29] Ramin Rajaei, Bahar Asgari, Mahmoud Tabandeh, and Mahdi Fazeli, Design of

Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer

Technologies, Device and Materials Reliability IEEE Trans. On, Vol. 15, No. 3,

September 2015

[30] Rajesh Garg, Nikhil Jayakumar, A Design Approach for Radiation-hard Digital

Electronics, Design Automation Conference, 43rd ACM/IEEE, 2006.

A SURVEY OF RADIATION HARDENING BY DESIGN (RHBD ... · Key words: Displacement Damage (DD),...

Documents

Transcript of A SURVEY OF RADIATION HARDENING BY DESIGN (RHBD ... · Key words: Displacement Damage (DD),...