IJITMISR, Vol. 4, No. 1, June 2015, pp. 53-57

A Purely Mux Based High Speed Barrel Shifter DesignAbhijit Asati1 and Chandrashekhar2

1EEE Group, BITS, Pilani, India-333031, E-mail: abhijitmicro@gmail.com2CEERI, Pilani, India-333031, E-mail: chandra @ceeri.ernet.in

ABSTRACT: Barrel shifters are often used in many key computer operations from address decoding to computer arithmetic.Barrel shifters are primarily used for performing data shifting and rotation operations. Different barrel shifter architecturesshow trade offs in terms of area power and delay. In this paper we present the design and the VLSI implementation of anovel ‘purely MUX based’ barrel shifter architecture in 0.6mm, N-well CMOS process using a optimized static CMOS logicdesign style. The proposed barrel shifter implementation shows almost 50% reduction in the propagation delay, while keepingthe almost similar average power consumption (at 10MHz) as compared to the implementation by Ramin Rafati [9]. Thetotal transistor count, maximum instantaneous power, leakage power, core area, total routing length and number of viashighlights the VLSI implementation characteristics.

Keywords: Barrel shifter, data shifting/rotation, left/right, DSP, computer arithmetic, static logic style, high speed, VLSIimplementation, MUX-based

1. INTRODUCTIONThe barrel shifter is an important data path elementused for digital signal processing applications. It is usedfor floating-point normalization, word pack/unpack,field- extraction from a bit stream, editing, datamodification and arithmetic manipulation. A barrelshifter is a combinational circuit that shifts or rotatesthe input data word by a desired number of positionsleft or right as specified by a control word [1], [2], [3].Different barrel shifter architectures show tradeoffsbetween speed of operations, average powerconsumption and silicon area [3], [4]. The rightwardoperations can be implemented as leftward operationsin order to achieve significant reduction in area andpower required by the barrel shifter circuit as describedin [1], [2]. These architectures are bit slower since allthe logic elements in the critical path are assigned tothe different partitions hence increases the length ofcritical path.

In this paper we present a novel ‘purely MUXbased’ barrel shifter architecture. The proposedarchitecture have the dedicated hardware for all theoperations to be performed by the barrel shifter, henceit is faster, but consume larger silicon area and power.This architecture is highly regular, hierarchical,modular and consistence. The 16-bit barrel shifterdesign has six external control signals out of whichfirst four bits represent the length of the operation,

while fifth and sixth bits represent ‘type’ and ‘direction’of operation respectively. Length bits S [3: 0], whichallow shifting or rotation of data from 0 to 15 positions.S/R bit decides shifting or rotation (S/R=0 meansshifting and S/R = 1 means rotation) and D bit decidesdirection of shift/rotation (D = 0 means leftward andD = 1 means rightward direction). Section 2 explainsthe design of 4-bit MUX-based barrel shifter, Section3 describes design of 16-bit MUX-based barrel shifter.Physical implementation and results are described insection 4 while section 5 concludes the paper.

2. DESIGN OF 4-BIT MUX-BASED BARRELSHIFTER

The MUX based Barrel shifter architecture (for sizesup to 16-bit) has been designed using 4:1, 8:1, 16:1,32:1 and 64:1 multiplexers. The design follows ahierarchy, which can be described as follows. The 2:1MUX is first designed using CMOS logic. It is thenused to design the 4:1 MUX. The 8:1 MUX is designedusing the 4:1 MUXs as the basic building block. Similarhierarchy is followed in the design of 16:1, 32:1 and64:1 MUXs. A 2n:1 MUX will have 2n input lines, nselect lines and one-output line. MUXs with any n,greater than one can be implemented using 2:1 MUX.One 2n:1 MUX requires (2n-1) number of 2:1 MUXsand has a delay of ‘n’ 2:1 MUX. In this architecturen=1, 2, 3, 4, 5, 6 are used in the design 2:1, 4:1, 8:1,16:1, 32:1 and 64:1 multiplexers.

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The table I show the behavior of 4-bit MUX-basedbarrel shifter, which utilizes control inputs D fordirection, S/R for operation (shift/rotate) and S

1, S

0 for

number of bits to be shifted or rotated. Y0, Y

1, Y

2, Y

3

represent the output bits and I0, I

1, I

2, I

3 are input bits.

D=‘0’ means the direction of shift/rotate operation istowards left and D=‘1’ means the direction of shift/rotate operation is towards right. ‘F’ represents the fillbit, where, the fill bit is ‘0’ for left shift and the fill bitis MSB bit for right shift operation. The line S/R=‘1’for Rotate operation and S/R= ‘0’ for Shift operation.Bits S

1 and S

0 are length selection bits. S

1S

0=‘00’ means

length is zero bit, S1S

0= ‘01’ means length is one bit,

S1S

0= ‘10’ means length is two bits and S

1S

0= ‘11’

means length is three bits. Table I explains the variousoperations performed by 4-bit barrel shifter. As thereare four control inputs, we need a 16:1 multiplexer foreach output bit. Thus for 4 output bits, we need four16:1 MUXs in the design of a 4-bit barrel shifter. Inaddition we need a 2:1 MUX for fill bit as shown infigure 1. Thus the total number of 2:1 MUXs requiredin the design are 61.

Each row of the truth table I can be implementedwith a dedicated 16:1 multiplexer circuit, which isdesigned using 2:1 MUX cells, to obtain the finaloutput.

Figure 1: A Schematic Diagram of 4-bit, MUX based BarrelShifter

Table ITruth Table for 4-bit Barrel Shifter Operation

Operation D S/R S1

S0

Y3

Y2

Y1

Y0

Arithmetic Shift Left 0 0 0 0 I3

I2

I1

I0

0 0 0 1 I2

I1

I0

F

0 0 1 0 I1

I0

F F

0 0 1 1 I0

F F F

Rotate left 0 1 0 0 I3

I2

I1

I0

0 1 0 1 I2

I1

I0

I3

0 1 1 0 I1

I0

I3

I2

0 1 1 1 I0

I3

I2

I1

Arithmetic Shift right 1 0 0 0 I3

I2

I1

I0

1 0 0 1 F I3

I2

I1

1 0 1 0 F F I3

I2

1 0 1 1 F F F I3

Rotate right 1 1 0 0 I3

I2

I1

I0

1 1 0 1 I0

I3

I2

I1

1 1 1 0 I1

I0

I3

I2

1 1 1 1 I2

I1

I0

I3

2.1. Fill Bit LogicFill bits are required only in the case of shiftoperations. In left shift operation, the lower significantbits are filled with 0’s. While in the right shiftoperation, in order to preserve the sign of the inputnumber, MSB is sign extended. This is accomplishedusing a 2:1 MUX. The D=‘0’ represent the leftoperation for which fill bit is ‘0’ and D=‘1’ means theright operation for which fill bit is MSB bit of input.The Fill bit is utilized for shift operations, while it isdiscarded for rotate operations. Figure 1 shows theschematic of a 4-bit MUX-based barrel shifter, whichalso includes fill bit logic.

A Purely Mux Based High Speed Barrel Shifter Design � 55

3. DESIGN OF 16-BIT MUX-BASED BARRELSHIFTERSimilar technique is followed in design of 16-bit

barrel shifter circuit design. As there are six controlinputs, we need a 64:1 multiplexer for each output bit.Thus for 16 output bits, we need 16, 64:1 MUX in thedesign of a 16-bit barrel shifter, in addition we need a2:1 MUX for fill bit. Thus total 2:1 MUX required indesign are 1009 (transistor count is 1009´12=12108).Since each row of a truth table is implemented using adedicated 64:1 multiplexer circuit, therefore delay ofsix, 2:1 MUX cell will be required for it; one additional

delay will be required for fill bit therefore total seven,2:1 MUX cell delay will be required to produce finaloutput for 16-bit barrel shifter. The schematic of 16-bit barrel shifter circuit is shown in figure 2(a). Thecritical delay of the circuit is 7 times the delay of a 2:1MUX cell, without considering the interconnect delay.The proposed architecture offers the importantproperties like regularity, hierarchy, modularity andconsistency. These properties help in reducing thedegradation in circuit performance due to interconnectdelay occurring in the sub-micron/ deep sub-microntechnologies.

Figure 2: (a) Schematic Diagram of a 16-bit, MUX based Barrel Shifter (b) Layout of a 16-bit, MUX based Barrel Shifter

4. PHYSICAL IMPLEMENTATION ANDRESULT

Layout assembly corresponding to a 16-bit barrelshifter schematic circuit is shown in figure 2 (b). Thelayout is implemented in 0.6µm, N-well CMOS process(SCN_SUBM, lambda = 0.3) of MOSIS, usingconventional static CMOS logic design style.

A schematic library consisting of a singlefunctional cell (i.e 2:1 MUX) is defined for static logic

design style. Figure 3 shows the 2:1 MUX cellschematic in conventional static CMOS logic.

Corresponding to the schematic library, threedifferent physical libraries were designed usingconventional static CMOS logic using the designprinciples of [5], [6], [7], [8]. Three different versionsof each physical library were developed byrespectively sizing the W/L ratios of the NMOStransistor to values of 3, 5 and 7 (W/L values smaller

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than 3 were also experimented with but not consideredfurther as they resulted in parasitic dominated slowerspeeds due to weak drives of transistors and were notconsidered good candidates for high performance).The layout assemblies for the 16-bit barrel shifterwere carried out using these cell libraries andautomatic place and route tool LEDIT (SPR) fromM/s Tanner Research Inc. The product of averageswitching energy and circuit delay was then computedfor each implementation of the barrel shifter usingthe static logic design style but utilizing three differentphysical libraries differing in their transistor sizes asdescribed above. It was noticed that for all the threelogic design styles, the physical library utilizing W/L ratio of 3 for NMOS transistor gave the smallestaverage switching energy-delay product. Thegenerated layouts were simulated after parasiticextraction using circuit simulator, ELDO spice.Supply voltage V

DD was kept at 3.3 V. Different design

parameters like propagation delay, transistor count,core area and power dissipation at 10 MHz data rateis compared. It was observed that layout with NMOStransistor sizing of 3 [shown in figure 2(b)] gave bestresults, which are then compared with other highspeed 16-bit barrel shifter implementation designedusing domino and D3L logic by Ramin Rafati [9] asshown in table II.

Comparing these two-barrel shifter architecturesshows that proposed barrel shifter architecture showssignificant reduction in delay and almost comparableaverage power consumption. The improvement in delayis obtained due to shorter critical path gate delay andkey architectural properties like regularity, hierarchy,modularity and consistency. These properties improvethe wiring delays on critical path. The maximum

instantaneous power, leakage power, core area, totalrouting length and number of vias are shown in tableIII for highlighting the VLSI implementationcharacteristics.

Table IIComparison of Barrel Shifter Architectures

Algorithm(technology) VDD

(V) Propagation Averagedelay (�) ns power (mW)

Proposed (static)(0.6mm) 3.3 1.163 3.59

Ref [9] D3L(0..6 mm) 5 2.25 2.66

Ref [9] Domino(0.6 mm) 5 2.68 3.23

Table IIIOther Implementation Details

Algorithm Maximum Leakage Core Total Number(technology) Power Power area routing of Via

(mW) (nW) (mm2) length (mm)

Proposed 65.87 65.75 28.34 1901.42 4316(0.6µm)

5. CONCLUSIONSThe paper presents design and VLSI implementationof a 16-bit MUX based barrel shifter circuit usingconventional static CMOS logic and 0.6mm, N-wellCMOS process. The proposed barrel shifterimplementation shows almost 50% reduction inpropagation delay, while maintain the similar averagepower consumption, as compared to theimplementation by Ramin Rafati [9]. The proposedarchitecture has shorter gate delay critical path besidesoffering important architectural properties likeregularity, hierarchy, modularity and consistency.

REFERENCES[1] G. M. Tharkan, “A New Design of a Fast Barrel Switch

Network,” IEEE Journal of Solid State Circuits, 27(2), 217-221, 1992.

[2] R. Pereira, “Fully Pipelined TSPC Barrel Shifter for HighSpeed Applications,” IEEE Journal of Solid State Circuits,30(6), 686-690, 1995.

[3] Ken Martin, “Digital Integrated Circuit Design,” Indian Edtion,Oxford University Press, 2007.

[4] K. Acken, M. Irwin and R. Owens, “Power Comparisons forBarrel Shifters,” ISPLED, Monterey CA USA, 1996.

[5] Mohab Anis, Mohamed Allam and Mohamed Elmasry, “Impactof Technology Scaling on CMOS Logic Styles,” IEEETransaction on Circuits and Systems-II, Analog and DigitalSignal Processing, 49(8), 577-587, 2002.

[6] S. M. kang, Yusuf Leblebici, “CMOS Digital IntegratedCircuits, Analysis and Design,” Third edition McGrawhill,2003.

Figure 3: A Schematic of 2:1 MUX Cell using ConventionalStatic CMOS Logic

A Purely Mux Based High Speed Barrel Shifter Design � 57

[7] N. Weste and K. Eshraghian, “Principles of CMOS VLSIDesign,” Addison-Wesley, 1994.

[8] Jan M. Rabaey, Anantha Chandrakasan, Borivose Nikolic,“Digital Integrated Circuits,” Second Edition Prentice–Hall ofIndia Private Limited, 2004.

[9] Ramin Rafati, Sied Mehdi Fakhraie, “A 16-bit Barrel ShifterImplemented in Data Driven Dynamic Logic (D3L)” IEEETransaction on Circuits and Systems-I, 53(10), 2194-2202,2006.