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8-Bit Barrel Shifter

Cyrus Thomas

Ekemini Essien

Kuang-Wai (Kenneth) Tseng

Advisor: Dr. David Parent

December 8, 2004

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Agenda• Abstract• Introduction

– Why– Simple Theory– Back Ground information (Lit Review)

• Summary of Results• Project (Experimental) Details• Results• Cost Analysis• Conclusions

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Abstract• Designed and Verified an 8-bit Barrel Shifter that operates at 200

MHz, uses 15.39 mW of Power, occupies an area of 340 x 300 m2

and has a power density of 15.1 W/cm2.

• The shifter works by shifting the bits left.

• Inputs: Data bits D0-D7 & encoded Select lines S2, S1, S0.

• Outputs: Shifted Data bits Q0 – Q7.

• Implementation Technology : 0.6 micron process.

• Latency = 5n s.

• External load driving capability = 33f F.

• Number of Metal layers used = 3.

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Introduction• Because there were 5 stages (combining each flip flop

stage as one stage), the propagation delay time was divided

amongst all 5 stages with each stage having a different

driving capacitance.

• Since each output of multiplexer in stage 2 and 3 was

connected to 2 other multiplexers, the fan out was 2.

• Since the connection from the multiplexers have long

wires through out the circuit, parasitic capacitances were

considered for sizing.

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8 Bit Barrel Shifter Logic DiagramStage 1 Stage 2 Stage 3 Stage 4 Stage 5

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Project Summary

• We designed a 8 bit Barrel Shifter that shifts data from an input to an output depending on the combination of three select lines.

• Our design of the Barrel shifter allows for an increase in the number of input bits without having to modify the existing design.

• Our design met the specifications for the project.

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Longest Path Calculations

5.714

7PHL

nsns Note: All widths are in microns

and capacitances in fF

Logic Cg to WN WP WN WP WN WPLevel Drive (H.C) (H.C) (S) (S) (L) (L)1 Mux-DFF

Nand17.1 1 2 1 2 1.96 1.63 1.96 1.6 1.96 1.6 5.99

1a Mux-DFF Master

5.99 2 2 2 2 3.96 6.8 3.96 6.8 3.96 6.8 18.3

2 Inveter 20 1 1 1 1 1.5 2.7 1.95 3 1.95 3 8.43

2a Mux (AOI22) 8.43 6 6 2 2 4.31 7.49 2.85 4.7 2.85 4.7 20.1

3 Inveter 40 1 1 1 1 2.86 5.14 3 6 3 6 13.6

3a MUX (AOI22) 13.6 6 6 2 2 3.46 5.99 2.25 3.9 2.25 3.9 16.1

4 Inveter 32 1 1 1 1 2.32 4.17 3 6 3 6 11.1

4a MUX (AOI22) 11.1 6 6 2 2 3.45 6.15 3.45 6.2 3.45 6.2 16.4

5 Mux-DFF Nand

33 1 2 1 2 5.64 4.85 5.64 4.9 5.64 4.9 17.8

5a Mux-DFF Slave

17.8 4 4 2 2 3.7 6.36 3.7 6.4 3.7 17 17.1

Superbuffer 17.8 4 4 2 2 3.7 6.36 3.7 6.4 3.7 6.4 12

inverter 1 240 1 1 1 1 26.7 49.2 26.7 49 26.7 49

#NSP Cg of gate

Gate #N #M #NSN

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Schematic

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Layout

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Verification

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Simulations

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Cost Analysis• We had to invest our time and resources to complete this

project. By our estimation, considering that we also had to study for other classes, we spent – 12 hours worth of time in a week and a half looking for and

deciding on a project with Dr. Parent’s consent. – 8 hours worth of time in a week verifying our logic and

making our schematic. – 6 hours worth of time in a day verifying our timing.– 36 hours worth of time in two and half weeks making the

layout of our project.– 8 hours of time in a week in determining our post

extraction time.

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Lessons Learned

• Doing the project helps in better understanding the course material.

• Start the project on time as the earlier you start, the better.

• Consult with the course instructor (Dr. Parent in this case) and your peers whenever you get stuck on the project as no one can know it all.

• And most importantly view the project as an opportunity to have fun while learning. It will make it a worthwhile experience.

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Summary

• Our project was a worthwhile endeavor as not many people know what a barrel shifter is and what it is used for. As such, doing it and presenting it to the class has helped to enlighten our classmates.

• Most importantly we got our circuit design to work and meet specification as we have ably shown in our presentation.

• We believe that our circuit can become a stepping stone to improving computer organization and memory.

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Acknowledgements

• Thanks to each member of the group for putting up with one another.

• Thanks to Cadence Design Systems for the VLSI lab

• Thanks to Synopsys for Software donation• Thanks to Professor Parent for his assistance and

advising with the project.• Thanks to you all for listening.