A POWER EFFICIENT DIGITALLY PROGRAMMABLE DELAY ELEMENT FORLOW POWER VLSI APPLICATIONS

Anusha Chithradevi Jeyanthi Parkavi

OBJECTIVE

Digitally programmable delay elements (DPDE) are required to be monotonic and low power.

In this project, a low power digitally programmable delay element (DPDE) with monotonic delay characteristics is proposed.

The static power is eliminated while dynamic power is made proportional to the delay to enable

current on demand operation

DESIGN & ANALYSIS

It is a Quality Electronic Design. Digitally Controled Delay elements. Digitally Programmable Delay Element. * Shunt-capacitor based DPDE

* Variable Resistor based DPDE

* CSI based DPDE. Dynamic current mirror.

DCDE ARCHITECTURE

DIGITALLY CONTROLLED DELAY ELEMENT

A monotonic digitally controlled delay element (DCDE) is implemented in the 0.18 μm CMOS technology. The delay of the DCDE changes monotonically with respect to the digital input vector. The monotonicity is one of the important features of this new architecture. Due to its monotonic behavior, the design of the DCDE is rather straightforward. The DCDE can be analyzed by a simple set of empirical equations with reasonable accuracy and can be made more tolerant to process, temperature, and supply voltage variations. The implemented delay element provides a delay resolution of as low as 2 ps and consumes 170 μW to 340 μW static power depending on the digital input vector.

DIGITALLY PROGRAMMABLE DELAY ELEMENT

Digitally programmable delay elements (DPDE) are required to be monotonic and low power. A method of delaying a signal along a line using a programmable delay device, the delay device comprising: a plurality of delay elements, each delay element having an input and output terminal, each delay element providing a fixed and separate amount of delay; a first, second and third set of transmission gates, each transmission gate having a controlled current path and a control terminal, the inputs of the first set of transmission gates are coupled together, the outputs of the first set of transmission gates are separately coupled to the input of a delay element, the output of a delay element is coupled to the input of a separate second set transmission gate, the outputs of the second set of transmission gates are connected together, the inputs of the third set of transmission gates are separately coupled to the output of a separate delay element, the outputs of the third set of transmission gates are coupled separately to the input of a separate delay element; the method comprising: enabling two or more transmission gates to form a connected path from the input terminal to the output terminal, thereby choosing a single delay element or a series of delay elements.

SHUNT-CAPACITOR BASED DPDE.

SHUNT-CAPACITOR BASED DPDE

A shunt capacitor based DPDE that was proposed is in the figure. A digital input code controls the output capacitive load seen by the input inverter. The MOS with source and drain shorted can be used for the capacitors. The technique is quite robust but the use of capacitors is prohibitive in terms of area.

VARIABLE RESISTOR BASED DPDE

VARIABLE RESISTOR BASED DPDE

The proposed Variable Resistor Based DPDE technique is shown in the figure above. An input code switches a bank of stacked transistors thereby producing varying resistance at the source. Different resistance values produce different discharging currents and hence different delays. Extra coding is however required for the transistor switching.

CSI BASED DPDE

CSI BASED DPDE

It is a current starved – Inverter based DPDE. A CSI based DPDE using current mirror (CM) was proposed that provides monotonic delay and is less sensitive to temperature variation. Due to charge sharing between the capacitance at the output of the input inverter and the capacitance at the source , the delay may not be monotonic. A one to one mapping of input vector to delay is therefore not guaranteed. This problem was identified and analyzed and a different technique based on a current mirror, was proposed to solve the problem

DYNAMIC CURRENT MIRROR Well, for normal topology CM , it's can used for low

output resistance (not main issue in the design) because it has excellent output dynamic range.

The Vds drop on o/p transistor can be as low as (vgs-vt) .if u keep this vgs-vt minimum than vds req to keep the transistor becomes low, therefore your dynamic range of the ckt that is connected to this mirror increases because the voltage consumed by mirror becomes low

Well the current remains constant over a certain voltage range and hence the dynamic range of current mirror is more....

The accuracy of dynamic current mirrors is independent of the mismatch of the transistors comparing the mirror, because of the same transistor is sequentially used at the input and the output of the mirror. Limitation of such dynamic current mirrors and the influence of clock phase delays are shown through simulation.

ADVANTAGES

CONCLUSION

A digitally programmable delay element with very low power consumption has been presented. By using a switched current mirror and feedback, the static current is eliminated while the dynamic power is made proportional to the delay allowing the element to operate at 450MHz with a maximum of 36uW power consumption. The delay element is an attractive candidate for DCOs, DDLL, ADPLLs and clock multipliers.

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