A New Wafer Level Latent Defect Screening...

Paper 30.2 INTERNATIONAL TEST CONFERENCE 1 1-4244-4203-0/08/$20.00 ©2008 IEEE

A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method

Junghyun Nam*, Sunghoon Chun*, Gibum Koo**, Yanggi Kim**, Byungsoo Moon**, Jonghyoung Lim***,

Jaehoon Joo***, Sangseok Kang***, Hoonjung Kim**, Kyeongseon Shin**, Kisang Kang**, Sungho Kang*

*: Yonsei University, Computer System & Reliable Soc Lab, Seoul, Korea **: Samsung Semiconductor Memory Division, Packaging & Test Technologies, Wafer Test Technology Team, Korea

***: Samsung Semiconductor Memory Division, Product Engineering Team, Korea

Abstract

Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposed methodology consists of a defect-based wafer burn-in (DB-WBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.

1. Introduction

Recently, advances in emerging IC packaging technology have enabled novel packages like CSP (chip scale package), MCP (multi-chip package), and WSP (wafer-level processed stack package). High capacity memory MCPs are used for 3G mobile phones or smart multimedia camera phones, requiring various types of memory for code execution and data storage. Many packaging technology studies have evaluated the feasibility of 3D stacking technology for high density, multi-function convergence [1]. In particular, wafer thinning and through silicon via (TSV) technology are emerging as new packaging technologies for 3D integration packages [2–4]. Dies can be stacked on top of each other with TSV or wiring technology. Although multichip convergence packaging technology has advanced, manufacturing still suffers from low yield and reliability. One of the problems is the requirement for KGD quality level for economical manufacturing. KGD refers to die availability at the same quality and reliability as an equivalent packaged single chip. KGD has been applied to

MCM (multi-chip module) production used in the aerospace industry and super computers from the mid-1980’s through the 1990’s [5]. Multi-chip packages require high reliability equivalent to the KGD quality level because of yield loss probability due to latent defects. The presence of a bad bare chip in the multichip package will cause the other chips to be discarded.

In previous approaches, sacrificial metal (SM) WLBI (wafer level burn-in), presented by Motorola and comprising WLBI circuitry linked together with a metal interconnect layer into clusters sharing common power and driver signals from an individual die in a wafer, has been used [6]. The full contact WLBI system method, by using a full wafer direct contact method, takes advantage of massive parallelism [7–9]. This method needs to implement a full wafer contactor that interfaces every pin independently to the burn-in system. In general, in the wafer-probing test, the probe card technology used for interfacing with pads in devices has many critical characteristics such as fine pitch, planarity variation, contact force, and thermal stability. Recently, most DRAMs have a fine pitch pad of less than 80 um. For example, in the case of containing square chips with 80 pads, there are approximately 1,000 chips and 80,000 pads in a twelve-inch diameter wafer. In this case, the total force is 400 kg when the contact force is 5 g per pin. In addition, the horizontal planarity of the contactor requires high resolution of less than the overall pin planarity of 10 µm.

In [10], a wafer burn-in method is presented by Toshiba. This method uses the embedded wafer burn-in stress circuitry in a device to overcome the drawbacks of conventional package burn-in. In addition, the WBI method was applied to characterize the reliability of the new memory product and new fabrication process development [11, 12].

In general, wafer test process has two key roles: (1) it provides detailed analysis information for estimating fabrication yield and design optimization and (2) it provides pre-screen information for assembly cost saving and yield-up. Especially, among the wafer test processes, a wafer burn-in test is important process for increasing the manufacturing test yield and reliability. This is the reason why semiconductor industries have developed several wafer level burn-in methods to achieve high reliability components like KGD at the wafer level. However, previous WBI methods still have many drawbacks related to defect screen types, uncontrollability for

Paper 30.2 INTERNATIONAL TEST CONFERENCE 2

diverse defects such as micro-bridge defects due to deep sub-micron processes, and over-current flow problems due to multi word-line operation during the wafer burn-in operation at the high temperature.

In this paper, we propose a novel statistical DB-WBI (defect based wafer burn-in) stress method. The proposed method includes controllable stress factors and flexibility to screen several latent defects occurring under sub-100 nm scales. The proposed screen method consists of two main parts: (1) a new latent defect based wafer burn-in stress method and (2) a statistical defect screen optimization method that uses RSM (response surface method), which is a collection of statistical techniques used to model and analyze problems in which a response is influenced by several variables.

This paper is organized as follows. In Section 2, we describe a new DB-WBI stress method to screen latent defects in the wafer probing test. In Section 3, a statistical latent defect screen optimization method using RSM (Response Surface Method) is presented. Then, in Section 4, experimental results showing the efficiency of the proposed method through practical production reliability evaluation are shown. Finally, conclusions are presented in Section 5.

Term Acronym CSP Chip scale package MCP Multi-chip package WSP Wafer-level processed stack package TSV Through silicon via KGD Known good die

DRAM Dynamic random access memory RSM Response surface method MCM Multi-chip module ILT Infant life test WBI Wafer burn-in (it is embedded wafer burn-in

circuits) WLBI Wafer level burn-in ATE Automatic test equipment

DB-WBI Defect based wafer burn-in DOE Design of experiments PRT Production reliability test

2. Wafer Level Latent Defect Screen Methodology

Nowadays, DRAM memory devices have an embedded accelerated operation mode to allow the application of more accelerated conditions than user conditions for high reliability. If latent defects are pre-screened and repaired at the wafer-probing step, the final package test and burn-in time can be drastically reduced or even eliminated. The proposed methodology consists of a DB-WBI (defect based wafer burn-in) stress method and a statistical defect screen method that uses RSM (response surface method). In this section, we

describe design considerations and key characteristics of the DB-WBI stress method. Then, in the next section, we present a statistical defect screening method that uses RSM in conjunction with the DB-WBI stress method.

2.1 Defect-Based Wafer Burn-In Stress Method

Fig. 1 shows a basic DRAM cell structure, which is consists of a transistor controlled by a word-line (WL), which connects a bit-line (BL) with a cell capacitor. For read and write operations, both bit line pairs connect directly with the sense amplifier (S/A). The S/A can detect small signal differences between bit-lines during normal read operation.

Figure 1. Basic DRAM circuit for write/read operation

Considering the latent defects can be generating from DRAM operation of Fig. 1, we can extracted the latent defect modeling cases in shown Fig. 2, which consist of expected defects related to the cell such as bit-line contact short, resistive BC not open, gate to drain short, gate to source short, s-poly resistive open, and bridge defects between adjacent cells including BL to BL soft bridge, WL to BL soft bridge, and WL to WL soft bridge.

Figure 2. Latent defect models and DB-WBI stress factors

(W/L: VPP, Bulk Bias: VBB, Bit Line: VBL, Cap Plate: VP, Power: VDD) Fig. 3 shows an example of the latent defects defined by an

infant life test (ILT) failure analysis. Partial resistive via not open defects in DC (direct contact) or BC (bit-line contact) can be screened with direct electrical bias for shortened times.


(a) B/L thinning failures

(b) Via not open failures

Figure 3. An example of latent defect types Certainly, these defect types can be screened during the

conventional burn-in operation. However, as subtle defect types increase due to the scaling down of process, it is difficult to screen diversified defects. Hence, we focused on flexible stress factors based on the defect types at wafer test process. Simultaneously, we considered the electrical stress of the voltage potential difference between physical nodes influenced by DRAM read/write pattern operation. To accelerate latent defects shown in Fig. 3, conventional package burn-in can apply several patterns such as March-X,

March-Y and dynamic disturbing patterns for dynamic burn-in test. Similarly, to efficiently screen weak cells in terms of geographical defect view, we designed some stress patterns such as even-odd word-line activated stress pattern of row-stripe type, and true-complement word-line activated stress patterns of column-stripe type, and all word-line activated read stress pattern covering diverse cell to cell defect types. The proposed DB-WBI consists of run-time controllable stress factors and the embedded read/write stress pattern parts controlled by ATE signals.

Fig. 4 shows overall structure of proposed DB-WBI stress method, which consists of DC stress factors controlled externally from WBI mode enable signal of ATE, and the merged word-line control, and the merged bit-line. In terms of the merged structure, this method can consequently make 1 Gb DRAM to 8 bit DRAM of the 4 x 2 matrix structure as a merged word-line and bit-line scheme considering the cell data topology. The DB-WBI structure of Fig. 4 has the ability to maintain a constant burn-in time even as device density is increased. However, because of merged WL and BL, consuming currents for the multi-cell operation are increased. Therefore, the merged structure of the DB-WBI has to handle this power consumption problem for good operation. Generally, as shown in Fig. 4, the operation of DRAM read/write executes an operation of a cell selected by BL and WL with the S/A. However, for economic DB-WBI write/read operations, we have firstly solved the operational noise problem of multi-WL activation mode up to 1K WLs. To significantly improve signal disturbance occurred by merging word-line and bit-line structures, we enhanced the driving capability of the sense amplifier to sense the charge of the

Figure 4. Proposed DB-WBI stress method (for example, 4x2 matrix structure by merged word line, bit line)


multi-cells in the same BL pairs. Also, we have adopted externally controllable VBB as a bulk bias control factor for noise suppression of multi-WL operation.

In the next subsection, we explain operation flow of the DB-WBI stress mode and power considerations in multi-cell operation.

2.2 Main Considerations for the DB-WBI Stress Method

Since the DB-WBI stress method uses a merged word-line and bit-line structure and applies more excessive patterns into devices, the circuitry for the DB-WBI stress have to be carefully designed with the following considerations.

First, when the DB-WBI circuitry is designed, it should eliminate the floating node as an abnormal leakage path. Specifically, in the case of DB-WBI stress mode entry or unintended transistor switching, we prevent the abnormal current path due to transistor on/off. In many DB-WBI operating cases, floating nodes may result in positive current feedback leading to current runaway. Excessive current causes melting of the probe card needle.

Second, the expected peak power consumption during write and read operation must be predicted. In general, during the read operation of the normal DRAM, current driving capability of the S/A to read the voltage difference of only a cell exists between a pair of bit lines. However, under full sensing operation of the merged BL and BL bar pairs during DB-WBI read pattern operation, the peak power consumption is very high because peak power is consumed when all cells of the WLs and BLs are enabled for DB-WBI read stress operation through the sense-amplifier. For stability of the DB-WBI read operation, the current supply power structure design of the sense-amplifier used for DB-WBI operation should be carefully implemented using a sufficiently powerful power source.

Third, the current capability of the pin driver is considered, which is included in the PE (pin electronics) for the ATE (automatic test equipment). In general, the pin driving capability of the PE for a general memory tester is sufficient with 20-30 mA per pin driver. However, the current capability of the high power pin driver is minimally required in the range of 200 mA to 300 mA considering both the DB-WBI peak power consumption and the melting current limitation of the cantilever probe card needle.

Given the merged structure of the DB-WBI, a longer time is required to write/read the full cell data compared to the standard DRAM operation because of the leakage current of multi-cell operation due to soft bridge defects in the unmatured process. Therefore, for optimal write and read time decision during DB-WBI operation, consumed time should be measured through the design simulation of the EDA tool and the evaluation of the write time by DB-WBI operation at the ATE (automatic test equipment).

Figure 5. Operation flow of the DB-WBI stress method

Fig. 5 shows the operational flow of the DB-WBI stress method. The flow of the DB-WBI stress method consists of the write and read stress patterns including the even/odd WL stress pattern, true/complement WL stress pattern, and true/complement write-modified read pattern with a S/A operation. Because latent defects differ in screenability according to the defect structure, the value of the DC bias stress factors is experimentally determined. The DC bias conditions of stress patterns are decided by the screen-priority of latent defects according to the specified DB-WBI stress pattern application. Finally, the total time of the DB-WBI stress patterns depends on the bathtub evaluation of the DB-WBI stress method. 2.3. Defect Screenability of the DB-WBI Stress Method

In general, resistive latent defects are mainly due to variations of the fabrication process such as etching, CVD,


and photo among others. These latent defects are harder to screen with fixed voltage stressing in the conventional burn-in or final testing stages. Table 1 shows the characteristics of the DB-WBI stress method selectively applied to latent defect models. The DB-WBI stress table is summarized by a defect analysis to verify the screen effectiveness of the DB-WBI stress method. For screening, effective factors are selectively applied to the device with optimized conditions as the device has a different defect PDF (probability density function) depending on whether or not a matured process was used. To screen for diversified defect types at the wafer level, enhanced controllability is important with respect to yield-up, functional test time reduction, and lower defect rate for reliability. Therefore, as many as possible predictable defect models should be added for extraction of the effective stress factor. In DB-WBI, the main stress factors are the DC bias control factors, the write operation patterns, and read disturbing patterns for cell to cell stress between bit-lines. For example, DRAM cell capacitance comprises oxide, nitride, and oxide in old capacitance types.

The DC bias stress factors can apply electrical stress to the potential defect node and current paths. For example, resistive latent defects are due to the WL to WL micro bridge, the BL to BL micro bridge, the GD_short, and the GS_short within the same cell or long bridges between the other cells. Generally, because resistive latent defects on good die tend to pass normal test patterns, it is more difficult to screen resistive latent defects than hard defects, which are easily sorted by conventional test patterns. Most resistive latent defects tend to have the characteristics of progressive failure. To make progressive potential defects into hard defects, it is necessary to apply electrical stress between resistive defect nodes.

For screening latent defects with cell cap ONO (oxide-nitride-oxide) when the write pattern is operating, the latent defect of the cell capacitance can be screened by a voltage difference forced differentially through VBL and VP nodes from ATE. The proper stress values of the VBL and VP can be defined by a break-down voltage calculation of the oxide and nitride thickness. However, the optimal condition for mass production is generally determined through experimental stress characteristic evaluation. Main reliability defects related to the cell capacitance, gate oxide, and cell junction are measured from fail bits induced by write, read stress pattern, and other stress bias conditions.

Fig. 6 shows that when operating the DB-WBI, resistive latent defect models between BL and BL can be screened by applying electrical stress with a voltage level difference between the adjacent cells. The stress of the potential difference between adjacent cells is formed by switching the operation from high to low voltage.

Table 1. The screen characteristics of the DB-WBI stress method

Figure 6. Stress influences for potential defect in the

write/read operation of DB-WBI stress pattern (a case of 8F2 process)

In particular, among voltage transition cases, the transition from data 1 to data 0 is most effective for screening resistive bridge defects. Latent defects of resistive micro bridges are continuously stressed under a looped burn-in timing operation by a write or read stress pattern. In addition, if the structure of the defect is physically influenced by the DC bias level, the bias level for optimal stress can be controlled in the run-time pattern operation. However, it is not easy to choose the best pattern condition for the optimized stress condition for defects which range from major defects to minor defects defined through a yield learning analysis. Also, in the CMOS fabrication process, gate oxide thickness has a deviation with a Gaussian distribution due to process variation and the gate oxide thickness tends to lower the cell VT because of high-speed switching. Therefore, to choose the optimal stress condition for production, bathtub evaluation of oxide degradation should be considered.


Figure 7. Bathtub graph to find proper stress time

Fig. 7 shows a bathtub curve example of D92 512M DRAM achieved by a DB-WBI stress method and wafer final test. The results show that most of the die including the latent defects can be screened in 3 minutes under the specified DB-WBI condition compared to bathtub times during the package burn-in of the immature process of 24 to 48 hours. That is, wafer level bathtub results show that the burn-in time can be drastically shortened by the merged structure of the DB-WBI. In addition, as shown in Fig. 7, over 90% of the overall latent defects are screened in just 1 minute and within 3 minutes, 12.3% of the latent defects among the good chips passed by the final wafer test are further screened by the DB-WBI stress method. After 3 minutes, the latent defect screen rate is saturated. Therefore, increasing pre-screened latent defects in the wafer level test imply an increase in the overall yield of the package test process. However, in a real fabrication process, because the probability of major defects can change continuously, the stress condition of the DB-WBI should be verified with respect to whether the pre-screened latent defects are effective in yield enhancement in the package test process or not. In DB-WBI stress method control, the most important step is to find effective stress patterns for defect types defined through defect analysis of the predictable latent defect models and field reliability claim defects. 3. Statistical Defect Screen Optimization Method Using a Response Surface Method

To efficiently screen out only the weak cells while not overstressing the good cells, the DB-WBI stress parameters must be carefully chosen. In addition, optimizing the DB-WBI stress conditions under the process variation is very difficult and time consuming. In general, a long evaluation time is required to obtain the massive experimental data required to determine the burn-in production time and conditions or to meet requirements of the reliability. However, in reality, a long evaluation time to optimize a specific condition is not

feasible. In such circumstances, the proposed DB-WBI stress method also has difficulty optimizing many parameters simultaneously. Further, if the yield deviation is very large in the immature process, optimization is very difficult job. Therefore, we investigated a statistical method to efficiently reduce evaluation time and to precisely extract optimal conditions. Among DOE (design of experiments) methods, we chose to use the RSM (response surface method), which can simulate and optimize many parameters simultaneously [13-15]. In this section, we describe the visualized stress effects and procedure for modeling the stress effects by the proposed analysis-feedback flow of DB-WBI stress using RSM.

3.1. The Proposed RSM Analysis-Feedback Flow of the DB-WBI Stress Method

In an immature fabrication process, the deviation of the manufacturing test yield in the wafer test is high. The difference in wafer test yield is over 10% even within the same lot group. Generally, however, DB-WBI stress is evenly applied to the device whether the yield is high or not before the wafer test. In such circumstances, it is not easy to screen out only the weak cells while not over-screening the good cells. To address this problem, we have considered DOE method, which is used for factor screening and optimization for optimal design parameter and process parameter in industry. Especially, the purpose of RSM is to approximate the function ƒ in terms of input/output of specified system. Function ƒ may be a linear or quadratic function, or involve higher order terms of the factors. We adopted statistical DB-WBI stress optimization using RSM. For an effective stress optimization system, it is important to define X factors and output response Y for the DB-WBI stress analysis system. We designed a RSM analysis flow to define the effectiveness of the DB-WBI stress parameter as shown in Fig. 8. In this flow, it is assumed that tested dies throughout the “Wafer Final Test” step of the wafer test, prior to assembly, are fully verified good dies in the packaging assembly step. Therefore, by statistically comparing fail die differences screened by RSM-DOE between the 1st “Wafer Final Test” and the 2nd “Wafer Final Test”, we can construct a stress effect model to produce a response surface regression equation, Y=f(x).

First, to determine the system output response Y, we investigated the response Y which has to possess adequately linear characteristics while under the influence of the DB-WBI stress factor. Using correlation analyses, we evaluated different Y candidates such as the total fail-bit counts in a die, wafer test yield, fail-bit count according to patterns, and the current difference before/after stress, and we found that the fail die count was the most suitable candidate for response output Y. The following DC bias stress parameters are considered the most influential and necessary to control in terms of the latent defect screen: VCC, VPP, VBL, VP, VBB, and tRC.


Figure 8. Proposed statistical DB-WBI stress optimization

flow using RSM

For economical experimental design, before using RSM in the DB-WBI stress method, we applied a screening DOE to the DB-WBI parameter. Based on the screening DOE, we selected the four dominant control factors VCC, VPP, VBB, and tRC as X factors for the RSM experiment. To perceptively understand the response of a system, it is often convenient to use the coded value of a design variable.

3.2. RSM-DOE and Response Analysis

In the RSM experiment, it is important to determine how a specific response is affected by changes in the level of the factors over the specified levels of interest. A simple 2k factorial experiment would allow us to fit a first-order model. However, in the RSM experiment, we could check for curvature by adding center-points to the 2k factorial. Further, a fitted second order model would allow robust parameter design. RSM facilitates determination of controllable variables values that optimize mean response and minimize variability in the response transmitted from “noise” variables.

Therefore, for the RSM experiment, we designed the exploratory parameter levels shown in Table 2. The RSM experiment of the DB-WBI stress was run according to the

Box-Behnken design, which can minimize experiments of DOE, shown in Table 3. The total number of experiments to be run is 27 but we reduced this to 25 runs by adjusting the number of center point experiments from three to one. We limited the experiment lot size to contain only 25 wafers so as to exclude lot-to-lot variations.

Table 2. Parameters explored for the RSM experiment

Factors Parameter level( Low, Middle, High)

VCC 3.0 V,3.2 V ,3.4 V VPP 5.2 V,5.5 V,5,8 V VBB -1.3 V,-1.5 V,-1.8 V tRC 5 ms,100 ms,200 ms

Table 3. Box-Behnken Design

Box-Behnken Design

Factors: 4 Replicates: 1 Base Runs: 27 Total Runs: 27 Base Blocks: 1 Center Points: 3

For every experiment, we used MINITAB software [16]

for statistical analysis. In addition, experiments for each condition were run according to the run order of the RSM-DOE shown in Table 4. Both DC and FUNCTION as response Y of latent defects screened by RSM-DOE were added to Table 4. DC is the device counts that failed by a dc parametric test due to their being over-stressed after RSM-DOE. That is, DC is a guideline response index to judge whether FUNCTION of response is suitable or not. The limitation of the RSM-DOE was to find the yield drop factor. FUNCTION represents the latent defect device counts screened by the function test after RSM-DOE.

Table 4. Analysis table of the RSM-DOE


As shown in Fig. 9, the first response analysis has an R-Sq of 66.7% and a P-value of 0.289 from analysis of variance before pooling. This indicates that the regression equation is not yet adequate. Insignificant terms were pooled to compare the significance level of 0.05. Although the R-Sq value decreased from 66.7% to 61.8%, the R-Sq (adj) improved from 20% to 38.9% and the P-value of the regression improved from 0.289 to 0.043, which lies within the significance level of 0.05. In general, a R-Sq value of over 80% in a mature process indicates a mean yield of over 90%. Here, the R-Sq value of 61.8% is certainly lower. However, in an immature process, this is considered reasonable in terms of maximum yield differences of 30% scattered in a process. For R-Sq up to 90%, with a wafer yield similar to a matured process, it is possible to select sampling wafers with up to 80% yield among many lots, but this is too costly. Moreover, for overall process optimization, it is not a feasible sampling method. Stress effects, including the noise factor of an immature process, could be modeled to address this issue. The response regression equation can be summarized as the following equation.

VBBVCC-VBBVPP.

VCC.tRC-.VBB +. +

VPP.VCC +.+.

r wafer) =en rate peefect scre (latent dResponse Y

!!!"!"

!!!

!!"

19512444169

1322829093244

89188351176046916

22

2

(1)

Therefore, R-sq = 61.8% and R-sq (adj) = 38.9% indicate

that 61.8% of the total variation in the DB-WBI stress can be explained by the fitted model (1) and the estimate of the error variance provided by the residual mean square is 38.9% of the error variance estimate using the total mean square. Using the fitted equation, we can simulate and analyze the influence of individual factors to find the optimal stress condition, as shown in Fig. 10. By using the response regression equation

(1) in MINITAB, we can better intuitively understand the influences of factors compared with previous engineering-based lot evaluation.

(a) Old DB-WBI stress condition

(b) Optimal conditions analyzed by RSM response optimizer

Figure 10. Response Optimizer Comparison in MNITAB software

In Fig. 10(a), the result shows that the previous experimental conditions had a considerable influence on screening defects. But, it is not adjusted to optimal conditions for maximum defect screen rate. The latent defect screen rate of Fig. 10(a) is only 8.75 chips per wafer. However, in Fig. 10(b), the screen rate of the function fail is 56.3 chips per wafer. The RSM response optimizer analyzes the optimal

Figure 9. Response surface regression analysis before/after the pooling

(a) Before Pooling (b) After Pooling


screen value of each factor. The response optimizer shows that the stress effect of each stress factor reaches its maximum at the curvature point. Therefore, using previous conditions, 15.5% of the defects among latent defects are screened whereas 84.5% of the remaining latent defects are unscreened. 4. Experimental Results

We can simulate DB-WBI stress effects with the response

regression equation (1). To explore the influence of different stress effects, we conducted a pilot experiment in which we applied different DB-WBI stress conditions to the sample wafers after the final wafer test.

Fig. 11 shows the different screened latent defects compared with the wafer test map. The map shows that the simulated results of the RSM optimizer and a pilot experiment correspond exactly. In addition, screening by DB-WBI stress revealed that the majority of screened latent defects are single bit stuck failures (Fig. 11(b)). This result is consistent with most package and reliability test failures which are single bit failures. To verify screen effects according to the analysis of the RSM response optimizer, a production experiment by the split group was conducted using the values of optimum control factors. The comparison between the non-RSM condition and RSM-optimized condition is summarized in Table 5. When using the previous WBI condition, the time used for package burn-in is 24 hours and the accepted PRT (production reliability test) index for production is less than 200 ppm.

Table 5. Yield and reliability evaluation results

Experiment Group

Package Burn-In

Time

FT- Hot Test

Yield

FT- Hot @speed

Test Yield

FT-Cold Test Yield

Reliability Data

(PRT)

Non-RSM DB-WBI 3 hrs 93.3% 97.5% 97.1% 830 ppm

(6/7226)

With RSM DB-WBI 3 hrs 97.3% 97.9% 99.3% 99 ppm

(1/10132)

As shown in Table 5, when the package burn-in time was

changed from 24 hours to 3 hours for time-to-market, the PRT index increased to 830 ppm compared with 200 ppm, which is the quality guideline. However, when the RSM condition was applied and the package burn-in time changed from 24 hours to 3 hours, a PRT index of 99 ppm was obtained. A comparison of the total test yield of the two groups clearly showed that the yield difference between the two groups was 6.2% as a result of increase in yield from 88.3% to 94.5%. That is, 6.2% more latent defects are screened during the wafer test process. As a result, the total yield of the package test is improved.

(a) Function fail die counts screened by old DB-WBI stress condition

(Orange Color)

(b) Single bit counts of the function fail dies screened by optimal

DB-WBI stress using RSM (Orange Color) Figure 11. The difference of screened latent defects

The package test executes three steps: the final hot test, the final speed test, and the final cold test. Comparing each test process, we found that the final hot test results in the largest yield improvement of 4%. The yield of the cold test process is improved by 2.2%. However, the yield improvement of the high-speed test process was very slight at 0.4%. In terms of stress acceleration, we found that the DB-WBI stress method helps to screen the latent defects under-screened by conventional functional test patterns. In addition, in this


experiment, we recognize and emphasize the importance of overall optimization in terms of statistical control of many stress factors.

Consequently, as shown in our experimental results in immature process of the industrial manufacturing, we proved that the proposed statistical DB-WBI stress method can significantly reduce burn-in time and increase yield of products. Especially, the proposed method contributes to significantly reduce engineering time required to optimize burn-in conditions. In addition, the increased yields by the proposed method are pivotal to reduce memory manufacturing costs.

5. Conclusion

The long time required for package burn-in test process,

which can take as much as 80-90% of the manufacturing testing time, is the bottleneck of overall semiconductor manufacturing turnaround times. Therefore, burn-in optimization for yield and reliability is becoming more and more important in scaled DRAM developments. Especially, at the wafer level, we proposed a new statistical defect screening methodology targeting DRAM latent defects to enhance reliability of deep-submicron devices. The proposed DB-WBI (defect based wafer burn-in) stress method, which is compatible with current wafer probing technology, has shown to be very helpful in reducing overall manufacturing test time, enhancing reliability, and raising yield. Therefore, by combing the DB-WBI stress method and RSM, we have achieved the quality level of KGD requiring for mobile consumer DRAM products on the matured process.

The proposal is applied to the 512M Mobile DRAM family, Graphic DRAM family developed on the 90 nm 8F2 and 80 nm 6F2 design rule process.

6. Acknowledgment

The authors would like to thank Woosik Jeung, Inseok

Hwang, Seokho Park, kwanjong Lee, Junsoo Ji, Kunhan Kim, Sejang Oh, Yonghoon Lee, Miyeon Cho, Miwha Moon, Jaeyoung Lee, Sewoong Park, Sungho An, and Sungik Jang for their technical support and valuable discussions in the wafer burn-in test process development.

References [1] P. R. Morrow, C. M. Park, S. Ramanathan, M. J. Kobrinsky,

and M. Harmes, “Three-Dimensional Wafer Stacking Via Cu–Cu Bonding Integrated With 65-nm Strained-Si/Low-k CMOS Technology”, IEEE Electron Device Letters, Vol. 27, pp. 335-337, 2006.

[2] W. Koh, “Memory device packaging - from lead frame packages to wafer level packages”, Proceedings of IEEE CPMT Conference, pp. 21 – 24, 2004.

[3] J.U. Knickerbocker, C. S. Patel, P. S. Andry, C. K. Tsang, L. P. Buchwalter, E. J. Sprogis, H. Gan, R. R. Horton, R. J. Polastre,

S. L. Wright, and J. M. Cotte, “3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias“, IEEE Journal of Solid-State Circuits, Vol. 41, pp. 1718-1725, 2006.

[4] S. Pozder, R. Chatterjee, A. Jain, Z. Huang, R. E. Jones, E. Acosta, “Progress of 3D Integration Technologies and 3D Interconnects”, Proceedings of International Interconnect Technology Conference, pp. 213 – 215, 2007.

[5] T. Sudo, “Present and Future Directions for Multichip Module Technologies”, IEEE Journal of Solid-State Circuits, Vol. 30, pp. 436-442, 1995.

[6] W. L. Ivy Jr., P. Godavarti, N. Alizy, T. Mckenzie, D. Mitchell, “Sacrificial Metal Wafer Level Burn-In KGD”, Proceedings of Electronic Components and Technology Conference, pp. 535–540, 2004.

[7] D. R. Conti and J. V. Horn, “Wafer level burn-in”, Proceedings of Electronic Components and Technology Conference, pp. 815-821, 2000.

[8] W. R. Manna, F. L. Taber , P. W. Seitzer, and J. J. Broz, “The Leading Edge of Production Wafer Probe Test Technology”, Proceedings of International Test Conference, pp. 1168- 1195, 2004.

[9] Y. Nakata, I. Miyanaga, S. Oki, H. Fujimoto, “A Wafer-Level Burn-in Technology Using the Contactor Controlled Thermal Expansion”, Proceedings of International Conference on Multichip Modules, pp. 259-264, 1997.

[10] T. Furuyama, N. Kushiyama, H. Noji, M. Kataoka, T. Yoshida, S. Doi, M. Ezawa, and T. Watanabe, “Wafer burn-in (WBI) technology for RAM's” Proceedings of International Electron Devices Meeting, Technical Digest, pp. 639-642, 1993.

[11] I.-G. Kim, S.-K. Choi, J.-H. Choi, J.-S. Park, “DRAM reliability characterization by using dynamic operation stress in wafer burn-in mode”, Proceedings of Reliability Physics Symposium, pp. 361-365, 2003.

[12] H. Seo, G. Jin, K.-H. Yang, Y.-J. Lee, J.-H. Lee, D.-H. Song, Y.-C. Oh, J.-Y. Noh, S.-W. Hong, D.-H. Kim, J.-Y. Kim, H.-H. Kim, D.-J. Won and W.-S. Lee, “Charge trapping induced DRAM data retention time degradation under wafer-level burn-in stress”, Proceedings of Reliability Physics Symposium, pp. 287-291, 2002.

[13] R. H. Myers and D. C. Montgomery, Response Surface Methodology: Process and Product Optimization Using Designed Experiments, John Wiley and Sons.

[14] B. P. Harish, N. Bhat, and M. B. Patil, “On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, pp. 606-614, 2007.

[15] A. A. Mutlut, C. Kwongt, A. Mukherjeett, and M. Rahmant, “Statistical circuit performance variability minimization under manufacturing variations”, Proceedings of International Symposium Circuits and Systems, pp. 3025-3028, 2006.

[16] MINITAB 15, www.minitab.com, Minitab Inc.

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