Nano Defect Detection

Seong Ho Yoo

Agenda

o Importance of nano defectivity control

oDefect Sources & Size distribution

oDefect Root‐cause Analysis

oDetection Challenges & Next Gen targets

Importance of defectivity control

|

Nano De

fect 

impacts p

rofit

Competitive wafer cost

Ramp & time‐to‐market 

Product reliability

Prepare for next gen high densities 

*Nano‐defects = <50nm*High $$ penalty for ‘incorrect’ inspection system / strategy

Defect generation mechanisms

• Material Contact• Air & Liquid Movement• Nucleation, Condensation

Physical

• Electric Spark• Plasma Discharge• Wafer Arcing

Electrical

• Chemical Reaction• Material Degradation• Corrosion

Chemical

|

Importance of nano-defectivity controlInspection strategy & methods

|

Flag Excursion

Classify defect

Isolate Source Fix issue Monitor

* Early & Actionable

Agenda

o Importance of defectivity control

oDefect Sources & Size distribution

oDefect Root‐cause Analysis

oDetection Challenges & Next Gen targets

Defect sources

Defect Sou

rces

Wafer substrate

Process tools & Materials

Integration

Patterning

PID

Residue

embedded

Bridge

Stacking Fault

Fall‐ons

Sensitivity needs for polished Si & films

|

oxide

poly

Critical defect size

design node

How small defect would be a problem?Defect decoration

Pattern Defects 

FA Analysis

Root Cause: smaller than DR size defect

Si Nitride

SiONS‐HMACL

Photo resist

Poly Si

Nano-defects: Small defect matter

Agenda

o Importance of Defectivity Control

oDefect Sources & Size distribution

oDefect Root‐cause Analysis

oDetection Challenges & Next Gen targets

PWP (Particle per Wafer per Pass) Test: Qualifying equipment, components, materials AND defect isolation

Process ToolInput materialsProcess Tool

Input materialsPre‐scan Pre‐scan  Post Scan Post Scan 

•# Added Defects•Defect Types•Surface Quality

Material issue not chamber related

Repeated Operations

Beyond Individual Defect Isolation: Surface Quality Monitoring

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CMP Excursion

Slurry Residue

Thickness variation

Poor Etch

Tip of Iceberg

SURFImage

Defect map

Wafer InspectionProcess monitor

SPC/ RBB Defect

classification& Haze

Tool released for production

Passed

Adders/DOIFall-on, scratch

Non-process DefectsCOP, In-film

Surface QualitySURFImage

SEM review w/ EDX

SEM Size: <30nm

SEM Size: >50nm

Scratches

Failed

HW issue A

HW issue B

HW issue C

Defect Review and Root-Cause AnalysisSEM review and EDX

Agenda

o Importance of Defectivity Control

oDefect Sources & Size Distribution

oDefect Root‐cause Analysis

oDetection Challenges & Next Gen targets

Detection challenges getting harder

1. Amplify Signal

2. Suppress Noise

3. Manage Cost of ownership

4. Invest in Technologist + Vendors development

|

polished wafer

film

defect scatter

surface scatter

defect scatter

surface scatter

Challenges:

Optimizing for Signal, Noise, and COO

|

Simulations &Complex Algorithms

Optical test benches

Architectural Analysis

Available levers

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Detection Levers

Laser wavelength

Laser power

Spot size

Scattered light collection

PMT noise / QE

Scanning speed

11/9/2012 www.kla-tencor.com