A New Surface Potential-based Compact Model for IGZO TFTs in

RFID Applications

Ling Li, Guanhua Yang, Ming Liu

Institute of Microelectronics，Chinese Academy of Sciences, China

Outline

Introduction of IGZO TFT

Multiple Trapping and Release Theory

Surface Potential and Model Equations

RFID Circuit simulation

Summary

IGZO TFT application-Display

a-Si LTPS a-IGZO Organic

Mobility(cm2/Vs) ~0.5 ~100 10~80 5~6

Uniformity Good Poor Good Poor

Reliability Poor Good Good Poor

Cost Low High Low Low

IGZO TFT application-Flexible Circuit

Haitian, et al., “Large-scale complementatrymacroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors”

Adrian Chasin, et al., “An Integrated a-IGZO UHF Energy Harvester for Passive RFID Tags”

Flexible

Transparent

Room temperature

process

Low cost

IGZO TFT Structure

S/D: CrAu

L= 5um

T=294K

Motivation

IGZO TFT is an excellent candidate for display and

flexible circuit application

Circuit designers need accurate but fast compact

model

The charge transport mechanism in IGZO is

different from a-Si and organic

More physical meaning. Without numerical

calculation.

Outline

Introduction of IGZO TFT

Multiple Trapping and Release Theory

Surface Potential and Model Equations

RFID Circuit simulation

Summary

Multiple-trapping and release theory

Band-like

Hopping like

Free carrier density

Trapped carrier densityEffective mobility

Gate voltage and temperature dependent

mobility，Mobility vs. Temperature, at different Gate Voltage

Multiple-trapping and release theory

Outline

Introduction of IGZO TFT

Multiple Trapping and Release Theory

Surface Potential and Model Equations

RFID Circuit simulation

Summary

Analytical Surface Potential Solution

Density of total carrier

Poisson’s Equation

Gauss Law

F(0): The electric field at

the interface x=0

=

Analytical Surface Potential Solution

Density of states in IGZO

Trapped carrier density

Final Surface Potential Equation

Free carrier Trapped carrier

Analytical Surface Potential Solution

Taylor expansion

Schroder series modification

0 2 4 6 8 10 12 14 160

1

2

3

4

5

6

7

8

9

Vch=2.5V

Vch=5V

Su

rfac

e P

ote

nti

al (

V)

Vg-Vfb (V)

Line: Analytic solution

Symbol: Numerical result

Vch=7.5V

Maximum error : 0.03mV

Fully analytical without adding

new fitting parameters

Model equations

Effective Mobility Equation

Drain Current Equation

0 5 10 15 20

40

80

120

160

Ids

(uA

)

Vds (V)

Vg=20V

Vg=16V

Vg=12V

Line:Model

Symbol:Experimental

Integrate from FSS to FSD

Model equations

Capacitance Equations

Minkyung Bae, et al., “Analytical Current and Capacitance Models for Amorphous IGZO Thin-Film Transistors”

Ward’s charge-

partitioning scheme

Gummel Symmetry Test

All derivatives are continuous at Vds=0

2nd-order

1st-order

3rd-order

Key requirements for GST

• Odd function

• Nonsingular for nth-order derivative

Parameters extraction

Parameter initialization

Choose fitting strategy

RMS lsqError

RMS lsqError without noise

Log RMS lsqError

Input experimental

data

Converge

Least square method

Output fitting parameters

Exit

Change convergence

condition

No

Yes

m0

TA

n0t0

Parameters extraction

-20 -10 0 10 200

0.5

1

1.5

2x 10

-5

Vgs [V]

Ids [A

]

data

model

Automatic parameter extraction

Vds=1V, 20V

5 10 15 20 250

0.5

1

1.5x 10

-5

Vds [V]

Ids [A

]

data

model

Automatic parameter extraction

Vgs=-4V, 4V, 12V, 20V

Vds [V]

Accurate

&

Rational

Model results

Output and gds-Vds curves

0 5 10 15 20

40

80

120

160

Ids

(uA

)

Vds (V)

Vg=20V

Vg=16V

Vg=12V

Line:Model

Symbol:Experimental

0 5 10 15 200

4

8

12

gd

s (mS

)

Vds (V)

Line: Model

Symbol: Measurements

Vgs=12V,16V,20V

Comparison between the calculation and experimental

data for output characteristics of IGZO under different

gate voltages and gds-Vds curves.

Model results

Transfer and trans-conductance curves

-5 0 5 10 15 20

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

Ids(

A)

Vg(V)

Vds=0.1V

Vds=3.1V

Vds=9.1VLine:Model

Symbol:Experimental

0 5 10 15 200

2

4

6

8

10

gm

(mS

)Vgs (V)

Vds=0.1V, 3.1V, 9.1V

Line: Model

Symbol: Measurements

Comparison between the calculation and experimental

data for transfer characteristics of IGZO under different

drain-source voltages and transconductance curves.

Model results

Temperature and gate capacitance curves

-15 -10 -5 0 5 10 151

2

3

4

5

6

Gate

capacit

ance (

pF

)Gate voltage (V)

L=40um

L=30um

L=20um

L=40um

L=30um

L=20um

Line:Model

Symbol:Experiment

0 5 10 15 20

0

5

10

15

20

25

30

35

Ids

(uA

)

Vds (V)

T=300K

T=280K

T=260KLine: Model

Symbol: Experiment

Vg=5V

Model results and experimental

data a good agreement

Outline

Introduction of IGZO TFT

Multiple Trapping and Release Theory

Surface Potential and Model Equations

RFID Circuit simulation

Summary

RFID circuit simulation

Verilog-A Module

Minkyung Bae, et al., “Analytical Current and Capacitance Models for Amorphous IGZO Thin-Film Transistors”

Simulation results & discussion

0 1 2 3 4 50

1

2

3

4

5

60

Vout

(V)

Vin (V)

60

50

25

16.7

12.5

10

W/L=

W/L=60

W/L=10

0 4 8 12 16 20

0

50

100

150

200

250

300

Fre

qu

ency

(K

Hz)

VDD (V)

W/L=50/1

W/L=50/2

W/L=50/5

Pseudo

-CMOS

RFID circuit simulation

RFID digital circuit block

• Ring Oscillator

• Synchronous Counter

• 3-8 Decoder

• 64bit ROM

• Manchester EncoderR

ing Oscillato

r

Synchron

ous

coun

ter

3-8

Deco

der

64bit ROM

DFF

Manchester encoder

3-8

Deco

der

Synchron

ous

coun

ter

BL

WL

CLK RFID logic output

RFID circuit simulation

Schematic diagram

Simulation results & discussion

Failure situation 1:

• Vdd=5V

• Driver transistor W/L=35

Minimum power

consumption

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Simulation results & discussion

Failure situation 2:

• Vdd=12V

• Driver transistor W/L=50

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Maximum Clock

Frequency

Simulation results & discussion

40 50 60 70 800

5

10

15

20

25

30

Fail

ure

vo

ltag

e (

V)

W/L

Failure voltage at different W/L of driver transistor

The shaded area

shows available region

for VDD and W/L.

Simulation results & discussion

RFID circuit simulation results

Manchester

encoded data

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Summary

•Incorporated multiple-trapping and release theory into compact modeling

•Proposed a new method for calculating surface potential analytically

•Developed the parameter extraction program for IGZO TFT compact model

•RFID circuit design based on developed model•Discussed the maximum operating frequency and

minimum power consumption in particular situation

Thanks for your attention!

Q & A