A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration

A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / IntegrationA Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration

Che-Sheng Chen1 ([email protected]),

Louis Thiam2, Ahmed Hussein Osman2,

Kuei-Ann Wen1, Long-Sheng Fan3

1 Inst. Of Electronics, National Chiao Tung University, Taiwan2 VCAD, Cadence Design System, Ltd, USA

3 Inst. Of NanoEngineering and MicroSystems,

National Tsing Hua Unversity, Taiwan

MotivationMotivation

Analog+Mixed-Signal + Digital Components

Signal Proc

Clock Tree& Divider

C-to-V

ADC

MEMS IP

GlueLogic

MEMSInter-digitized

Sensor

FEM Simulation

Cross-domain Verification

Design Team Fragmentation

Cross-discipline Verification

MEMS + Mixed-Signal +

Digital concurrent design Integration

Methods for efficient use of EDA + FEM

Single monolithic CMOS-MEMS

C-to-V

Inter-digitized Sensor IP

OutlinesOutlines MS/MEMS Co-Design Flow Overview

MEMS Design Sub-flow MEMS HDL Behavioral ModelingMEMS HDL Behavioral Modeling DRC-aware Layout GenerationDRC-aware Layout Generation

MEMS-IP Publishing/Integration Interface (SIMPLI) OverviewOverview Layout Black-boxingLayout Black-boxing HDL Code EncryptionHDL Code Encryption Electrical Parasitic ExtractionElectrical Parasitic Extraction

Mixed-Signal Design Sub-flow Correlated Double Sampling Capacitive ReadoutCorrelated Double Sampling Capacitive Readout

Summary

MS/MEMS Co-design FlowIP Integration ApproachMS/MEMS Co-design FlowIP Integration Approach

SIPP-SIMPLI (SIPP MEMS PLatform Integrator)

MEMS Design Sub-flow

MEMS/Mixed-Signal Design Sub-flow

CM

OS

ME

MS

Fou

ndry

Des

ign

Kit

Physical Design

Electro-mechanical Simulation

IC S

ystem S

pecificationsAnalog (M

ixed-S

ignal)E

lectro-mechanical

Physical Design

Electrical Simulation

Digital

Top

-dow

nT

op-d

own

Bot

tom

-up

Functional Validation

Physical Integration

ME

MS

S

pecifications Inte

grat

ion

/ P

ublis

hing

MEMS design flow is traditionally top-down starting from mechanical characteristics with FEM iterations

SIPP-SIMPLI interface is providing the bridge between MEMS and IC designers

IC design flow integrate MEMS components as IP


MEMS Design Sub-flow MEMS HDL Behavioral ModelingMEMS HDL Behavioral Modeling Specification-Driven VerificationSpecification-Driven Verification DRC-aware Layout GenerationDRC-aware Layout Generation

MEMS-IP Publishing/Integration Interface (SIMPLI) OverviewOverview Database StructureDatabase Structure Code/Layout EncryptionCode/Layout Encryption Electrical Parasitic ExtractionElectrical Parasitic Extraction


Summary

MEMS Design Sub-flowTop-down approachMEMS Design Sub-flowTop-down approach



CM

OS

ME

MS

Fou

ndry

Des

ign

Kit

Physical DesignElectro-mechanical Simulation

GeometricalBehavioral Macro Model

(MM)

FEM Simulations

N-DOFReduced-Order Model

(ROM)

P-Cell Layout Generator Creation

Layout Generation Optimization

Post-layout Sign-off

IC S

ystem S

pecifications

Electro-m

echanical

GU

I

GU

I Top

-dow

n

MEMS Design Sub-flow DetailsInterleaved InteractionMEMS Design Sub-flow DetailsInterleaved Interaction

1BFoundry

Design Kit (180nm)

1AMEMSDesign

Specifications

2AMEMS Executable Specifications Creation

3AMEMS Topology Selection

4AGeometrical/Mechanical Nominal Design

2BMEMS Design Validation Strategy

MEMS Top-down Functional Design

MEMS Top-down Physical Design

5ANominal Finite-Element Verification

6Geometrical/Mechanical Models Enhancement

7BGeometrical/Mechanical Design Optimization

7ANominal/Statistical Verification with Enhanced Models

3BP-Cells Creation

4BMEMS Layout Nominal Design Generation

5BMEMS Block EarlyDesign Rule Checking

8CMEMS Block FinalDesign Rule Checking

8AFinite-Element Sign-off

7CMEMS Layout/Abstract Final Design Generation

8DMEMS Block Electrical Parasitic Extraction

MEMS Design

Data Input

2CAuxiliary DRC Rules Creation

8BN-DOF Reduced-order Model Generation

9MEMS IP Packaging

MEMS HDL Macro-Modeling (1)Interfacing multi-physics, electrical and MEMS geometriesMEMS HDL Macro-Modeling (1)Interfacing multi-physics, electrical and MEMS geometries

Substrate connection port name

Parameters governing accelerometer geometrical dependancies

MEMS electrical ports corresponding to silicon ports

Mechanical ports expressed in VHDLAMS displacement type

Advantages of HDL behavioral modelling for MEMS:

Multi-disciplinary language Multi-disciplinary language combining physics and combining physics and electrical quantitieselectrical quantities

Open standard to enable Open standard to enable re-use and flexible mixed-re-use and flexible mixed-signal simulation signal simulation environmentenvironment

Ability to create highly Ability to create highly parameterizable parameterizable component librariescomponent libraries

MEMS geometrical MEMS geometrical structure description can structure description can be part of the macro-modelbe part of the macro-model

Natural convergence Natural convergence toward mixed-signal and toward mixed-signal and digital verificationdigital verification

MEMS HDL Macro-Modeling (2)Describing multi-physics equivalence with electricalMEMS HDL Macro-Modeling (2)Describing multi-physics equivalence with electrical

Expression of external force induced on the proof mass due to acceleration and electrostatic interaction of proof mass in motion

Electrical behaviour implemented as induced capacitance on electrical ports

Each physical equations can be stated independently and HDL concurrent process statement enables system solution convergence

No limit to describe 2nd, 3rd order effects but at expense of development time

Models can be further enhanced based on results extracted from FEM simulation

MEMS Functional Verification cockpitSpecification-driven verificationMEMS Functional Verification cockpitSpecification-driven verification

Specification boundaries

Global variables

Specifications captured as expressions, waveforms or post-processing scripts

Testbench bank and simulation analysis definition

MEMS Functional ValidationRe-usable and scalable verification environmentMEMS Functional ValidationRe-usable and scalable verification environment

Specification failure

Sensitivity defines as F/g

Specification passedOptimum

geometrical parameter value

Single specification-driven environment for: Re-use and Re-use and

automation of automation of verification tasksverification tasks

Synthetic view of Synthetic view of design status design status versus versus specification targetspecification target

Testing Testing environment can environment can be hierarchicalbe hierarchical

Use model similar Use model similar to digital functional to digital functional verificationverification

MEMS Physical DesignDRC aware parameterizable layout generatorMEMS Physical DesignDRC aware parameterizable layout generator

Finger Width

Spring Beams Width

Finger Length Eatch Hole Separation Length

Eatch Hole Width Length

Initial Displacement

Electrode-to-Mass Separation Length

SKILL based PCell enables parameterization over geometrical parameters with DRC awareness

Parameterization linked directly to HDL macro-modelling in order to enabled schematic-driven layout


MEMS Design Sub-flow MEMS HDL Behavioral ModelingMEMS HDL Behavioral Modeling Specification-Driven VerificationSpecification-Driven Verification DRC-aware Layout GenerationDRC-aware Layout Generation



Summary

SIPP-SIMPLI Subflow conceptIP publishing and integrationSIPP-SIMPLI Subflow conceptIP publishing and integration




CM

OS

ME

MS

Fou

ndry

Des

ign

Kit

IC S

ystem S

pecifications

Functional Validation Physical Integration

ME

MS

Specifications

GU

I

GU

I

Encrypted Electrical-Mechanical Model

Electrical Parasitic Network

Silicon Calibrated Model

MEMS Black-box Abstract

Black-box Physical Verification

Layout Sign-Off

Inte

grat

ion

/ Pub

lishi

ng

SIPP-SIMPLI MEMS IP Publishing SubflowAutomated approachSIPP-SIMPLI MEMS IP Publishing SubflowAutomated approach

Auxiliary Virtuoso not shipped

Required MEMS IP input files

SIMPLI Library Processor

Spice, Spectre

coupled C Netlists

Layout View

Target PDK

Specification Files

LEF Files

GDSII Files

Symbol Generation

Layout Generation

DRC

Coupled C extraction

Abstract Generation

Symbol View

Black-boxing

Abstract View

Layout GDSII File

Abstract LEF File

Assura customization

Functional View

Encrypted Functional

File

Functional Description

Files

CDL Netlist

Measurement Files

CDL Black-box

Spectre Black-box

Spice Black-box

Functional View

SIPP-SIMPLI operated on standard inputs and generates views required for Mixed-Signal design within Cadence environment

SIPP-SIMPLI requires following Cadence tools: AMS Incisive for AMS Incisive for

processing HDL processing HDL modelsmodels

Abstract Generator Abstract Generator for black-box layout for black-box layout generationgeneration

Assura for MEMS Assura for MEMS DRC compliance DRC compliance

QRC for MEMS QRC for MEMS parasitics extraction parasitics extraction

SIPP-SIMPLI MEMS IP Integration SubflowAutomated approachSIPP-SIMPLI MEMS IP Integration SubflowAutomated approach

Only Virtuoso views have to be re-created in target PDK which might be packaged differently between MEMS IP provider and end-user

If PDK package identical between MEMS IP provider and IC designer then MEMS IP published by SIPP-SIMPLI can be re-used as-is

Required MEMS IP package

SIMPLI Library ProcessorTarget PDK

Symbol Generation

Abstract Generation

Symbol View

Black-boxing

Abstract View

Assura customization

CDL Black-box

Spectre Black-box

Spice Black-box

Functional Functional View

SIMPLI MEMS Package

SIPP-SIMPLI Virtuoso Custom InterfaceSingle interface for publishing and integrationSIPP-SIMPLI Virtuoso Custom InterfaceSingle interface for publishing and integration

Single interface and options for both publishing and integration

Interface integrated directly with Virtuoso platform and compatible with both IC 5.1.41 and IC 6.1.3

Support batch processing through SKILL APIs for entire library management and maintenance

SIPP-SIMPLI Layout ProcessingLayout black-boxing while enabling accurate integrationSIPP-SIMPLI Layout ProcessingLayout black-boxing while enabling accurate integration

Before After

SIP

P-S

IMP

LI

Abstract with antenna information

SIPP-SIMPLI Functional ProcessingHDL description encrypted while enabling accurate simulationSIPP-SIMPLI Functional ProcessingHDL description encrypted while enabling accurate simulation

Before After

SIP

P-S

IMP

LI

RSA encrypted code readable in AMS Designer

SIPP-SIMPLI Extraction ProcessingLayout extraction while enabling accurate parasiticsSIPP-SIMPLI Extraction ProcessingLayout extraction while enabling accurate parasitics

Before After

SIP

P-S

IMP

LI

Vibrating sensor floating in air dielectric

Sensor harness connecting to normal CMOS substrate

“Air” capacitance

CMOS capacitance


MEMS Design Sub-flow OverviewOverview MEMS HDL Behavioral ModelingMEMS HDL Behavioral Modeling Specification-Driven VerificationSpecification-Driven Verification DRC-aware Layout GenerationDRC-aware Layout Generation


Mixed-Signal Design Sub-flow OverviewOverview Correlated Double Sampling Capacitive ReadoutCorrelated Double Sampling Capacitive Readout Design SummaryDesign Summary

Conclusion

CMOS Mixed-Signal MEMS Subflow conceptMeet-in-the-middle approach

CMOS Mixed-Signal MEMS Subflow conceptMeet-in-the-middle approach



CM

OS

ME

MS

Fou

ndry

Des

ign

Kit

IC S

ystem S

pecifications

Analog (M

ixed-Signal)

Physical DesignElectrical Simulation

Behavioral HDL + MEMS Selection

Calibrated HDL + ROM

FastSPICE + ROM

Transistor + ROM

Mix

ed-le

vel

Floorplan/Route + MEMS Abstract

Preliminary Estimate + MEMS Abstract

Pre-layout Abstract

Post-layout Abstract + MEMS Rule Set

Mix

ed-le

vel

Digital

Top

-dow

nB

otto

m-u

p

CMOS Mixed-Signal MEMS Subflow detailsMeet-in-the-middle approach

1BModified Foundry

Design Kit (180nm)

1ADesign

Specifications

2IC Design Validation Strategy

3AMS Design Partitioning

4Block

Specifications

IC Top-down Functional Design

IC Top-down Physical Design

6AIC Design Functional Concept

Validation

6BIC Design Early Floorplanning

11IC Refinement Floorplanning

9IC Design Functional

Performance Validation

IC Design Data Input

1CSystem-level

Models

1DSystem-level Testbenches

1EMEMS

packaged IP

1FMEMS DFII

Testbenches

1G3rd Party IP

1HLegacy IP

Bottom-up Functional and Physical Design 5A

Analog BlockCircuit Design

5BAnalog Block

Behavioral Design

5CLegacy and 3rd

PartyIP Import

5DDigital

HierarchicalRTL Design

5EMEMS IP

Import

8AAnalog Block

Circuit Optimization

8BDigital Block

Synthesis

7IC Design

Re-specification

10AAnalog Block

Physical Estimation

12AAnalog Block

Physical Design

12BDigital Block

Physical Design

13IC Post-layout

Validation

14Block Physical

Integration Preparation

15IC Design Assembly

16IC Design

Functional Sign-off

10BDigital Block

Physical Estimation

Correlated Double Sampling ReadoutCorrelated Double Sampling Readout

CfInertial Sensor

Φ1d

Vout

Φ2

Φ1dΦ2d

Φ2d

Vrefp

Vrefn

Φ1d

Φ1d

Cs

Φ1

CDS circuit is suitable for capacitive sensor readout Offset cancellation & Low frequency noise reductionOffset cancellation & Low frequency noise reduction Suitable for following Analog to Digital conversionSuitable for following Analog to Digital conversion Following another S/H amplifier for proper sensitivityFollowing another S/H amplifier for proper sensitivity

Process: UMC CMOS-RF 180nm

Schematic Capture of Monolithic IntegrationSchematic Capture of Monolithic Integration

Accelerometer mechanical inputs stimuli through inherited connections

System output

Parameterizable accelerometer suitable for both simulation optimization and schematic-driven layout

Switched-cap sampling clock

Schematic-Driven Layout AssemblyHierarchical layout while reducing LVS errorsSchematic-Driven Layout AssemblyHierarchical layout while reducing LVS errors

MEMS accelorometer as abstract

Opened MEMS connections

Readout as plain footprint

List of nets that are completed routed.

Schematic-driven layout enables to track connectivity between schematic and layout view

SIPP-SIMPLI creates a connectivity aware view for safe layout integration

Custom router could be leveraged since MEMS black-box as connectivity and antenna information

SIPP-SIMPLI has also LEF file for digital P&R integration

Design SummaryDesign Summary

Specifications Conditions Value UnitSensor Input Range ±2 g

Sampling Freq. <100 kHz

Sensitivity Vsupply = 3.3v 218 mv/g

SFDR Vsupply = 3.3v 58.5 dB

Resonate Freq. 6.3 kHz

Output RMS Noise < 4kHz Vsupply = 3.3v 141 uV

Current Consumed Vsupply = 3.3v

Clock Freq. = 100KHz

360 uA

[2] Movement of the fingers triggered by external voltage source

[1] SEM of the ACC

The first result of accelerometer (ACC) fabricated with .18m 8” CMOS foundry under the constrain of standard CMOS process.

[3] Capacitance variation under the excitation of shaker with 20~8kHz shaking. ( The green one is the "PZT reference accelerometer“ provided as the reference and the blue one is the performance of DUT.)


MEMS Design Sub-flow OverviewOverview MEMS HDL Behavioral ModelingMEMS HDL Behavioral Modeling Specification-Driven VerificationSpecification-Driven Verification DRC-aware Layout GenerationDRC-aware Layout Generation

MEMS-IP Publishing/Integration Interface (SIMPLI) OverviewOverview Data StructureData Structure Code/Layout EncryptionCode/Layout Encryption Electrical Parasitic ExtractionElectrical Parasitic Extraction

Mixed-Signal Design Sub-flow OverviewOverview Correlated Double Sampling Capacitive ReadoutCorrelated Double Sampling Capacitive Readout Design SummaryDesign Summary

Conclusion

ConclusionConclusion

A Mixed Signal-MEMS co-design flow is proposed for CMOS/MEMS monolithic integration.

A MEMS IP Publishing/Integration interface is developed to enable handshaking between MEMS & Mixed signal circuits.

With parametric layout & HDL, MEMS/CMOS co-optimization can be achieved.

A fully integrated CMOS monolithic accelerometer has been implemented to demonstrate the proposed design flow.

Q & AQ & A

A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration

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