A Mini Stereo Digital Audio Processor Design DINESH GUNDU VIGNESH SABARINATH.
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Transcript of A Mini Stereo Digital Audio Processor Design DINESH GUNDU VIGNESH SABARINATH.
![Page 1: A Mini Stereo Digital Audio Processor Design DINESH GUNDU VIGNESH SABARINATH.](https://reader036.fdocuments.in/reader036/viewer/2022062322/5697c0061a28abf838cc5af4/html5/thumbnails/1.jpg)
A Mini Stereo Digital Audio Processor Design
DINESH GUNDU
VIGNESH SABARINATH
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Introduction to MSDAP
Aim:
Performing basic audio signal processing computations using a programmable FIR filter.
Implementation:
Linear convolution described by the equation for FIR filter design.
k).x(nh(k)y(n)N
0k
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Implementation
To save computation time: Multiplier is replaced by using the coefficients
represented in Power of Two format (POT). Use of 1 bit shift rather than employing a 16 bit
shifter.
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Rj = 0005
• RJ values dictate the amount of coefficients to consider for calculating 1 ui value. • The first uj will have 5 additions/subtractions given by the 5 coefficients.
Coeff = 00B4
• MSB corresponds to sign bit. 0 is addition and 1 is subtraction.• Rest of the 8 bits represent the magnitude.• The above coefficient is equivalent to adding the term x(n-180).
After every ui is calculated we shift it and add it with the next ‘ui’ in accordance with theequation shown above to generate the output for all 16 ui’s.
0 1 0 1 1 0 1 0 0
0 0 0 0 0 1 0 1
Sample Computation
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Dig
italA
nalo
gA system level abstraction of the MSDAP chip:
• A/D & D/A converter to sample inputs and make it available digitally.
• A controller unit that drives the processing unit (MSDAP) chip.
System Setting
ADC
DACC
on
trolle
r
MS
DA
P
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Signal Format - Input
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Signal Format - Output
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Processing ……………
Inputs
Coeff
RJ’s
State 2Reading Rj
State4Reading
coefficients
State 6Working
StateReset
Reset
800 zeros in
both channels
Frame ‘0’
InReady ‘0’
Operation ModesState 0
Initialization
State 8Sleep State
State 1 Waiting for
Rj
Frame ‘0’
State 3Waiting for coefficients
Frame ‘0’
State 7Clearing State
State 5Waiting for
Inputs
One non
zero
Reset
Rese
t
Start
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INITIAL STATE 0:
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Entering State1 after initialization
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Entering State2 on Frame ‘0’ to capture RJs
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Entering State3 to wait for coefficients
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Entering State4 on Frame ‘0’ to capture coefficients
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Entering State5 to wait for data inputs
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Entering State6 on Frame ‘0’ to begin computation
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Entering State8 sleep state after 800 zeros in both channels
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Entering back to State6 computation on receiving one non zero
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Entering to State7 on Reset ‘0’ and back to State5 after reset
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Challenges
• Flags –
Synchronization issue.
• C Program output – Debugging internal
working steps.
• Blocking/Non-blocking – scheduling assignments.
• Non overlapping variables – Multiple Driver issue.
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C program computation snapshot
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MSDAP I/O Pins
Pin Name
TypePin No.
Function
VDDC Power 3, 14Connected to a well-decoupled +1.65V DC core power supply.
VDDIO Power 7, 19Connected to a well-decoupled +1.65V DC I/O power supply
VSSGround
4, 8, 13, 18
The core and I/O ground pins connected to GND
SCLK Input 1
System Clock : 50 % duty cycle clock at the frequency 26.88 MHz.
Timing reference to the internal I/O control signals.
The InReady and OutReady signals are updated during the rising edge of Sclk.
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Pin Name Type Pin No. Function
START Input 15 When set HIGH the processor goes into initialization
process. Asynchronous with both Sclk and Dclk.
Input 5 Chip goes into Reset state on LOW for one DCLK.
INREADY Output 12It is set HIGH when the chip is ready to read the data from the controller.
OUTREADY Output 11It is set HIGH when the chip is ready to transmit the processed data to the controller.
DCLK Input 2
Data Clock: 50 % duty cycle at the frequency of 768 KHz. Provides the timing reference for input sample
transmission. Inputs InputL/R are read during the falling edge.
MSDAP I/O Pins
RESET
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Pin Name Type Pin No. Function
INPUTL/INPUTR Input 17To carry the input samples serially to respective channels and is read at falling edge of DClk.
OUTPUTL/OUTPUTR
Output 9To carry the output processed samples of respective channels and transmitted at falling edge of SClk.
FRAME Input 20It aligns the serial coefficients, input and output samples.
Setfor one DClk when the controller transmits the sequence.
NC 6 Not connected
MSDAP I/O Pins