A Low Power LC-VCO and a Fast Divider forDVB-SH Applications

R. Pulido Medina, E. Ortega Garc ía, D. Ramos-Valido, Sunil L. Khemchandani, J. del PinoInstitute for Applied Microelectronics, Universidad de Las Palmas de Gran Canaria, Spain.

Published in XXVII Design of Circuits and Integrated Systems Conference.

Aviñon, Francia, 2012.

In this paper, the design of a fully integrated LC-VCO and a high-speed frequency divider by 2 is discussed. Using a standard 90nm CMOS technology, both circuits show a good performance for DVB-SH applications. With a control voltage between 0 and 1V, the VCO oscillates from 2.17 to 2.2 GHz, drawing only 13 mA current from a 1.2V supply. The VCO core uses a current feedback network to improve the phase noise response with low power. The divider core is formed with a low voltage swing current mode logic (CML) structure, which permits high frequency operation at very low power dissipation. The divider core draws only 200 μA from a 1.2 V supply. Both circuits occupy a chip area of 750x850 μm2, witch includes the measurement pads.

Conclusions

0

Circuits Design Simulations

INSTITUTO UNIVERSITARIO DE MICROELECTRÓNICA APLICADA (IUMA) UNIVERSIDAD DE LAS PALMAS DE GRAN CANARIA (ULPGC)

AbstractThis paper presents the design of a fully integrated LC-VCO and a high-speed frequency divider by two. Both circuits are designed for DVB-SH standard in 90nm CMOS technology. The VCO uses a current feedback technique to achieve better phase noise without causing an increase in power consumption. The oscillation frequency can be tuned from 2.17GHz to 2.2GHz, with a control voltage between 0 and 100 mV. The VCO only draws 13 mA from a 1.2 V supply. The divider core is formed by low voltage swing current mode logic (CML) structures, which permit high frequency operation at very low power consumption. The divider core draws only 200 μA. Both circuits occupy a chip area of 750x850 μm2, which includes the measurement pads.

This work is partially supported by the Spanish Ministry of Science and Innovation (TEC2008-06881-C03-01 and TEC2011-28724-C03-02), the Spanish Ministry of Industry, Tourism and Trade (TSI-020400-2010-55) and Cabildo of Gran Canaria.

Acknowledgement

Fig. 4. Conventional Master-Slave CML latch.

Fig. 10. LC-VCO and fast divider layout.

Fig. 11. Total system transient response.

Fig. 2. LC-VCO Phase Noise.

Fig. 5. Latch with single bias current and clock network.

Fig. 6. LC-VCO layout.

Fig. 7. Stand alone VCO transient response.

Fig. 8. Oscillation Frequency vs. Vtune.

Fig. 9. Stand Alone VCO Phase Noise.

Fig. 12. Phase noise of the whole system.

Fig. 1.LC-VCO. Fig. 3. LC-VCO with current feedback network.