A Low Power 10 Gb/s Serial Link Transmitter in 90 …...IBM Research CSIC Symposium November 2, 2005...

IBM Research

CSIC Symposium November 2, 2005

A Low Power 10 Gb/s Serial Link Transmitter in 90-nm CMOS

Alexander Rylyakov and Sergey Rylov

IBM T.J. Watson Research Center, Yorktown Heights, NY, USA

IBM Research

CSIC Symposium | November 2, 20052

Transmitter Top-Level Block Diagram

4:2 MUX

4 x 2.5 Gb/s 2 x 5 Gb/s 4 x 10 Gb/s 10 Gb/s

InputBuffers 4-tap FFE DAC/Driver

DAC settings5GHz CLOCKKey transmitter goals

• Demonstrate half-rate architecture at 10 Gb/s with reduced power dissipation

• Demonstrate modified DAC design with improved bias current mirroring, reduced leakage sensitivity and improved voltage reference switch

• Explore key performance metrics (power, output voltage swing, jitter, duty cycle distortion)at different temperatures and supply voltage conditions

Tx is a wirebond breakout testsite of the SerDes for chip-to-chip communications:“A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology”

M. Meghelli et al., accepted for ISSCC 2006

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Equalizationin time domain the signal, after passing through the channel, will spreadover adjacent sampling points, resulting in inter-symbol interference (ISI).

Feed-Forward Equalizer (FFE) attempts to correct for that by reshaping the signals before sending them into the channel.

channel FFEmain tap1st postcursor

n-1

ISI

n n+1 frequencytimeFFE + channel

in frequency domain this means attenuating low-frequency components of the signal and amplifying high-frequency components

The resulting transfer function is more broadband with less ISI

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Equalization (1-tap example)

yn = xn - α* xn-11-tap FFE:

if xn = xn-1 then yn = (1 - α) * xn

if xn ≠ xn-1 then yn = (1 + α) * xn

FFE de-emphasizes low-frequency components (1, 1 or -1,-1)and pre-emphasizes high-frequency components (1,-1 or -1, 1)

FFE channel

1 1 -1 -1 1 1 -1 -1 1 1 -1 -11 1 1

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Transmitter Chip Block Diagram

IDAC

1:4

1:4

5

6

tap 0

tap 3

192

AVTT

channel

chip

ed

1:4

5

6

tap 1

1:4tap 2

DAC/Drivers

ge

SEL0

SEL3

XOR0

SEL1 XOR1

SEL2 XOR2

XOR3

DIV 2

CLOCK 2

CLOCK 4

DATA 0DATA 2

DATA 1DATA 3

VDDA

MUX0

MUX1

4:2 MUX 4-tap FFE

198

tap weightspower down

4

sign bits

serial interface

VDDD

Three circuit design styles with differentpower and clock domains:

• analog (AVTT, no clock)• high-speed digital (VDDA, CLOCK2 and 4)• standard CMOS (VDDD, low-speed clock)

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CML Sub-blocks Design Highlights

SEL0

SEL3

XOR0

SEL1 XOR1

SEL2 XOR2

XOR3

DIV 2

CLOCK 2

CLOCK 4

DATA 0DATA 2

DATA 1DATA 3

VDDA

MUX0

MUX1

4:2 MUX 4-tap FFE

4 x 2.5 Gb/s

5 GHz

2 x 5 Gb/s 10 Gb/s (precursor)

10 Gb/s (main tap)

10 Gb/s (1st postcursor)

10 Gb/s (2nd postcursor)

Aggressively scaled for low-power CML ( current-mode-logic) blocks (buffers, latches, selectors).The 2.5 Gb/s latches have 150 µA tail currents (4 kΩ resistor loads) and the 5.0 Gb/s latches have 300 µA tail currents (2 kΩ resistor loads).

The timing condition between the 5 GHz CLOCK2 and the 5 Gb/s data at the input of the FFE has to be satisfiedacross process, voltage and temperature variations.

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IDAC and Output Drivers Design Highlights

IDAC

1:4

1:4

5

6

tap 0

tap 3

192

AVTT

channel

chip

ed

1:4

5

6

tap 1

1:4tap 2

DAC/Drivers

ge

• The output driver IDAC features novel current mirrors (with opamp-like structures) and dummy loads in the lower 4 bits, to match the leakage in the voltage reference nodes and improve linearity.

• Output stages (drivers, predrivers and pre-predrivers) carefully designed for timing with matching loads and symmetric layout.

• High-current carrying nodes are compliant with electro-migration rules, all chip I/O is ESD protected.

• Can drive both AC- and DC-coupled (50 Ω to AVTT) channels. AC-coupling is more challenging because DC and AC signals are loaded differently and that reduces maximum voltage swing, distorts the signal.

198

tap weightspower down

serial interface

VDDD

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Transmitter Core LayoutThe wirebond padcage of the chip(1.7mm x 1.7mm) is not shown.

Transmitter Core Dimensions: 700um x 550 um(the C4 version built of the same blocks is smaller)

CML CORE : 120um x 140um10 Gb/s

Drivers

CML Core

IDAC

SI

ESD

Clock Receiver

ESD

IDAC

140 µm

2.5 Gb/s 2.5 Gb/s

2.5 GHz 5 GHz

120 µm

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Test Setup

~

PRBS Generator Transmitter Chip

4 x 2.5Gb/s DATA

BERT

Oscilloscope

10Gb/s DATA

oscilloscope can be triggered either by a subrateclock signal (for eye diagram) or by a bitframe signal(for bit pattern)

Spectrum Analyzer

one of the differential 10 Gb/s output signals is directly observed on the oscilloscope, while another is applied to BERT to continuously verifyerror-free operation.

testing is done on-wafer with high-speed picoprobesand high-bandwidth cables, the output is AC-coupled to the oscilloscope and BERT

on-chip divider performance is monitored on the spectrum analyzer

2.5GHz CLOCK

5GHz CLOCK

Trigger

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10 Gb/s Transmitter Output (Unequalized)AVTT=1.65V / 42mAVDDA=1.2V / 32mAT=25C, 27-1 PRBS, tap0=tap3=0 tap1= +111100 tap2= -00000

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10 Gb/s Transmitter Output (with Equalization)AVTT=1.65V / 50.4mAVDDA=1.2V / 32mAT=25C, 27-1 PRBS, tap0=tap3=0 tap1= +111100 tap2= -11100

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10 Gb/s Transmitter OutputAVTT=1.65V / 42mAVDDA=1.2V / 32mAT=25C, 27-1 PRBS, tap0=tap3=0 tap1= +111100 tap2= -00000

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10 Gb/s Transmitter OutputAVTT=1.65V / 45.5mAVDDA=1.2V / 32mAT=25C, 27-1 PRBS, tap0=tap3=0 tap1= +111100 tap2= -10000

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10 Gb/s Eye Diagram at 25° Cerror-free operation at 231-1 PRBS, AC-coupled load

tap0 = tap3 = 0, tap 1 = +111111, tap2= -00100AVTT = 1.2V (38mA), VDDA = 1.2V (43mA), Vpp = 295mV (x2), Jitter p-p = 23ps

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Performance Summary

57

95

171

95

167

94

174

Power, mW

1.0

1.2

1.2

1.2

1.2

1.2

1.2

V mAmAV

28511.2380 x270

28831.65535 x270

23341.0235 x270

27521.2339 x2100

27821.65497 x2100

27511.2302 x2125

35801.65468 x2125

VDDAAVTTVpp, mVT, °C

error-free operation at 10 Gb/s, 231-1 PRBS, AC-coupled load

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Equalization of a 16” link (standard Tyco HM-Zd XAUI test backplane)

equalizedunequalized• Data rate: 6.3 Gb/s• Test sequence: 27-1 PRBS• BER (of equalized data): < 10-11

• All 4 FFE taps are used to open the eye• Data rate is limited by the sensitivity of the single-ended BER tester ( no filtering on the Rx side)• Test backplane introduces ~20dB of losses at 3GHz

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Conclusions

10 Gb/s error-free operation is demonstrated at 125 °C (231-1 PRBS, 0.9 Vppd into AC-coupled channel, 170mW total power). Maximum Vppd is higher at lower temperatures.

Maximum error-free data rate: 14 Gb/s at 25 °C

Low-power CML part is error-free at 1.0V supply at up to 70 °C, and at 1.2V at higher temperatures

Integrated version of the Tx successfully evaluated, will be reported in paper“A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology”M. Meghelli et al., accepted for ISSCC 2006

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Backup slides

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6-bit IDAC Performance

30

35

40

45

50

55

60

65

70

75

0 16 32 48 64

tap0 = tap2 = tap3 = 0AVTT = 1.65V, T=100°C

bit settings (tap1)

AVTT current( mA )

• bits 1:4 are linear• current jumps when bits 5 and 6 are turned on• headroom compression clearly visible at high currents

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TX Only Characterization*

10Gb/s Eye Diagrams10Gb/s Eye with -15% on FFE tap2

Main tap 600mVpd

27-1 ¼ rate data inputs leading to a serial PRBS length of 505(serial output measured with a spectrum analyzer)

* “A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology”M. Meghelli et al., accepted for ISSCC 2006

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10Gb/s Channel Equalization ExperimentTyco 16” Channel (Hm-Zd XAUI Test Backplane)

The evaluation channel Includes:Tx package->Evaluation board->12” cable->16” Tyco backplane->12” cable->Evaluation board->Rx package

33.4dB losses at 5GHz

A Low Power 10 Gb/s Serial Link Transmitter in 90 …...IBM Research CSIC Symposium November 2, 2005...

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