A Design of Low-dropout Regulator with Adaptive Threshold...

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, 2018 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2018.18.2.287 ISSN(Online) 2233-4866

Manuscript received May. 16, 2016; accepted Dec. 9, 2016 The Department of Electronics & Electrical Engineering, University of Dankook E-mail : [email protected]

A Design of Low-dropout Regulator with Adaptive Threshold Voltage Technique

Kyeong-Hyeon Park, Il-Suk Yang, and Yong-Seo Koo*

Abstract—In this paper, the characteristics of Low Dropout Regulators to which the adaptive threshold voltage technique was applied were analyzed. For this analysis, fore types of LDO were fabricated. Also Proposed LDO is fabricated in 0.18 um BCD process. The first was a conventional LDO. For the second type of LDO, the adaptive threshold voltage technique was applied to the error AMP and voltage buffer; for the third type of LDO, the adaptive threshold voltage technique was applied to the pass TR and for the fourth type of LDO, the adaptive threshold voltage technique was applied to the error AMP, voltage buffer, and pass TR. The adaptive threshold voltage technique applies a separate voltage to the body terminal of transistor to reduce the threshold voltage (Vth) and increase the drain current. In this paper, the adaptive threshold voltage technique was applied to each block. Then the characteristics and areas of the four types were comparatively analyzed. The area of the current-mirror of the error AMP and voltage buffer proposed in this paper decreased by about 61% compared to the conventional current-mirror. Furthermore, the area of the pass TR proposed in this paper decreased by 5.5% compared to the conventional pass TR and the regulation characteristic of the LDO improved Index Terms—LDO regulator, body effect, threshold voltage, Pass transistor, adaptive threshold voltage technique

I. INTRODUCTION

The recent development of integrated circuit technology and the cultural needs of consumers brought about the production and sale of numerous mobile multimedia devices that offer a variety of features, compact size, and light weight. Consequently, technologies to reduce the chip area size while maintaining the existing circuit characteristics are being developed in order to implement many features in the same chip area. The scale-down trend, however, presents great challenges to analog and mixed analog-digital chip designers because of problems such as higher sub-threshold conduction, increased gate-oxide leakage, lower output resistance and so on. In addition, this trend requires a high performance processing technique. So it is difficult to reduce the transistor size and VLSI chip size [1-3]. This paper presents a method to reduce the chip area while maintaining the circuit characteristics in LDO regulator. The LDO regulator is composed of the pass transistor, error amplifier, feedback resistor, and load. In the operating mode, the change of the output voltage is detected through the error amplifier. And the error amplifier generates an error signal. The generated error signal is transmitted to the load terminal through the pass transistor. The value transferred to the load forms a feedback loop through the feedback resistor. Although there is the external change through the feedback loop, it can provide a stable output voltage. So, an LDO regulator for which the adaptive threshold voltage technique was applied to decrease the area and improve the characteristics was proposed. Furthermore, the adaptive threshold voltage technique was applied in phases to verify the effect of the adaptive threshold

288 KYEONG-HYEON PARK et al : A DESIGN OF LOW-DROPOUT REGULATOR WITH ADAPTIVE THRESHOLD …

voltage technique. In this way, the characteristics and areas of LDOs to which the adaptive threshold voltage technique was applied were comparatively analyzed. To compare the characteristics, four types of LDOs according to the application of the adaptive threshold voltage technique were designed and fabricated. The adaptive threshold voltage technique can reduce the Vth limit effectively by controlling the weak positive bias between the body and source of transistors, can reduce the Vth limit by controlling the weak positive bias to reduce the transistor size and PMIC chip area. Furthermore, it is completely compatible with the standard CMOS process. The Proposed IC was fabricated in 0.18 um BCD process. The IC was manufactured based on the results of previous work [1]. The manufactured IC was verified and analyzed for its performance and characteristics.

II. ADAPTIVE THRESHOLD VOLTAGE

TECHNIQUE

1. Body Effect

Fig. 1 shows a typical PMOSFET transistor using the CMOS process. There are largely four terminals: drain, gate, source, and body. The gate terminal must receive a voltage to form a channel for current feed to the transistor. Furthermore, based on the source terminal, the drain terminal defines the driving area of the transistor as triode or saturation sections according to the applied voltage. The body terminal is referred to as the second gate terminal and offers a simple interpretation of the circuit. To prevent loss by leakage current, the body terminal shorts the body and source terminals, thereby preventing control by the body terminal. However, applying a voltage to the body terminal without shorting the body and source terminals changes the circuit characteristics, and this is called ‘body effect’ [2-5]. The body effect can be explained as follows. As shown in Fig. 1, the thickness of the depletion region is changed by the source-body voltage, and when the source-body voltage becomes a positive voltage, a forward bias is applied to the P-N junction and the depletion region decreases. This helps the channel formation. On the other hand, if the source-body voltage becomes a negative voltage, the depletion region increases and this interferes with

channel formation. In conclusion, when a forward voltage is applied, the threshold voltage decreases and the amount of current increases, but when a reverse bias is applied, the threshold voltage increases and the amount current decreases. However, if a voltage that is too large for the operation of the parasitic P-N diode, a large leakage current can bring about a power loss and circuit breakdown. Therefore, a proper value that gives a small threshold voltage while minimizing leakage current must be found.

2. Adaptive Threshold Voltage Technique In this paper, a forward body bias is applied to the p-

channel transistor to lower the transistor Vth and reduce transistor size. The forward body biasing scheme is favorable because it reduces transistor size at the same Vth. But a strong body bias voltage activates parasitic devices such as the bipolar transistor and p-n junction diode in MOSFETs [2]. So, a forward body bias voltage is limited to certain value to prevent the operation of parasitic devices and to provide stable operation. An appropriate forward bias must be defined to achieve a design that prevents the operation of parasitic devices and gives a leakage current value that is insensitive to power consumption. To determine the forward bias voltage in this paper, the transistor operation was checked and analyzed through the variation of forward body voltage. As shown in Fig. 2(a), an PMOSFET transistor was used for simulation. The PMOSFET size is 20u/2u (W/L) and drain current is 10 uA. Fig. 2(b) and (c) show the graphs obtained by analyzing the IBS-VBS and VDS-VBS characteristic curves. By referring to the variation of body voltage in Fig. 2, we can find a value where the leakage current and current become the maximum. In Fig. 2(b), the leakage current sharply

Fig. 1. Body effect in PMOSFET.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, 2018 289

increases when the body bias voltage rises to 0.6 V or higher. Furthermore, in Fig. 2(c), the threshold voltage becomes the lowest when the body bias voltage is 0.7 V.

Fig. 3 shows the temperature characteristic curve. To prevent the activation of parasitic devices by temperature changes, we can check the leakage current values at changing temperatures. The PMOS Size is 20u/2u (W/L) and drain-source voltage is 3.2 V. In Fig. 3, when the body bias voltage decreases to 0.4 V or lower, the leakage current becomes insensitive to temperature changes. Through this analysis, 0.4 V was set as the body bias voltage for the design in this paper.

III. THE PROPOSED LDO REGUALTOR

The pass TR(pass transistor) provides the load current of the LDO regulation and determines the current value according to the gate voltage. What needs to be concerned when determining the size of pass TR is that it must have a suitable size to prevent the breakdown of the device when the maximum current flows to the load. Furthermore, a size that can increase efficiency and provide the maximum output voltage when an input voltage is applied to the target current must be determined. In addition, the maximum output voltage is obtained by setting the voltage drop for the target current, and the voltage difference between the two terminals of the pass TR is called ‘dropout voltage’. An important factor for increasing efficiency and deciding the maximum output voltage is the size of the pass TR. A large size offers the advantage of increasing the amount of maximum output current, but it also causes difficulty in achieving frequency stability by the gate capacitor and decreases the reaction speed to time due to a delay by the capacitor. Therefore, a forward body bias is applied to the p-channel Pass TR to reduce transistor size as well as dropout voltage.

In this paper, the adaptive threshold voltage technique was applied to two types of LDO pass TRs and the characteristics were analyzed. The dropout voltage characteristic is shown in Table 1. DC sweep analysis was used to calculate the dropout voltage under forward body bias voltage from 0 to 0.6 V. The body bias was supplied from an internal adaptive bias source and VBS was about 0.4 V. The dropout voltage (VDO) used for moderate size MPASS is about 368 mV at 150 mA load condition and the body biasing transistor's VDO is about 350 mV at same load condition. The voltage difference is 18 mV in order to achieve the same VDO. And the Pass TR can reduce its size by 5.5%, that is, the Pass TR size is 113*186(um^2) when the VDO is 350 mV [5].

1. Current-mirror in LDO Control Block

Error AMP is one of the key blocks of regulator and a

Fig. 2. The characteristics of PMOS body bias variation (a) adaptive threshold voltage technique, (b) IBS-VBS characteristic, (c) VDS-VBS characteristic.

Fig. 3. The characteristic of temperature variation.of PMOS.

Table 1. Performance summary (measurements)

Load condition = 150 mA VBS[V] 0 0.1 0.2 0.3 0.4 0.5 0.6

VDO[mV] 368 363 358 354 350 347 344


current bias was selected to provide a stable bias to the error AMP. The error AMP that uses a current bias is insensitive to current variations, so it acquires high insensitivity to variations and a high CMRR. To implement this performance, the current-mirror of the error AMP is increased or a cascode current-mirror is used. Accordingly, the transistor size of the current source increases for stable operation, and the greater the number of current mirrors, the greater the circuit area becomes and it gets more difficult to add many circuits to the IC. Therefore, in this paper, the adaptive threshold voltage technique was applied to the current mirror of the error AMP. When a forward bias voltage is applied to the body, the amount of current increases by the body effect, and this was used to decrease the transistor size and the overall area. Fig. 4(a) shows a schematic of the proposed current mirror. The current sources used by the error AMP are MP1- MP8. MP1 and MP2 receive the reference bias current source and copy it to the current mirrors in MP3 – MP8. To apply the adaptive threshold voltage technique, a voltage to be applied to the body terminal of the transistor must be generated.

Diode-connected n-MOSFET transistors Mb1, Mb2 are used to generate the body bias voltages (Vpb1, Vpb2) of the cascode current mirror in Fig. 4(a). Mb1 and Mb2 provide the moderate voltage through connection between drain and gate. In other words, the body biasing circuit consumes the leakage current because the input resistance in the MOSFET is essentially infinite. In addition, the use of the cascade current mirrors increases the output resistance and makes the current insensitive to supply-voltage variations [4-7].

It is shown the output resistance and the layout area compared with the conventional current mirror in Fig. 4(b) and (c). The current mirror which were not applied with the adaptive threshold voltage technique occupied an area of 81*52 (um2) and the output resistance was about 700 MΩ. The proposed current mirrors, which were applied the adaptive threshold voltage technique.

Occupied an area of 63*26 (um2) and the output resistance was about 670 MΩ. The output resistances exhibited similar characteristics for supply-voltage variations. Therefore, the proposed current mirror can save chip area by about 61% compared with the conventional current mirror [6, 7].

2. The Proposed LDO Block

Fig. 5 shows a schematic diagram of the LDO

proposed in this paper. Fig. 5(a) shows a schematic diagram of the error AMP, and Fig. 5(b) shows a schematic diagram of the voltage buffer and pass TR. The current-mirror of the error AMP and voltage buffer consist of PMOSFET. In previous work [6], the body bias technique was used, which applies a separate voltage to the body terminal of the PMOSFET used in the current-mirror and the pass TR. For the LDO proposed in this paper, however, four case of LDO were compared to verify the effect of the adaptive threshold voltage technique applied to the parts of LDO. To these four

Table 2. Type of LDO Regulator

Body Bias apply Type 1 Basic LDO Regulator Type 2 Error AMP & Voltage Buffer Type3 Pass Transistor Type4 Error AMP & Voltage Buffer & Pass TR

(b) (c)

Fig. 4. The proposed current-mirror (a) schematic, (b) Output impedance, (c) layout.


types of LDOs, the adaptive threshold voltage technique was applied in phases. The type1 is the most basic LDO. For the type2, the adaptive threshold voltage technique was applied to the error AMP and voltage buffer to decrease the areas of the error AMP and voltage buffer while maintaining the characteristics. For the type3, the adaptive threshold voltage technique was applied to the pass TR to decrease the size of the pass TR and improve the regulation characteristic of the LDO. For the type4, the adaptive threshold voltage technique was applied to the error AMP, the voltage buffer, and the pass TR to decrease the area of the LDO and improve the regulation characteristic. In this paper, the performances of these four types of LDOs were comparatively analyzed and the effect of the adaptive threshold voltage technique was verified.

3. The Proposed LDO Block

Fig. 6 shows the loop gain characteristics of the four

types of LDOs. The AC simulation was performed for identifying effect on stability for adaptive threshold voltage technique. Fig. 6(a) and (b) are the AC simulation result of the type1 and type2. At full load condition, the loop gain is 75 dB and the phase margin is 80°. It confirms that the stability is maintained even if adaptive threshold voltage technique is applied to error amplifier. Fig. 6(c) is the AC simulation result of the

type3. At full load condition, the loop gain is 75dB and the phase margin is 88°. The reason is that the gate capacitance of the pass transistor becomes smaller and the second pole is pushed to high frequency. Also, Fig. 6(d) is the AC simulation result of the type4. At full load condition, the loop gain is 75 dB and the phase margin is 88°. It confirms that the stability is maintained even if adaptive threshold voltage technique is applied to error amplifier, voltage buffer and Pass transistor. Also the gate capacitance of the pass transistor becomes smaller. As a result, LDO regulator with adaptive threshold voltage technique has system stability same as conventional LDO regulator. The output capacitance of all LDO Regulator is 4.7 uF.

IV. MEASUREMENT RESULTS

The proposed IC is fabricated in 0.18um BCD process. The manufactured IC was verified and analyzed for its performance and characteristics by using probe-station and measurement equipment. We measured line regulation, load regulation, line transient response. Proposed LDO was manufactured and characterized

Fig. 5. The circuit diagram for the proposed LDO Regulator.

Fig. 6. Frequency responses under full-load (a) Type1, (b) Type2, (c) Type3, (d) Type4.


based on the results of previous work [1]. Input voltage range was 2.7 ~ 5 V, load condition range 0 ~ 110 mA and quiescent current 68uA. An output capacitor of 2.2 uF with 1~300 mΩ equivalent series resistance (ESR) was used for simulation to obtain stability under various load conditions. Fig. 7 appear to comparison of layout.

1. Layout

The layout is compared with conventional and

proposed LDO Regulator in Fig. 6. The effective die area of the conventional LDO Regulator Type1 is 84,000 (um^2) not including the testing pads and bias blocks. The area of the proposed LDO Regulator Type2 is 75,000 (um^2). The area of the proposed LDO Regulator Type3 is 62,200 (um^2). The area of the proposed LDO Regulator is 59,000 (um^2) so that can reduce the area compared with conventional LDO Regulator.

2. Measurement Results

Four types of LDO regulators were fabricated to verify

the effect of the adaptive threshold voltage technique in this paper. The adaptive threshold voltage technique was applied to these four types of LDOs in phases. The manufactured IC was measured for line regulation, load regulation and line transient response.

Fig. 8 shows the load regulation measurement results of the four types of LDOs. A comparison of (a) and (b) in Fig. 8 reveals that the regulation characteristics are almost identical up to 70 mA. Furthermore, a comparison

of (a) and (c) in Fig. 8 reveals that the application of the adaptive threshold voltage technique to the pass TR provided more stable output voltages under heavy loads.

Fig. 9 shows the line regulation measurement results of the fore types of LDOs. Output voltage was measured with variation of input voltage from 2.5 V ~ 4 V. The measurement results confirm that applying the adaptive threshold voltage technique to the pass TR improved the regulation characteristics which resulted in a shorter time to normal operation.

Fig. 10 shows the line transient response measurement results of the four types of LDOs. For the measurement of line transient response, the changes in output voltage

Fig. 7. Comparison of layout.

Fig. 8. Measurement results of Load regulation (a) Type1, (b) Type2, (c) Type3, (d) Type4.

Fig. 9. Measurement results of Line regulation (a) Type1, (b) Type2, (c) Type3, (d) Type4.


when the input voltage was quickly increased from 2.7 V to 3.5 V and then quickly decreased from 3.5 V to 2.7 V were measured. The output voltage change rates of (a) and (b) in Fig. 10 are almost identical at around 90 mV. The output voltage change rates of (a) and (b) in Fig. 10 are around 25 mV. This confirms that the application of the adaptive threshold voltage technique to the pass TR improved the current driving capacity and decreased the changes in output voltage compared to the LDO to which the adaptive threshold voltage technique was not applied.

Fig. 11 shows the temperature measurement results of the four types of LDOs. Measurements were performed from -40°C to 150°C. It confirms that the stability about temperature is maintained even if adaptive threshold voltage technique is applied to error amplifier, voltage buffer and Pass transistor.

Table 2 shows the specifications of the four LDO regulators that were fabricated in this paper. In the line

regulation(VDD : 2.8~5 V), type1 and type2 show stable state since 3.2 V. In the load regulation(Iload : 1~ 100 mA), type1 and type2 show unstable state since 70 mA.

V. CONCLUSIONS

In this paper, the adaptive threshold voltage technique was applied to four LDOs in phases and the characteristics and areas of the LDOs were comparatively analyzed. For comparison of high-reliability, four types of LDOs were designed and fabricated by applying the adaptive threshold voltage technique to the error AMP, the voltage buffer, and the pass TR in phases, which are the internal blocks of LDO. When the adaptive threshold voltage technique was applied to the error AMP and voltage buffer, the LDO showed the same performance in the normal operation range as the conventional LDO and about 61% of area reduction in the current-mirror was achieved. When the adaptive threshold voltage technique was applied to the pass TR, the LDO provided a more stable output voltage against the variations of load current and input voltage and entered into the normal state faster due to improved regulation characteristics. In terms of line regulation, the LDO was activated at a lower VDD due to the drop-out voltage. In terms of load regulation, the LDO operated normally at a higher load current due to the improved current driving capacity. Furthermore, the area of the pass TR decreased by about 5.5%.

Fig. 10. Measurement results of Line transient response (a) Type1, (b) Type2, (c) Type3, (d) Type4.

Fig. 11. Measurement results of temperature.

Table 2. The spec. of the 4 LDOs(0.18 um BCD Process)

Type1 Type2 Type3 Type4 Supply voltage[V] 3 to 5

Storage temperature range[℃] -40 to 125

Drop-out voltage[mV] 350 Starting point for a stable

line regulation[V] 3.2 3.2 2.8 2.8

Line regulation[mV] (VDD : 3.2~5 V) 5 8 2 6

Line regulation[mV] (VDD : 2.8~5 V) - - 8 10

Ending point for a stable load regulation[mA] 70 70 110 110

Load regulation[mV] (Iload : 1~70 mA) 17 18 11 13

Load regulation[mV] (Iload : 1~100 mA) - - 14 18


ACKNOWLEDGMENTS

This work was supported by the Ministry of Trade, Industry & Energy (10065137, “Boosted Class-DG Audio Power Amplifier with Embedded ADC for Mobile Speaker Protection”) and by Institute for Information & communications Technology Promotion(IITP) grant funded by the Korea government(MSIP) (No.B0186-15-1001, Form factor-free Multi Input and output Power Module Technology for Wearable Devices)

REFERENCES

[1] SuVolta Corp., “Body Effect And Body Biasing”, Technology Brief.

[2] Rui He; Lihong Zhang, “Evaluation of modern MOSFET models for bulk-driven applications,” Circuits and Systems, 2008. MWSCAS 2008. 51st

[3] P. R. Gray; R. G. Meyer, "Analysis and Design of Analog Integrated Circuits," New York, John Wiley & Sons, Inc., 1993.

[4] Li Yanio; Yang Yintang, “A novenl low-voltage low-power bulk-driven cascade current mirror”, ICACTE 2010, vol. 3, pp. 78-83, Aug. 2010

[5] Carrillo, J. M; Duque-Carrillo, J. F, “Design considerations on CMOS bulk-driven differential input stages”, SMACD 2012, pp. 85-88, Sept. 2012.

[6] Yong-Seo Koo, “A Design of Low-area low dropout regulator using body bias technique”, IEICE Electronics Express, vol. 10, no. 19, pp. 20130300, Oct. 2013.

[7] Kyunghwan Kim; Wonsuk Park; Dongsu Kim; Junsoo Park; Bobae Song; Yongseo Koo, “Low- dropout regulator using adaptive threshold voltage technique”, TENCON 2012, pp. 1-5, Nov.

Kyeoung-Hyeon Park was born in Hwaseong, Republic of Korea, in 1990. He received his B.S. in Electronic Engineering from Seo- Kyeong University, Seoul, Republic of Korea in 2015. He joined the Department of Electronics and

Electrical Engineering in Dankook university as a Master's course in 2015. His current research interests include high-efficiency power management circuit (PMICs), such as DC-DC converter and Low Drop-Out regulator.

Yil-Suk Yang received his BS, MS, and PhD from the School of Electrical Engineering & Computer Science at Kyungpook National University, Daegu, Rep. of Korea, in 1989, 1994, and 2008, respectively. Before joining ETRI, Daejeon, Rep.

of Korea, in 1999, he was with LG Semiconductor. Since 1999, he has worked in the ETRI Basic Research Laboratory, where he has been engaged in research of low power circuit design, high energy efficiency circuit design, and power electronics design.

Yong-Seo Koo was born in Seoul, Republic of Korea, in 1957. He received his B.S., M.S. and Ph.D. degree in Electronics Engineering from Sogang University, Seoul, Republic of Korea, in 1981, 1983 and 1992, respectively. He joined the

Department of Electronics and Electrical Engineering, Dankook University as a Professor, in 2009. His current research interests include semiconductor device, such as power BJTs, LDMOSs, and IGBTs, high-efficiency power management integrated circuit(PMICs), such as DC-DC converter and electrostatic discharge(ESD) protection circuit design.

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