ultra low power low dropout voltage regulator

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1072 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013 A 0.9- A Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS Sau Siong Chong, Student Member, IEEE, and Pak Kwong Chan, Senior Member, IEEE Abstract—An ultra-low quiescent current output-capacitorless low-dropout (OCL-LDO) regulator with adaptive power transis- tors technique is presented in this paper. The proposed technique permits the regulator to transform itself between 2-stage and 3-stage cascaded topologies with respective power transistor, depending on the load current condition. As such, it enables the OCL-LDO regulator to achieve ultra-low power consumption, high stability and good transient response without the need of off-chip capacitor at the output. The proposed LDO regulator has been implemented and fabricated in a UMC 65-nm CMOS process. It occupies an active area of 0.017 mm . The measured results have shown that the proposed circuit consumes a quiescent current of 0.9 A at no load, regulating the output at 1 V from a voltage supply of 1.2 V. It achieves full range stability from 0 to 100 mA load current at a maximum 100 pF parasitic capacitance load. The measured transient output voltage is 68.8 mV when load current is stepped from 0 to 100 mA in 300 ns with pF. The recovery time is about 6 s. Compared to previously reported counterparts, the proposed OCL-LDO regulator shows a signi- cant improvement in term of OCL-LDO transient gure-of-merit (FOM) as well as balanced performance parameters in terms of PSR, line regulation and load regulation. Index Terms—LDO regulator, output-capacitorless LDO regu- lator, OCL-LDO regulator, ultra-low quiescent LDO, multi gain stage LDO. I. INTRODUCTION M ODERN development of power management unit for on-chip applications requires many voltage regulators to power-up each component and functional block [1]. A low-dropout (LDO) regulator is an ideal choice, especially for high performance and sensitive analog/mixed-signal blocks. Normally, the conventional LDO regulator relies on a bulky off-chip capacitor in the range of F to maintain a stable op- eration [2]–[6]. However, the large off-chip capacitor may not be favorable for on-chip applications that embed many voltage regulators. This motivates the use of embedded output-capaci- torless LDO (OCL-LDO) regulators in the on-chip applications. With OCL-LDO regulators, the resistive and inductive parasitic Manuscript received April 24, 2012; revised June 28, 2012; accepted July 27, 2012. Date of publication September 07, 2012; date of current version March 23, 2013. This paper was recommended by Associate Editor M. Ortmanns. The authors are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: chon0157@e. ntu.edu.sg; [email protected]). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TCSI.2012.2215392 effects due to the external connection and the huge number of I/O pads on the chip can be eliminated. Furthermore, the printed-circuit-board layout area can be minimized [7]. This raises the interest in developing the OCL-LDO regulators. For portable electronic devices such as mobile phones and PDAs, low power consumption is a very critical requirement to extend the battery life. Thus, low voltage and low quiescent current are the most desirable parameters to achieve high battery efciency for power saving purpose. However, the OCL-LDO regulators suffer from the exiting tradeoff problem between power consumption against other important design parameters such as loop stability and transient response perfor- mance metrics. OCL-LDO regulators have been recently reported in [7]–[17]. In [8], an ultra-fast-transient regulator implemented in 90 nm CMOS with an on-chip capacitor of 0.6 nF con- sumes signicant high quiescent current of 6 mA, which is not suitable for low power design. Although the LDO regulator [9] implemented in a 2-stage structure is ease in frequency compensation, it comes at the price of not having high loop gain. In [10], an efcient multistage LDO regulator using an active-feedback frequency compensation approach is proposed. Its operating supply voltage needs to be increased to cater for the cascode structure in the slew rate enhancement circuit. Further architecture is the use of ipped-voltage-follower (FVF) based designs [7], [11], [12]. Due to the simple folded structure, the LDO regulators in [11] and [12] can be made stable easily in exchange of low loop gain. As a result, the load regulation is affected. When extended to the gain-enhanced structure [7] for load regulation improvement, it demands a minimum load current of 3 mA to maintain stability despite it consumes a quiescent current of 8 A. The minimum load cur- rent operation limits the exibility for applications that require light load currents. Furthermore, the value of minimum load current depends on the size of output load capacitor. A higher minimum load current is often needed when the OCL-LDO regulator drives a capacitive load larger than 50 pF. Similarly, the proposed designs in [13] and [14] demanding a minimum load current which makes it unattractive in the light load case. This is mainly because when load current is low, the non-domi- nant complex poles, having a large Q factor, cause a magnitude peaking near the unity gain frequency in a multistage structure. Ultra low quiescent current design techniques are proposed in [15] and [16]. Although LDO regulator in [15] consumes only 103 nA (the biasing current for the power transistor is not included), it has been reported to have a settling time of 400 s. 1549-8328/$31.00 © 2012 IEEE

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ultra low power low dropout voltage regulator

Transcript of ultra low power low dropout voltage regulator

Page 1: ultra low power low dropout voltage regulator

1072 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

A 0.9- A Quiescent Current Output-CapacitorlessLDO Regulator With Adaptive Power

Transistors in 65-nm CMOSSau Siong Chong, Student Member, IEEE, and Pak Kwong Chan, Senior Member, IEEE

Abstract—An ultra-low quiescent current output-capacitorlesslow-dropout (OCL-LDO) regulator with adaptive power transis-tors technique is presented in this paper. The proposed techniquepermits the regulator to transform itself between 2-stage and3-stage cascaded topologies with respective power transistor,depending on the load current condition. As such, it enables theOCL-LDO regulator to achieve ultra-low power consumption,high stability and good transient response without the need ofoff-chip capacitor at the output. The proposed LDO regulatorhas been implemented and fabricated in a UMC 65-nm CMOSprocess. It occupies an active area of 0.017 mm . The measuredresults have shown that the proposed circuit consumes a quiescentcurrent of 0.9 A at no load, regulating the output at 1 V from avoltage supply of 1.2 V. It achieves full range stability from 0 to100 mA load current at a maximum 100 pF parasitic capacitanceload. The measured transient output voltage is 68.8 mV when loadcurrent is stepped from 0 to 100 mA in 300 ns with pF.The recovery time is about 6 s. Compared to previously reportedcounterparts, the proposed OCL-LDO regulator shows a signifi-cant improvement in term of OCL-LDO transient figure-of-merit(FOM) as well as balanced performance parameters in terms ofPSR, line regulation and load regulation.

Index Terms—LDO regulator, output-capacitorless LDO regu-lator, OCL-LDO regulator, ultra-low quiescent LDO, multi gainstage LDO.

I. INTRODUCTION

M ODERN development of power management unit foron-chip applications requires many voltage regulators

to power-up each component and functional block [1]. Alow-dropout (LDO) regulator is an ideal choice, especially forhigh performance and sensitive analog/mixed-signal blocks.Normally, the conventional LDO regulator relies on a bulkyoff-chip capacitor in the range of F to maintain a stable op-eration [2]–[6]. However, the large off-chip capacitor may notbe favorable for on-chip applications that embed many voltageregulators. This motivates the use of embedded output-capaci-torless LDO (OCL-LDO) regulators in the on-chip applications.With OCL-LDO regulators, the resistive and inductive parasitic

Manuscript received April 24, 2012; revised June 28, 2012; accepted July 27,2012. Date of publication September 07, 2012; date of current version March23, 2013. This paper was recommended by Associate Editor M. Ortmanns.The authors are with the School of Electrical and Electronic Engineering,

Nanyang Technological University, Singapore 639798 (e-mail: [email protected]; [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSI.2012.2215392

effects due to the external connection and the huge numberof I/O pads on the chip can be eliminated. Furthermore, theprinted-circuit-board layout area can be minimized [7]. Thisraises the interest in developing the OCL-LDO regulators.For portable electronic devices such as mobile phones and

PDAs, low power consumption is a very critical requirementto extend the battery life. Thus, low voltage and low quiescentcurrent are the most desirable parameters to achieve highbattery efficiency for power saving purpose. However, theOCL-LDO regulators suffer from the exiting tradeoff problembetween power consumption against other important designparameters such as loop stability and transient response perfor-mance metrics.OCL-LDO regulators have been recently reported in

[7]–[17]. In [8], an ultra-fast-transient regulator implementedin 90 nm CMOS with an on-chip capacitor of 0.6 nF con-sumes significant high quiescent current of 6 mA, which is notsuitable for low power design. Although the LDO regulator[9] implemented in a 2-stage structure is ease in frequencycompensation, it comes at the price of not having high loopgain. In [10], an efficient multistage LDO regulator using anactive-feedback frequency compensation approach is proposed.Its operating supply voltage needs to be increased to cater forthe cascode structure in the slew rate enhancement circuit.Further architecture is the use of flipped-voltage-follower(FVF) based designs [7], [11], [12]. Due to the simple foldedstructure, the LDO regulators in [11] and [12] can be madestable easily in exchange of low loop gain. As a result, the loadregulation is affected. When extended to the gain-enhancedstructure [7] for load regulation improvement, it demands aminimum load current of 3 mA to maintain stability despite itconsumes a quiescent current of 8 A. The minimum load cur-rent operation limits the flexibility for applications that requirelight load currents. Furthermore, the value of minimum loadcurrent depends on the size of output load capacitor. A higherminimum load current is often needed when the OCL-LDOregulator drives a capacitive load larger than 50 pF. Similarly,the proposed designs in [13] and [14] demanding a minimumload current which makes it unattractive in the light load case.This is mainly because when load current is low, the non-domi-nant complex poles, having a large Q factor, cause a magnitudepeaking near the unity gain frequency in a multistage structure.Ultra low quiescent current design techniques are proposedin [15] and [16]. Although LDO regulator in [15] consumesonly 103 nA (the biasing current for the power transistor is notincluded), it has been reported to have a settling time of 400 s.

1549-8328/$31.00 © 2012 IEEE

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CHONG AND CHAN: QUIESCENT CURRENT OUTPUT-CAPACITORLESS LDO REGULATOR 1073

Fig. 1. Structure of the proposed LDO regulator.

In [16], the design displays a faster settling time but it suffersfrom the larger undershoot and overshoot which may not meetthe specific demand in some applications. Therefore, it is verychallenging to design an ultra-low quiescent current and fasttransient response OCL-LDO regulator without requiring theminimum load current due to additional gain stage(s) in amultistage circuit topology.This paper presents an ultra-low quiescent current OCL-LDO

regulator using an adaptive power transistors technique in65-nm CMOS process. The proposed technique allows the reg-ulator to transform itself from a 2-stage structure to a 3-stagestructure OCL-LDO regulator when a larger load current isdrawn. In addition, it offers an ultra-low quiescent currentsolution for OCL-LDO regulator at no load whilst achievingstability across the whole load current range. Section II dis-cusses the structure as well as the stability analysis of theproposed OCL-LDO regulator. Section III describes the detailsof the circuit implementation of the proposed structure. Theexperimental results, discussions and performance comparisonare given in Section IV. Finally, the conclusion is drawn inSection V.

II. PROPOSED ARCHITECTURE

A. Topology

Fig. 1 shows the proposed regulator architecture. It comprisesa dynamic-biased error amplifier as 1st gain stage, a non-in-verting amplifier as 2nd gain stage, a main power transistor

, a sub-power transistor , an overshoot reduction cir-cuitry, a frequency compensation network and a feedback net-work. In the proposed structure, the main power transistoris adaptively turned on or off, depending on the loading currentcondition.At light load condition, the 2nd gain stage is working in triode

region and the main power transistor is turned off. The proposedregulator can be viewed as a 2-stage structure when the loadcurrent is less than the defined threshold current . Besides,in order to achieve ultra-low quiescent current and improve thecurrent efficiency at light loads, the dynamic biasing technique[4] is added to the 1st gain stage. The dynamic biasing techniqueis achieved by making the biasing current proportionalto the current in sub-power transistor . It should be noted

that the biasing current stop increasing after the main powertransistor is activated.When the load current increases above , the proposed

regulator transforms itself into a 3-stage structure. Due to thehigher transconductance and reduced effective output resistancearising from the load current, the pole at the output of regulatoris shifted to high frequency. The proposed regulator remainsstable with the structural transformation. Furthermore, it elimi-nates the minimum loading current and stability problems in amultistage structure. Therefore, it has the feature of ultra-lowquiescent current at no load current condition.

B. Stability Analysis

The stability of the whole system is achieved by cascodecompensation technique. Cascode compensation is adopted inthis design because it offers higher current-bandwidth efficiencywhen compared to the Miller compensation technique [18]. Notonly does it improve stability by removing the right-hand-planezero, it enhances power-supply rejection (PSR) [18]–[20]. Toanalyze the stability of the proposed OCL-LDO regulator, thesmall-signal transfer function is investigated. Due to the struc-tural transformation, the stability of the proposed OCL-LDOregulator will be discussed on the basis of 2-stage and 3-stagestructure as shown in Fig. 2. It is noted that is defined as thetransconductance of the respective device whereas anddenote the respective lumped output parasitic capacitance andoutput resistance of each node. The feedback factor, , is 1/2 inthis design. The transfer function is derived using the followingassumptions: (i) the input resistance of the feedback transcon-ductance stage, , is equal to the reciprocal of its transcon-ductance, (ii) the gain of 1st stage and 2nd stage are much largerthan 1 and (iii) the capacitances and are muchsmaller than .Case I ( -Stage Structure): When

, the 2nd gain stage is operating in trioderegion and the main power transistor is deactivated.Hence, they can be ignored in the analysis. Fig. 2(a)shows the simplified small-signal model of the proposedOCL-LDO regulator in a 2-stage configuration. The effec-tive output resistance for 2-stage structure is defined by

, where andis output resistance of sub-power transistor, feedback

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1074 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

Fig. 2. Small-signal modeling. (a) 2-stage and (b) 3-stage configuration.

network resistance and load resistance, respectively. In gen-eral, is large, when the load current is small. Thederived transfer function is shown as follows:

(1)

where is the low frequency gain and is dominantpole. They are given as

(2)

(3)

Hence, the GBW can be obtained as

(4)

As shown in (1), the non-dominant poles and zero can beexpressed by

(5)

(6)

(7)

Fig. 3 shows the relative position of poles and zero. It can beobserved that and cancel each other. The dominant poleat the output of error amplifier is the only pole locates withinthe unity-gain bandwidth. Hence, the loop stability solely de-pends on the location of . Due to cascode compensation,is pushed to higher frequencies by a cascode factor of .

Fig. 3. Loop gain (magnitude plot not in scale) of the proposed LDO regulator.

Furthermore, is proportional to , which is proportionalto square-root of the load current. Therefore, the worst casestability happens at no load condition. As the load current in-creases, moves to higher frequencies. As a result, the phasemargin is enhanced.Case II ( -Stage Structure): The simpli-

fied small-signal model of the proposed OCL-LDO regulatorin the transformed 3-stage structure is depicted in Fig. 2(b).Since the 2nd gain stage andmain power transistor are activated,they are included in the stability analysis. The overall struc-ture can be viewed as a 3-stage amplifier. The effective outputresistance for 3-stage structure is defined by

, where andis the output resistance of sub-power transistor, main

power transistor, feedback network resistance and load resis-tance, respectively. is small because it is greatlyaffected by load current and dominated by theload resistance, . The simplified transfer function of thetransformed structure is shown in (8) at the bottom of the page.

(8)

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CHONG AND CHAN: QUIESCENT CURRENT OUTPUT-CAPACITORLESS LDO REGULATOR 1075

The low frequency gain and dominant pole are re-spectively given by

(9)

(10)

The expression of the GBW remains the same. However, theGBW is extended when compared to light load condition. It isbecause is enhanced due to the dynamic biasing scheme.From the transfer function (8), the non-dominant complex polesand the corresponding Q factor can then be determined as

(11)

(12)

From (11) and (12), both and Q factor depend on the pa-rameters and that control the stability ofthe regulator. It can be observed that are parasitic relatedpoles which can be located at high frequencies easily. From(12), it suggests that the Q factor is inversely proportional to

. The largest Q factor happens at full load currentwhere the is the minimum. To avoid peaking effectarising from high Q factor, a larger and or a smaller

can be used. In general, it is preferred to choose a largerbecause it pushes the to a higher frequencies as well.

The location of fourth pole is obtained as

(13)

As indicated in (13), the pole depends on the output capac-itance and output resistance. The effective output resistance isinversely proportional to the output load current which will pushthe pole to higher frequencies as the load current increases.On the other hand, there are also two zeros in the system.

They can be derived as follows:

(14)

(15)

The relative poles and zeros position when isillustrated in Fig. 3. The zero is placed slightly beyond theGBW to enhance the phase margin when transconductanceis designed to be slightly larger than transconductance . Thezero occurs at very high frequencywhich is evenmuch higherthan that of the fourth pole. As such, its effects can be neglected.Table I summaries the poles and zeros locations withpF in 2-stage and 3-stage configuration.Fig. 4 shows the simulated loop gain response of the pro-

posed regulator at different load current conditions. At no loadcurrent, the regulator achieves a minimum phase margin of 53with a low frequency loop gain of 40 dB. When load currentraises, the loop gain increases to around 100 dB. The regulatorachieves a gain bandwidth product GBW of about 9 MHz with a

TABLE IPOLES AND ZEROS LOCATION WITH PF

phase margin of 80 when load current is larger than 1 mA dueto dynamically increase in the bias currents. Fig. 5 shows thesimulated phase margin as a function of load current. Similar toprevious works [7], [9], the worst case stability happens when

is at its minimum and is at its maximum. Therefore,it can conclude that the stability of the regulator over the fullrange is ensured as long as is less than 100 pF.

III. CIRCUIT IMPLEMENTATION OF PROPOSEDLDO REGULATOR

A. Schematic

Fig. 6 depicts the simplified schematic of the proposed reg-ulator. The error amplifier is realized by a single folded-cas-code stage with transistor - . The dynamic biasing net-work which is formed by transistors - is added to im-prove the bandwidth of the ODC-LDO regulator under mod-erate load conditions. The non-inverting 2nd gain stage is re-alized by transistors - . Transistors and aresub-power and main power transistor, respectively. The tran-sistor size of and is 120 m/60 nm and 1800 m/60nm, respectively. The feedback network is realized by a stringof diode-connected PMOS transistors - biased in thesubthreshold region to minimize quiescent current as well as thesilicon area [21]. In ultra-low power design, the silicon area willbe much larger if the feedback network is realized by conven-tional approach using passive resistors. Finally, the load currentis modeled as a resistor in parallel with a parasitic ca-pacitor . The quiescent current distribution whenis indicated in Fig. 6. The dynamic current sources can be ig-nored as they are very small when compared to the static cur-rent source at no load condition. The targeted quiescent currentis about 0.5 A for the core circuit.Start-up circuit and bias current generator for the proposed

design are shown in Fig. 7. Transistors - and resistorform a supply-independent current generator to provide a

constant biasing to the proposed circuit. A capacitive-coupledstart-up circuit [22] is adopted because it consumes no staticpower. The tradeoff of this scheme is that the start-up capacitorsoccupy extra silicon area. The bias current generator consumes0.3 A.Since all the load current is supplied by sub-power transistorwhen the system operates in 2-stage mode, the transistorin the dynamic biasing network is used to copy the current

from [4]. A gate voltage that varies according to theload current is obtained. As a result, the biasing current of the 1st

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1076 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

Fig. 4. Simulated open-loop gain at different load currents with pF.

Fig. 5. Phase margin as a function of load currents.

gain stage can be increased accordingly. The dynamic biasingnetwork stops increasing the biasing current of 1st gain stagewhen the system transforms into 3-stage mode. It is because theexcess current is now supplied by main power transistor .Therefore, the amount of current flowing through is moreor less fixed.Both the sub-power transistor and 2nd gain stage tran-

sistor are driven by the output voltage of the dynamic-biased1st gain stage at node . They can be viewed as a pair of cur-rent mirror having a current ratio of 1: M.When the load currentis low, the current /M. The transistor is biased

to source a current of . When , the transistoris forced to operate in the triode region. As such, the node

potential at is pulled up close to potential that turnsthe main power transistor off. The pole at node is thuslocated at high frequency despite of the parasitic capacitancesarising from the gate of . Hence, stable operation is guaran-teed. When the load current increases gradually at the transitionbias point where , the transistor

moves out of triode region and starts operating in satura-tion region. At this juncture, the proposed regulator transformsitself into the 3-stage structure. The 2nd gain stage is activatedand the main power transistor starts conducting and supplyingthe extra required load. The available amount of loop gain in-creases substantially due to extra gain stage. The threshold cur-rent is defined by M, N and . The valueof , M and N is 100 nA, 67 and 125, respectively. The cal-culated is about 837.5 A. However, the simulated isaround 200 A. The difference is due to the combined effectof reverse short-channel effect (RSCE) [23], [24] and channellength modulation. In this design, the channel length of the tran-sistor and is 60 nm (60 nm is allowed by the foundryand stated in the design rule) and 500 nm respectively. The ex-tracted threshold voltage of sub-power transistor is 78 mVlarger than transistor . Therefore, for a given , the nor-malized current driving capability of transistor is larger thanthat of sub-power transistor . Temperature and corner sim-ulations have been conducted to confirm the stability of the pro-posed LDO regulator. Despite of that, the early activation ofmain power transistor would not affect the operation and per-formance of the proposed scheme.

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CHONG AND CHAN: QUIESCENT CURRENT OUTPUT-CAPACITORLESS LDO REGULATOR 1077

Fig. 6. Schematic of the proposed LDO regulator.

Fig. 7. Schematic of bias generator and start-up circuit.

Fig. 8. Simulated load transient response.

B. Overshoot and Undershoot Reduction

In general, undershoot and overshoot of the OCL-LDO regu-lators is larger when compared to the conventional LDO regula-

Fig. 9. Layout and chip micrograph.

tors with a large output capacitor. In this design, the undershootis reduced by employing the dynamic biasing technique intro-duced in [25]. It has been demonstrated in [25] that dynamicbiasing technique yields a smaller undershoot when comparedto the fixed biasing counterpart. It is because the amount of cur-rent that can be used to discharge the parasitic capacitance atthe gate of both power transistors is larger. In fact, the dynamicbiasing technique helps to reduce the overshoot too. However,the diode-connected feedback network PMOS, which is biasedin the subthreshold region, is the only path to discharge the extracurrent when is switched from full load to no load. Theovershoot appears at the output takes a longer time to dischargeand recover in transient condition. To suppress the overshoot, aresistor , a capacitor and a transistor form an over-shoot reduction network. is a pseudo-resistor realized by a

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1078 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

Fig. 10. Measured load transient response with V and V (a) mA (b) pF, mA,(c) mA (d) pF, mA.

PMOS transistor biased in the cut-off region whereas is a3 pF MOS capacitor which is realized by a high-voltage na-tive device to save silicon area and prevent the leakage cur-rent. This proposed overshoot reduction network is similar tothe RC circuits proposed in [5]. However, the overshoot reduc-tion network in our design is directly applied at the output ofthe LDO regulator which is similar to the amplifier design in[26]. In steady state, the current is around 100 nA. Whenthe output load current is switched from heavy to light load,couples the effect to the gate of and it momentarily in-

creases the discharging current from to ground. As aresult, the overshoot is suppressed and the transient response isimproved. Fig. 8 shows the simulated results of the proposedLDO regulator with and without overshoot reduction. It can beseen that the overshoot is reduced greatly from 93 mV to almostno overshoot. It is worth noting that the small-signal frequencyresponse will not be affected by the proposed overshoot reduc-tion circuitry as is much smaller than .

IV. EXPERIMENTAL RESULTS AND DISCUSSIONS

The proposed OCL-LDO regulator was designed and fabri-cated in a UMC 65-nm low-leakage CMOS technology. Thelayout and microphotograph of the proposed OCL-LDO regu-lator is shown in Fig. 9. The active area for the proposed designis about 0.017 mm (90 m 190 m). It is able to supply aload current from 0 to 100 mA with an output voltage of 1 V fora supply of 1.2 V. The dropout voltage is less than 200 mV atmaximum load current. At no load, the measured quiescent cur-rent for the proposed OCL-LDO regulator including the biasingcircuit is 0.9 A which is slightly higher than the targeted valueof 0.8 A. It is stabilized by a MOS compensation capacitorof 1.5 pF throughout the whole load current range. An externalvoltage reference of 0.5 V is used and an off-chip capacitor of100 pF is added at the output to model the for measurementpurpose. It should be noted that the system maintains stable aslong as the is less than 100 pF. It is because both (5) and

(13) suggest that the non-dominant pole is shifted to higher fre-quencies when is smaller.The measured load transient responses under different

loading conditions are shown in Fig. 10(a)–(d) to confirm thestability of the proposed LDO regulator for different testingconditions. The and are set to 1.2 V and 1 V, respec-tively when doing the load transient measurement. As shownin Fig. 10(a) and (b), the load current is switched between 0and 100 mA with a rise and fall time of 300 ns. Due to thehigh GBW contributed by the dynamic biasing scheme andthe employment of overshoot reduction circuitry, there is noobvious overshoot when load current is switched from 100 mAto 0. On the other hand, the maximum undershoot forand 100 pF is 65.1 mV and 68.8 mV, respectively. This isdue to the low quiescent current of 0.9 A at no load currentcondition. The maximum output voltage variation is less than7% (68.8 mV/1 V) and is able to settle to its final value in 6 s.Fig. 10(c) and (d) depict the measured load transient responseswhen the load current is switched from 1 mA and 10 mA to100 mA, respectively, with an edge time of 300 ns as well.It is shown that the measured undershoot is reduced to 36.9mV and 24.4 mV, respectively. The improvement is due tothe fact that the 1st gain stage has larger biasing current andthe main power transistor has been activated. The measuredload transient response confirms that the proposed OCL-LDOregulator is stable for whole range of load current.Fig. 11 shows the measured and estimated load regulation of

the proposed work. The voltage drops at high load conditionis due to the parasitic resistance of the bonding wire which isaround 250 m in our packaging. The voltage drops across thebonding wire can be as large as 25 mV when mA.In order to estimate the actual load regulation, the IR drop dueto the bonding resistance is excluded and plotted in Fig. 11 forcomparison.The line transient response is shown in Fig. 12. The supply

voltage changes between 1 V and 1.2 V in 10 s with an output

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CHONG AND CHAN: QUIESCENT CURRENT OUTPUT-CAPACITORLESS LDO REGULATOR 1079

Fig. 11. Measured and estimated load regulation with pF.

Fig. 12. Measured line transient response at and V.

voltage of 0.8 V and . The result shows that themaximum voltage spike is only 10.63 mV. It is interesting toobserve an overshoot at when is switched from 1.2V to 1 V. The overshoot is caused by the residue charges at thegate of when is switched from 1 V to 1.2 V. Fig. 13shows the measured dropout voltage across the load current.The measured result shows that the dropout voltage is less than200 mV when mA. Finally, the measured PSRat load current of 100 mA, V, V and

pF is shown in Fig. 14. The PSR is measured byusing a network analyzer (HP 4395A) and a high impedanceactive probe (HP 41800A). The proposed OCL-LDO regulatorhas achieved a PSR of dB at 10 kHz. Furthermore, a 50kHz sinusoidal waveform is applied to the input of the LDOregulator. The measured result is depicted in Fig. 15.Fig. 16 shows the measured versus . As can be

observed, keeps increasing until is about 200 Awhere the 2nd stage start working in saturation and the mainpower transistor start to conduct. It can be observed that, dueto channel length modulation effect, increases slightly after

A. At full load condition, the proposed regulatordraws a maximum current of 82.4 A and achieves a current ef-ficiency of larger than 99.9%.The measured performance of the proposed regulator is com-

pared to the state-of-the-art works in Table II. The transientfigure-of-merit (FOM) for OCL-LDO regulator in [7] is adoptedfor comparison. It is given by

(16)

Fig. 13. Dropout voltage as a function of load currents.

Fig. 14. Measured PSR at V, V and mA.

Fig. 15. Measured ripple-response at V, V andmA.

where the symbols have their usual meanings. K is the edge timeratio and defined by

(17)

The smaller FOM value, the better is the transient perfor-mance metric. The proposed design achieves the smallestOCL-LDO FOM value among the recently reported works.With the adaptive gain circuit architecture, dynamic biasing

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TABLE IIPERFORMANCE COMPARISON WITH REPORTED PRIOR-ART OCL-LDO REGULATORS

Fig. 16. Measured quiescent current as a function of load currents.

scheme and overshoot reduction circuitry, the transient per-formance at ultra-low quiescent current is comparable to thecounterparts biased at much higher quiescent values. Finally,other performance parameters such as PSR, line regulation andload regulation have achieved reasonable good values.

V. CONCLUSION

An ultra-low quiescent current OCL-LDO regulator withadaptive power transistors technique in 65-nm low-leakageCMOS process has been presented. With the proposed tech-nique and circuit architecture, the OCL-LDO regulator achievesfull range stability from 0 to 100 mA without the need of min-imum loading current requirement. In addition, it consumes

only 0.9 A at no load condition and enhances the currentefficiency at light load. At moderate and heavy loading con-dition, the performance is enhanced by additional gain stage.The proposed OCL-LDO regulator has been implemented andverified experimentally. Compared to the prior-art works, theproposed LDO regulator achieves a better quiescent current,transient performance metrics. It also offers good performanceparameters in terms of PSR, line regulation and load regulation.Finally, it also achieves the smallest transient FOM valuededicated for OCL-LDO regulator, suggesting the effectivenessof the proposed scheme. The proposed work will be useful inon-chip applications using nanometer CMOS technologies.

ACKNOWLEDGMENT

The authors would like to thank MediaTek, Singapore for thesponsorship of the chip fabrication.

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Sau Siong Chong was born in Malaysia. He re-ceived the B.Eng. (hons.) degree from NanyangTechnological University (NTU), Singapore, in2009, where he is currently working towards thePh.D. degree in School of Electrical and ElectronicEngineering.His research interests include design of analog in-

tegrated circuits and frequency compensation tech-niques for low-voltage low-power multistage ampli-fiers and low-dropout regulators.

Pak Kwong Chan was born in Hong Kong. He re-ceived the B.Sc. (hons.) degree from the Universityof Essex, Colchester, U.K., in 1987, the M.Sc. de-gree from the University of Manchester, Institute ofScience and Technology (U.M.I.S.T.), Manchester,U.K., in 1988, and the Ph.D. degree from the Uni-versity of Plymouth, U.K. in 1992.From 1989 to 1992, he was a Research Assistant

with the University of Plymouth, working in the areaof MOS continuous-time filters. In 1993, he joinedthe Institute of Microelectronics (IME), Singapore as

a Member Technical Staff, where he designed high-performance analog/mixed-signal circuits for integrated systems and CMOS sensor interfaces for industrialapplications. In 1996, He was a Staff Engineer with Motorola, Singapore wherehe developed the magnetic write channel for Motorola 1st generation hard-diskpreamplifier. He joined Nanyang Technological University (NTU), Singapore in1997, where he is an Associate Professor in the School of Electrical and Elec-tronic Engineering. He served the Program Director (analog/mixed-signal ICand applications) for the Center for Integrated Circuits and Systems (CICS) from2003 to 2010. He has also conducted numerous IC design short courses to the ICcompanies and design centers. He is the Program Manager for Advanced Tech-nology IC Shuttle Program between NTU and MediaTek, Singapore. He servesas a Guest Editor for several Special Issues on recent research topics. His re-search interests include sensor circuits and systems, mixed-mode circuits andsystems, precision analog circuits, ultra low-voltage low-power analog circuitsas well as power management IC for integrated sensors and system-on-chip.