A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2013 281

A Built-In Repair Analyzer With Optimal RepairRate for Word-Oriented Memories

Jaeyong Chung, Member, IEEE, Joonsung Park, Member, IEEE, and Jacob A. Abraham, Fellow, IEEE

Abstract—This paper presents a built-in self repair analyzerwith the optimal repair rate for memory arrays with redundancy.The proposed method requires only a single test, even in the worstcase. By performing the must-repair analysis on the fly duringthe test, it selectively stores fault addresses, and the final analysisto find a solution is performed on the stored fault addresses. Toenumerate all possible solutions, existing techniques use depthfirst search using a stack and a finite-state machine. Instead, wepropose a new algorithm and its combinational circuit implemen-tation. Since our formulation for the circuit allows us to use theparallel prefix algorithm, it can be configured in various waysto meet area and test time requirements. The total area of ourinfrastructure is dominated by the number of content addressablememory entries to store the fault addresses, and it only growsquadratically with respect to the number of repair elements.The infrastructure is also extended to support various types ofword-oriented memories.

Index Terms—Built-in self repair (BISR), memory test, redun-dancy allocation, repair analysis, spare allocation.

I. INTRODUCTION

T ODAY’S system-on-chip (SoC) environment requiressignificant changes in testing methodologies for memory

arrays. The failure of embedded memories in a SoC is more ex-pensive than that of commodity memories because a relativelylarge die is wasted. Due to the large die size and the complexfabrication process for combining memories and logic, SoCssuffer from relatively lower yield, necessitating yield opti-mization techniques [1]. At present, the area occupied by theembedded memories takes more than half of the total area of atypical SoC, and the ratio is expected to keep increasing in thefuture [2]. The defects are thus likely to affect the functionalityof the memory arrays rather than that of logic. In addition,the aggressive design rules make the memory arrays prone todefects [3]. Therefore, the overall SoC yield is dominated by

Manuscript received June 17, 2011; revised October 18, 2011; accepted De-cember 07, 2011. Date of publication January 31, 2012; date of current versionJanuary 17, 2013. This work was supported in part by Samsung Electronics Co.,Ltd.J. Chung was with the Department of Electrical and Computer Engineering,

The University of Texas, Austin, TX 78712 USA. He is now with Synopsys,Inc., Mountain View, CA 94043 USA (e-mail: [email protected]).J. Park was with the Department of Electrical and Computer Engineering, The

University of Texas, Austin, TX 78712 USA. He is nowwith Texas Instruments,Inc., Dallas, TX 75243 USA (e-mail: [email protected]).J. A. Abraham is with the Department of Electrical and Computer Engi-

neering, The University of Texas, Austin, TX 78712 USA (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TVLSI.2011.2182217

Fig. 1. Required number of CAM entries and worst-case test sessions of eachanalyzer for several redundancy configurations.

the memory yield, and optimizing the memory yield plays acrucial role in the SoC environment.To improve the yield, memory arrays are usually equipped

with spare elements, and external testers have been used to testthe memory arrays and configure the spare elements. However,in the SoC environment, the overall test time is prohibitivelyincreased if the test response data from the memory arrays aresent to the external testers. On the other hand, the SoC environ-ment, combined with shrinking technology, allows us more areafor on-chip test infrastructure at lower cost than before, whichmakes feasible a variety of built-in self test (BIST) and built-inself-repair (BISR) techniques for reducing the test time.In accordance with this trend, built-in redundancy allocation

(BIRA) approaches have been proposed as part of BISR. In [4],Kawagoe et al. propose a pioneering BIRA approach, CRESTA.They use parallel sub-analyzers, each of which evaluates a so-lution candidate. CRESTA has the sub-analyzers for all solu-tion candidates, which provides the optimal repair rate with asingle test. The sub-analyzer consists of a row content address-able memory (CAM) with entries ( is the number of repairrows) and a column CAM with entries ( is the number ofrepair columns), and CRESTA requires sub-analyzers.Since this may not be affordable in memories with many spareelements, subsequent studies have been focused on reducinghardware complexity.In [5], the authors provide a formal basis for design of BIRA

algorithms from prime repair algorithms, which correspond tothe sub-analyzers. They evaluate particular combinations of thesub-analyzers and show that the area overhead can be reducedwith slight degradation of the repair rate. In order to lower the

1063-8210/$31.00 © 2012 IEEE

282 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2013

Fig. 2. Proposed on-chip infrastructure and must repair analyzer details.

hardware complexity and still guarantee the optimal repair rate,another approach is proposed in [6] and [7]. This evaluates eachpossible solution one by one and thus does not require the par-allel sub-analyzers. Such serial implementations may increasethe overall test time, but the number of possible solutions is re-duced using the must-repair analysis. Also the hardware com-plexity for the must-repair analysis is only quadratic with re-spect to the number of repair elements. However, in this method,repeating the complete test for possible solutions may lead toa high increase in test time [8]. For existing optimal analyzers[4], [6], as well as our analyzer, Fig. 1 shows the number oftest sessions and CAM entries required for the repair analysis.The analyzers all use CAM arrays and the area is dominated bythe number of CAM entries. CRESTA consists of sub-an-alyzers, each of which has a row CAM with entries and acolumn CAM with entries. Thus the total number of CAM en-tries is . In [6], Oehler et al. use two CAMs for themust-repair analysis and each CAM has entries. Althoughthey did not mention this explicitly, additional CAM en-tries are required to store a repair solution and check if the faultsare covered by the solution.The major contributions of this paper can be summarized as

follows. Our infrastructure provides the optimal repair rate witha single test as in CRESTA and has the same requirements forthe number of CAM entries as [6]. Instead of a stack and a fi-nite-state machine (FSM) used to enumerate all possible solu-tions in [6], we propose a combinational circuit, which can beconfigured in various ways tomeet the requirements for area andtest time. For the fastest configuration, it can generate the nextsolution candidate in a single cycle. Unlike most repair analysisstudies [6], [9], [10], we show that the proposed method canwork for word-oriented memories.The rest of this paper is organized as follows. In Section II,

we introduce word-oriented repairable memories and basicterms for repair analysis. In Section III, we propose an on-chipinfrastructure for repair analysis. In Section IV, the on-chipinfrastructure is extended for word-oriented memories. InSection V, we explain in detail the combinational circuit thatenumerates all possible solutions. Experimental results are

presented in Section VI. Finally, Section VII concludes thispaper.

II. PRELIMINARIES

In the classical spare allocation problem, we consider a bit-oriented memory array with spare (repair) rows and spare(repair) columns. Any fault row (column) can be replaced witha spare row (column). A repair solution is a set of at most rowaddresses and at most column addresses that cover all faults(all faults are on the addresses). If a repair solution exists for amemory array, thememory array is repairable. A repair strategyis a string of the alphabet {“ ”,“ ”} such that occurs timesand occurs times. Thus there are repair strategies.For example, if and , the set of all possible repairstrategies is

Given a sequence of fault addresses, a repair strategy can gen-erate a repair solution candidate and the solution space consistsof solution candidates. For example, given a sequence offault addresses

a repair strategy RRCC generates a solution

The problem to find a repair solution is known as the constraintbipartite vertex cover (CBVC) problem, which is proven asNP-complete in [11].Definition 1: If a row (column) in a memory array has more

than faults, the row (column) is amust-repair row (column)[11].This follows from the fact that if a row (column) has more

than faults and a repair row (column) is not used for the

CHUNG et al.: BUILT-IN REPAIR ANALYZER WITH OPTIMAL REPAIR RATE FOR WORD-ORIENTED MEMORIES 283

row (column), the memory array is not repairable. The repairrate and the normalized repair rate are defined as follows [12]:

Repair rate (1)

Normalized repair rate (2)

The 100% normalized repair rate is called the optimal repairrate.The following propositions have been introduced in several

places in the literature [6], [12], [19]. Here we state them withnew, shorter proofs using the pigeonhole principle.Lemma 1: If a memory array is repairable and the number of

faults on the memory array is greater than , there exists atleast a must-repair row or column [19].

Proof: Let and be the number of row and columnaddresses in a repair solution for thememory array, respectively.Also let and be sets that contain the faults covered bythe th repair row and column, respectively. Suppose that themust-repair conditions are not satisfied for all repair rows andcolumns. Then

for all

and

for all

Since the memory array is repairable, the total number of faultsis

This is a contradiction. Therefore, for at least a repair row orcolumn, the must repair condition is satisfied.Corollary 1: If the number of faults on a memory array is

greater than and the must-repair conditions for all repairrows and columns are not satisfied, the memory array is notrepairable [12].Corollary 2: If a memory array is repairable, the number of

faults captured in the (unbounded) fault-list is at most [6],[12].

Proof: Let and be the number of must-repair rows andcolumns in the memory array, respectively. All faults which areneither on the must-repair rows nor columns should be coveredby at most repair rows and at most repair columns.The number of the faults are at most by the sameargument as Lemma 1. The fault-list has at most faultsfor the must-repair rows and columns. The number of faultscaptured in the fault-list is at mostsince and .There are various types of word-oriented repairable memo-

ries, and they impose different constraints on the spare allo-cation problem. Since it is difficult to capture all the differenttypes of repairable memories into a generalized model and to

Fig. 3. Column circuitry of a word-oriented memory of type A.

Fig. 4. Column circuitry of a word-oriented memory of type B.

design an universal repair analyzer, we categorize them intothree types, which will be called type A, type B, and type C,respectively. Typically, a faulty row is replaced with a sparerow, but the way to replace a faulty column varies, based onwhich they are classified. Fig. 3 illustrates the column circuitryof a word-oriented memory of type A. In word-oriented mem-ories, the data in a word is usually not placed in adjacent loca-tions due to several issues such as the coupling effect, and thecolumns associated with the same bit position are clustered to-gether. In type A memories, there are spare column-groups ofcolumns each. A group of columns associated with a word is

replaced with a space-column group. In other words, the columnreplacement is performed on a column group basis. For ex-ample, if the first bit line in group 0 is faulty, and it is replacedwith the first spare column in group 0, then the first bit lines inthe other groups are also replaced with the associated first sparecolumns, respectively. The spare allocation problem in this typecan be reduced to the conventional spare allocation problem forbit-oriented memories [13]. Most repair analyzers in the litera-ture are developed for bit-oriented memories. In type B memo-ries, a faulty column is replaced with a spare column, but amonga group of columns associated with a word, only one column canbe replaced. Fig. 4 shows where the restriction comes from. Aword-oriented memory of type B has only spare columns un-like that of type A. Each spare column is selected when a pro-grammed column address is accessed. Up to faulty columnscan be replaced, but columns that constitute a word cannot bereplaced together. An efficient implementation of a word-ori-ented memory of this type is proposed in [14]. Fig. 5 illustratesa memory of type C, where any faulty column can be replacedwith an available spare column without any restriction. Variousimplementations for this type are proposed in [15]–[17].In order to generalize the constraint that arises in type B, we

define a new term. In a memory, if up to columns out of thoseassociated with a word can be replaced with spare columns, thememory is column-per-word replaceable. Thus, memories oftype B are 1 column-per-word replaceable.


Fig. 5. Column circuitry of a word-oriented memory of type C.

III. PROPOSED INFRASTRUCTURE

In this section, we propose an on-chip infrastructure forbit-oriented memories. This infrastructure will be extended forword-oriented memories later. Our repair analyzer requiresonly a single test and provides the optimal repair rate. Our in-frastructure does not depend on BIST engines, and we assumethat an arbitrary BIST engine tests a memory array and providesfault addresses whenever detected. Our infrastructure adoptsthe framework of the Kuo-Fuchs algorithm [11] and consistsof must-repair analysis and final analysis. The must-repairanalysis identifies must-repair rows and columns, and the finalanalysis searches a repair solution. The must-repair analysis isperformed concurrently with the test, while the final analysisis done after the test is completed. The must repair analyzer(MRA) is shown in Fig. 2. The MRA consists of a pair ofCAMs for fault addresses, called the fault-list, and a pair ofCAMs for a repair solution, called the solution record.In the fault-list, each CAM has one extra valid bit for each

word, and the valid bits are initialized to “0” in the beginning.Since the CAMs assert “1” at the valid bit position for write andmatch operation, only written entries can be matched. Duringthe test, if the BIST engine detects a fault, it sends the faultaddress to the MRA on the fly through BIST_R_DUTAddr andBIST_C_DUTAddr, and continues the test. The row (column)fault address is compared against row (column) CAM entries,and the number of matched entries is efficiently counted bya parallel counter [18]. If the number of the matched entriesequals in the row (column) CAM, the row (column) indi-cated by the fault address satisfies the must-repair condition andR_MustRepair (C_MustRepair) signal is asserted. If the faultaddress triggers neither the row nor column must-repair condi-tion, MRA writes the row and column address in the row andcolumn CAMs, respectively. Due to Corollary 2, we can limitthe size of the fault-list as 2 , and if the overflow of the fault-listoccurs, the memory array can be determined as unrepairable,and the test can be terminated early.If a particular row or column is identified as must-repair, the

row or column address must be part of the solution. Thus theMRA writes the row or column address in the solution record.The L registers are used as valid bits for the solution record andalso determine the next available CAM entry. Since a must-re-pair row and a must-repair column can be identified by a faultat the same time, the MRA should be able to write a pair of rowand column addresses simultaneously. Once a row or columnaddress is stored as part of solution by the must-repair condi-tion, then all solution candidates considered by the SOLVER

include the address, and faults on the address do not affect thefinal analysis any more. Therefore, such faults do not need to bestored, and we can collect all necessary information for the finalanalysis during a single test.Once the test is completed (thus the must-repair analysis is

done), BIST_Done signal is asserted and the final analysis isstarted. In the final analysis, the SOLVER module controls theMRA. The operation of the SOLVER and the MRA in the finalanalysis phase is illustrated in Fig. 6. The SOLVER will gen-erate repair strategies one by one and will check whether eachrepair strategy can fix all the faults captured in the fault-list. If“ ” and “ ” are mapped to “1” and “0”, respectively, then a re-pair strategy can be represented by a -bit word as shownTable I. The RepairStrategy module comprises a -bit reg-ister and stores the repair strategy being tested currently. Thefirst repair strategy is generated depending on the numbers ofmust-repair rows and columns, or UsedMustRepairRows andUsedMustRepairCols. For example, although and ,if one repair row and one repair column are used as must-re-pair, only the two repair strategies “ ” and “ ” should begenerated as if and . After a repair strategy istested, the state of the MRA should be reverted to that rightafter the must-repair analysis so the values in the L registers arecopied to the L_save registers before the final analysis begins.The SOLVER generates the first repair strategy and the MRAreads each fault address in the fault-list in order until there ex-ists no more fault address or the RESTART signal is arrived. TheMRA checks if each fault is covered by the current solution,stored in the solution record, and asserts R_Covered or C_Cov-ered. If both signals are low, the fault should be covered by anew repair row or column. The SOLVER determines whether arepair row or column is used for the uncovered fault, and assertsR_Insert or C_Insert. If R_Insert (C_Insert) is high, the faultrow (column) address is written in the row (column) CAMof thesolution record. If the CAM is full, the memory array cannot berepaired by the first repair strategy, and the SOLVER generatesthe next repair strategy and asserts the RESTART signal. Thenext repair strategy can be generated directly from the currentrepair strategy by a combinational circuit called K-subset enu-merator, which will be explained in detail in Section V. Whenthe RESTART signal becomes high, the MRA restores the ini-tial state, and the next repair strategy starts being evaluated. Inthis way, the SOLVER explores the solution space and can finda solution if one exists.In order to test the optimality of a solution, we can define

a cost function as in [11]. In our implementation, the cost isdefined as the number of used spare elements. The SOLVERhas a register to store the cost of the current repair strategy, orUsedRepairElements. The SOLVER also has registers to storethe repair strategy with minimum cost so far and the minimumcost, or RepairStrategyOpt and UsedRepairElOpt. The currentcost is compared against the minimum cost so far, which gen-erates the Better signal. If the Better signal goes down duringthe evaluation of the current repair strategy, the SOLVER im-mediately asserts the RESTART signal and moves on to the nextrepair strategy. If the Better signal stays at “1” until the end ofthe evaluation, the SOLVER saves the current repair strategyand its cost.


Fig. 6. Solver details and MRA operation in the final analysis phase: If the fault address being read is not covered by the current solution, depending on R_Insertor C_Insert, the row or column fault address is added to the current solution.

TABLE IBIT REPRESENTATIONS OF REPAIR STRATEGIES

Since the SOLVER continues to search for a better solutioneven after finding a solution, the MRA may not have the op-timal solution after the last repair strategy is evaluated. To re-duce area, we have stored the optimal repair strategy instead ofthe optimal solution. If the solution is directly stored, the sizeof the solution record should be doubled. Thus we need to re-cover the solution from the repair strategy, and the SOLVERgoes into recovery phase. In the recovery phase, the optimal re-pair strategy, stored in the RepairStrategyOpt, goes into the Re-pairStrategy register and the strategy is evaluated again and thefinal analysis ends up with the optimal solution.

IV. EXTENSION FOR WORD-ORIENTED MEMORIES

In this section, we will extend the proposed infrastructure forword-oriented memories, which is more common than bit-ori-ented memories in practice. Unlike the bit-oriented memorycase, from the BIST engine, our infrastructure takes as inputa triplet ( , , S), where is the row (column)address, and is the failure syndrome, which is the exclusiveOR of the test response and the expected output of the wordat . For word-oriented memories of type A, we candiscard the failure syndrome and can input only the row andcolumn addresses to the proposed infrastructure. Then withoutany modification, it will perform repair analysis for type Aword-oriented memories.

A. Dealing With Type B

For a word-oriented memory of type B, our repair analyzeris modified as follows. Let be the word size of the deviceunder test (DUT). We will map the word-oriented memory to

a bit-oriented memory. Since every bit should be addressablein the bit-oriented memory, we expand the width of the columnaddress by to distinguish each column within a word.We call the extended address the virtual column address. In thiscase, a triplet can generate up to virtual column address forthe bit-oriented memory. However, in the case that the numberof “1”s in is greater than 1, it is obvious that the row beingtested is a must-repair row since the DUT is 1 column-per-wordreplaceable. Thus, if this case is handled separately, one tripletwill generate only one virtual column address. The pair of theincoming row address and the virtual column address is fed intothe proposed infrastructure, which will work with the word-ori-ented memory of type B. Let us extend this scheme for acolumn-per-word replaceable memory where . In thismemory, a triplet can generate virtual column addresses. Itis common to perform memory BIST at-speed for higher testquality, whichmeans that our infrastructure may receive a tripletat every cycle so the virtual column addresses may need tobe handled in one cycle. They can be placed in pipeline, butthis does not prevent the BIST from being stopped. Thus, inorder to enable at-speed BIST together with BISR, it is nec-essary to handle this memory in a different way from that oftype B. Note that -bit-word-oriented memories of type C arecolumn-per-word replaceable. If we can deal with type C, anycolumn-per-word replaceable memory with can be alsohandled easily.

B. Dealing With Type C

We modify the MRA to support word-oriented memories oftype C. To begin with, we define several terms. In word-orientmemories, bits (columns) have the same address. However, inorder to repair such memories on a column basis, we need to dis-tinguish each column anyway, so we define the extended columnaddress as a pair of a column address and a word of bits, eachof which corresponds to one among the columns indicatedby the column address. The extended column address can indi-cate multiple columns within a word. Also, we call a pair of arow address and an extended column address the extended faultaddress. Multiple extended fault addresses indicating each fault


Fig. 7. Modified must repair analyzer for word-oriented memories of type C.

within a word can be combined into a single extended fault ad-dress. For example, and canbe combined into . The triplet coming from theBIST can also be represented by an extended fault address. Thuswe say that our RA engine receives an extended fault address ata cycle from the BIST engine.The modified MRA is illustrated in Fig. 7. In the MRA, the

columnCAM in the fault-list needs to store the extended columnaddresses, and each entry comes to have additional bits. Theeach bit has its own match signal, and thus each entry hasmatch signals including the original match signal. The new

match signals except the original one for the th entry are de-noted by , respectively. These signals are fedinto the logic for generating the signal. Thislogic comprises parallel counters (PCs) and the final adder tocount the number of faulty cells in a row across the word bound-aries. The number of the faulty cells is added to the number of1’s in the incoming fault syndrome, and if it is greater than ,then the must repair condition is satisfied and the R_MustRe-pair signal is asserted. The new match signals are also used togenerate , each ofwhich is asserted when each column within a word satisfiesthe must-repair condition. Columns in a word are handled inparallel using the PCs. Since our architecture is designed toshare storage elements as much as possible, this parallel oper-ation is implemented using a little extra hardware. The solu-tion record in the MRA is extended accordingly and it will gen-erate . As in thebit-oriented case, each signal indicates whether each columnwithin a word is already included in the solution record (so willbe repaired by a spare column). If a fault, not covered by thecurrent partial solution, triggers the must-repair condition forthe row (column), the row (extended column) address shouldbe inserted to the solution record. If a fault is neither covered bythe current partial solution, nor triggers the must-repair condi-tion, then the extended fault address of the fault is added to thefault list. For up to faults in a word, this operation should beperformed in parallel. Some fault addresses can be inserted tothe solution record, and at the same time others can be added tothe fault-list. In this process, the fault addresses to be insertedto the solution record are combined. If more than one columnsatisfies the must-repair condition for the first time by the in-coming triplet, the extended column addresses to be added tothe solution record should be also combined. Thus one tripletadds at most one entry to the solution record and the fault-list.

Fig. 8. Part of control logic for writing extended column addresses to the fault-list and the solution record: the other two inputs of the lower AND gates are con-nected to R_Covered and one of , respec-tively.

The logic to implement this function is illustrated in Fig. 8. Sup-pose this figure shows the first empty entries in the fault-list andthe solution record, which are indicated by FLEnd and SolEnd,respectively. Thus the two signals in this figure are consideredto be asserted. Readers can identify that a control logic is in-stantiated times for the parallel operation. The SOLVER alsotries to write an extended column address to the solution recordin the final analysis phase, when the signal C_Insert is used.To demonstrate the operation of the modified MRA, we will

consider an example. Suppose that we are given a DUT with3 rows and each row has 2 words of 2 bits each. The DUT isequipped with 2 spare rows and 2 spare columns. Fig. 9 depictsthe faults on the DUT. At cycle 0, our RA engine takes the ex-tended fault address from the BIST engine andthis is added to the fault-list. At cycle 1, is re-ceived, and R_MustRepair is asserted. Thus the row addressis inserted to the solution record. At cycle 2 and 3, each faultaddress is added to the fault-list without triggering the must-re-pair condition. At cycle 4, the left column in triggers thecolumn must-repair condition, but the right column does not.Thus, the extended column address is inserted to thesolution record and the extended fault address isinserted to the fault-list. Finally is added to thefault list. The fault-list after the test is shown in Table II. Ac-tually, the row 2 and the right column in are a must-repairrow and a must-repair column, respectively, but these are not


Fig. 9. Faults on a DUT.

detected by the MRA. Note that the main goal of the MRA isnot to detect all must-repair conditions but to capture all nec-essary information with entries. As in the bit-oriented case,once the must-repair analysis is completed, the final analysis isstarted. The final analysis is an iterative process for each entryin the fault-list and is summarized in Algorithm 1. The overallprocedure is similar to the final analysis in the bit-oriented case.The reason why the final analysis can be performed with minormodifications is that given multiple faults within a word, thereare still only two possible (meaningful) ways to fix them; a re-pair row is used, or all faults are fixed by a repair column. It isobvious that the other ways lead to suboptimal results. We willcontinue to use the example, for the final analysis.

Algorithm 1 Final Analysis

1: Read an extended fault address ( , ( ,S)) from the faultlist

2: Let be the bitwise OR of and. Then

represents the faults in not covered by the current partialsolution.

3: Let be the number of ‘1’ in4: if then5: Go to line 16: else7: if a repair row should be used according to the current

repair strategy then8: if is 1 then9: Restore the state of the MRA right after the

must-repair analysis is done10: Obtain the next repair strategy, initialize the pointer

of the fault list and go to line 111: else12:13: end if14: end if15: if a repair column should be used according to the current

repair strategy then16: Let be the number of remaining repair

columns17: if then18: Perform the same procedure as line 9–1019: else20:21: end if22: end if23: end if

TABLE IIFAULT-LIST AFTER THE TEST OF THE DUT IS COMPLETED

TABLE IIICHANGE OF THE SOLUTION RECORD WHEN “ ” IS USED

TABLE IVCHANGE OF THE SOLUTION RECORD WHEN “ ” IS USED

Table III shows the change of the solution record in the ex-ample. Initially, the solution record contains andthat are detected as must-repair during the test. Except these,only two spare elements are remaining. Suppose that the currentrepair strategy is “ ”. At cycle 0 and 1, the first and secondentries are read from the fault-list in Table II. These are alreadycovered by the current partial solution and nothing happens. Atcycle 2, the third entry is loaded and according to the currentrepair strategy, a repair row is used for the fault. The row 1 isadded to the solution record. At cycle 3, is readand a spare column is used to fix this fault. At cycle 4, sincethere is no remaining spare element for the last entry, the cur-rent strategy cannot fix the DUT.Now the current repair strategy becomes “ ”. Table IV

shows the change of the solution record in this case. The internalstate of the MRA is restored to that before the final analysis be-gins, and the solution record consists of and again.The cycle 0 and 1 are the same as before. At cycle 2, a repaircolumn is used at this time, which adds to the solutionrecord. At cycle 3, the fault is fixed by a repair row. At cycle 4,since the last entry is already covered by the repair row, nothinghappens. Since every fault in the fault-list is covered by the cur-rent partial solution, we obtain a solution.

V. K-SUBSET ENUMERATOR

A repair strategy is represented a -bit word. Since thewords contain “1”s and “0”s, enumerating all repair strate-gies is equivalent to enumerating -bit words that con-tains “1”s. This problem is also equivalent to enumerating-subsets, which are subsets of size , given a set of size ,where and . Usually the enumeration canbe done by using the depth-first search, which can be imple-mented by using a stack. A software implementation using re-cursion is shown in [20]. Note that recursive algorithms use thecall stack. A hardware implementation using a stack and coun-ters is shown in [6] which requires times 4 storage ele-


ments (RAM or flip-flops) and a FSM, and the number of cy-cles to derive the next repair strategy varies. In [21], the authorsuse an linear feedback shift register (LFSR) and show the feed-back polynomials and initial seed values to enumerate all repairstrategies for up to 2 repair rows and 2 repair columns. How-ever, this approach is not general for arbitrary and values.A maximal LFSR may be used with a parallel counter to countthe number of “1”s. If the number of “1”s equals , the LFSRvalue is a repair strategy. However, the numbers of available re-pair rows and columns are different after the must-repair phase,and during the enumeration of the LFSR, it is difficult to detectevery repair strategy for the available repair rows and columnsonly once using a simple circuit. We therefore propose an ef-ficient algorithm and a combinational circuit implementation.It is important to note that the problem of enumerating all re-pair strategies also corresponds to generating constant weightvectors, which are often used as test patterns [22]. A methodto generate constant weight vectors is presented in [22] whosescheme, however, requires an external tester to input a partic-ular sequence.Enum_K_Subset, summarized in Algorithm 2, consists of two

distinct operations. If the LSB is “0” (line 2), Enum_K_Subsetperforms a move operation (line 3–6), which finds the trailing“1” and moves it towards the LSB by one bit. For example, ifis 001100, the next -subset representation becomes 001010.

If the LSB is “1”, Enum_K_Subset performs a borrow opera-tion (line 8–12), which finds the trailing “1” excepting one ormore consecutive “1”s ending in the LSB and moves it towardsthe LSB by one bit. We call such a trailing “1” a pivot. Afterthe pivot, it writes the same number of “1”s as the consecutive“1”s and writes “0”s until the LSB. This is equivalent to flip-ping the group of bits in the position lower than the pivot. Forexample, if is 00100011, the next -subset representation be-comes 00011100. It is interesting to note that both the operationsin Enum_K_Subset preserve the number of “1”s in .

Algorithm 2 Enum_K_Subset

Require:

1: while is not a string of one or more consecutive 0sfollowed by one or more consecutive 1s do

2: if then3: // move operation4: Let the bit index of the trailing ‘1’5:6:7: else8: // borrow operation9: Let the bit index of the first ‘1’ followed by one or

more consecutive 0s and one or more consecutive 1sending in LSB

10:11:12:13: end if14: end while

If Enum_K_Subset takes a -bit string and we need to enu-merate all -subsets of a set of size , then the initial stringshould be consecutive 0s and consecutive 1s followedby consecutive 0s. For example, given , , and

, the initial string is 001000 and Enum_K_Subset enu-merates the sequence . Notethat can be greater than . Thus, in the proposed BIRA,can be greater than . This is a crucial feature because theavailable repair elements after the must-repair analysis can befewer than even if we set .

A. Combinational Circuit Implementation

In this subsection, we propose a combinational circuit imple-mentation of Enum_K_Subset that consists of two stages. In thefirst stage, the circuit generates borrow signals defined as fol-lows:

if and an index such thatand

otherwise.

The borrow signals indicate the position of the pivot. In thesecond stage, the next -subset representation, , is generatedusing the borrow signals. To derive the borrow signals from, we define two types of intermediate signals and . Thesignal is high if is a string of consecutive “1”s. Thesignal is high if is a string of one or more consecutive“0”s followed by one or more consecutive “1”s. Then, we canwrite

Using , the borrow signal can be written as

Owing to the dependency of on , the borrow signals maybe difficult to compute in a single cycle. We thus generalizethese signals to break the dependency. This allows us to usethe parallel prefix algorithm, which is used for high-speed treeadders such as the Kogge-Stone adder, Brent-Kung adder andso on. asserts if it is a string of consecutive “0”s,if it is a string of consecutive “1”s, and if it is a string of oneor more consecutive “0”s followed by one or more consecutive“1”s. So we write

If

If for an integer such that


Fig. 10. 8-bit -subset enumerator with Kogge-Stone style configuration.

Note that and . Fig. 10 shows a groupLHT cell to generate and signals. Similar to carrysignals of adders, there are various configurations to generatethe final , , and by using the group LHT cells,which provides a trade-off between speed, area and complexity.Such configurations for adders are shown in [23] and can be di-rectly converted into ones for -subset enumerators. Since theSOLVER takes some time to consume a repair strategy, a slowconfiguration may not be critical in the overall performance.However, since the SOLVER can request the next repair strategyin less than cycles in some cases, we can consider a fastconfiguration, provided that area is not a crucial factor. Fig. 10also shows the Kogge-Stone style configuration that providesthe best speed, and if the smallest area is desired, the ripple-carrystyle configuration can be used. For a -bit -subset enumerator,

indicates that is the last one (i.e., the end of the enu-meration). Once , and signals are obtained from aconfiguration, the next -subset representation, , can be de-rived from the following formulas. For all

For all such that

ifififif

ifotherwise.

For or , can be derived similarly. The firstline of implements the move operation.For the borrow operation, the previous equation can be rep-

resented again in Table V when . This shows the borrowoperation can be implemented by combining two distinct oper-ations, the bypass operation for the upper triangle and the shiftoperation for the lower triangle. Thus we call this the partialbypass-and-shift. To select one of the two operations, we canuse . We may need to use a barrel shifter for the lower

TABLE VBORROW OPERATION CAN BE IMPLEMENTED BY COMBINING A BYPASS

OPERATION AND A SHIFT OPERATION

triangle. However, since the conditions for are mutually ex-clusive, we can directly implement the formula for by usingthe AOI gates in an implementation of small size such as 8-bit.Besides, the bypass operation is dominant in the high order bitsand the area overhead is small.

VI. EXPERIMENTAL RESULTS

We implemented the proposed infrastructure in 130-nm tech-nology for a memory array with four repair rows and four re-pair columns, and the operating frequency is 400 MHz. Wecustom-designed CAMs and synthesized the other logics usingSynopsys Design Compiler except an 8-bit -subset enumer-ator.Major evaluation factors of BIRA performance include anal-

ysis time, area, and repair rate. Table VI compares our methodto CRESTA and the intelligentSolveFirst proposed in [6]. Sinceall these methods provide the optimal repair rate, the repair ratesare not presented. The number of test and the number of CAMentries dominate the analysis time and the area, respectively.Thus, the test time in the worst case and the area can be esti-mated using Table VI. As mentioned earlier, CRESTA performsrepair analysis in parallel with the test and evaluate all solutioncandidates simultaneously using the multiple sub-analyzers, re-quiring only one test irrespective of the number of repair ele-ments. The test and repair analysis finish at the same time, andone of the sub-analyzers contains the optimal solution. Since noextra cycle after the test is required, the analysis time equals thetest time. In the case that or as in the third row inTable VI, the number of possible solution candidates increaseslinearly in the number of repair elements, and the spare allo-cation problem becomes relatively easy. However, it is knownthat the repair rate of and is worse than that of

and [4]. The methods proposed in [6] reducethe number of required CAM entries at the cost of the analysistime. TheBasicSolve in [6] performs the exhaustive search andrequires tests (or, restarts) if the optimal solution is nec-essary in terms of the number of repair elements used. If thenumber of repair elements used does not matter, it may find asolution with a few tests [6] but the worst case bound is still

. The required number of tests by the intelligentSolve andthe intelligentSolverFirst in the worst case seems to be muchless in simulation, but it is not proven theoretically. In our pro-posed method, the restart of the test does not happen in any case.This comes at the cost of a few extra cycles after the single testfor the final analysis.In the final analysis phase, the read operation of the fault-

list takes less than 1.7 ns as shown in Fig. 11, and the subse-quent logic uses 0.8 ns. Thus the SOLVER can evaluate a repair


TABLE VINUMBERS OF TEST SESSIONS IN THE WORST CASE AND THE NUMBERS OF CAM ENTRIES

Fig. 11. Read operation of the row CAM in the fault-list.

strategy within cycles, which includes one extra cycleto move on the next repair strategy. The SOLVER should eval-uate repair strategies in the worst case and one extra repairstrategy for recovering the optimal solution, so the final analysistakes less than cycles. This amount oftime is negligible compared to a single test time, which is typ-ically over a few hundred million cycles [9], [10]. The storagerequirement of the proposed method remains the same as [6].Even in the extension for word-oriented memories, the resultsin Table VI do not change although each entry in the CAMsfor the column address requires additional bits. Since our in-frastructure requires entries for each CAM in the fault-listand entries for the solution record, if the number of re-pair rows and columns are evenly divided, the total number ofCAM entries grows quadratically with respect to the numberof repair elements, even if the redundancy allocation problemis NP-complete. Actually this is no surprise since the problemkernel of the redundancy allocation is known to be small,[24]. The extra cycles clearly grow exponentially. However, wehave tried to minimize the constant that is multiplied by the ex-ponential term in the complexity representation of the test time.As a result, the extra cycles become insignificant for the smallnumber of repair elements used in practice.Our implementation of the proposed method uses 94 flip-

flops and the number of flip-flops grows at most linearly withrespect to the number of repair elements. Also, it uses about800 combinational cells including an 8-bit -subset enumeratorwith Kogge-Stone style configuration, as shown in Table VII.

TABLE VIICOMBINATIONAL LOGIC SUMMARY

The -subset enumerator has much slack in timing, so if it is re-placed by a slower configuration, we can implement it using asmaller number of cells. As mentioned earlier, the number of cy-cles to generate repair strategies varies in the stack-based imple-mentation unlike the -subset enumerator, which could lengthenthe final analysis time. However, this may be marginal com-pared to the long test time. Rather, the -subset enumerator isbeneficial for its simplicity as well as smaller area. Due to thevarying generation time, the stack-based implementation com-plicates control logics, while our proposed enumerator does notrequire them and it is easy to verify once implemented.

VII. CONCLUSION

In this paper, we have proposed an on-chip infrastructure forrepair analysis with the optimal repair rate. Our infrastructurerequires a single test and a few extra cycles, which is about 600cycles in a memory array with four repair rows and four re-pair columns. Most built-in repair analyzers are developed forbit-oriented memories, whereas our repair analyzer also aimsat various types of word-oriented memories. To achieve this,we have extensively studied existing word-oriented repairablememories and have classified them into three types. For eachtype, we have showed how the bit-oriented version can be ex-tended. As part of our repair analyzer, we have also developeda novel combinatorial circuit for enumerating constant-weightvectors.

ACKNOWLEDGMENT

The authors would like to thank E. Byun and C.-J. Woo atSamsung Electronics for helpful discussions.

REFERENCES[1] R. Rajsuman, “Design and test of large embedded memories: An

overview,” IEEE Design Test Comput., vol. 18, no. 3, pp. 16–23, May2001.

[2] S. Hamdioui, G. Gaydadjiev, and A. van de Goor, “The state-of-artand future trends in testing embedded memories,” in Proc. Records Int.Workshop Memory Technol., Design, Test., 2004, pp. 54–59.

[3] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair:Infrastructure IP for SOC yield,” IEEE Design Test Comput., vol. 20,no. 3, pp. 58–66, May/Jun. 2003.


[4] T. Kawagoe, J. Ohtani, M. Niiro, and T. Ooishi, “A built-in self-repairanalyzer (cresta) for embedded drams,” in Proc. Int. Test Conf., 2000,pp. 567–574.

[5] S. Shoukourian, V. A. Vardanian, and Y. Zorian, “A methodology fordesign and evaluation of redundancy allocation algorithms,” in Proc.VLSI Test Symp., 2004, pp. 249–255.

[6] P. Oehler, S. Hellebrand, and H.-H. Wunderlich, “An integratedbuilt-in test and repair approach for memories with 2D redundancy,”in Proc. Eur. Test Symp., 2007, pp. 91–96.

[7] P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing test andrepair times for 2D integrated memory built-in test and repair,” inProc.Design Diag. Electron. Circuits Syst., 2007, pp. 1–6.

[8] P. Oehler, A. Bosio, G. D. Natale, and S. Hellebrand, “A modularmemory BIST for optimized memory repair,” in Proc. Int. On-LineTest. Symp., 2008, pp. 171–172.

[9] W. Jeong, I. Kang, K. Jin, and S. Kang, “A fast built-in redundancyanalysis for memories with optimal repair rate using a line-based searchtree,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no.12, pp. 1665–1678, Dec. 2009.

[10] W. Jeong, J. Lee, T. Han, K. Lee, and S. Kang, “An advanced BIRA formemories with an optimal repair rate and fast analysis speed by using abranch analyzer,” IEEE Trans. Comput.-Aided Design Integr. CircuitsSyst., vol. 29, no. 12, pp. 2014–2026, Dec. 2010.

[11] S.-Y. Kuo and W. Fuchs, “Efficient spare allocation for reconfigurablearrays,” IEEE Design Test Comput., vol. 4, no. 1, pp. 24–31, Feb. 1987.

[12] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancyanalysis for memory yield improvement,” IEEE Trans. Reliab., vol. 52,no. 4, pp. 386–399, Dec. 2003.

[13] A. Sehgal, A. Dubey, E. Marinissen, C. Wouters, H. Vranken, and K.Chakrabarty, “Redundancy modelling and array yield analysis for re-pairable embedded memories,” IEE Proc. Comput. Digit. Techn., vol.152, no. 1, pp. 97–106, 2005.

[14] A. Ferris and G. Work, “Memory circuit capable of replacing a faultycolumn with a spare column,” U.S. Patent 5 163 023, Nov. 10, 1992.

[15] B. Fitzgerald and E. Thoma, “Circuit implementation of fusible redun-dant addresses on RAMs for productivity enhancement,” IBM J. Res.Develop., vol. 24, no. 3, pp. 291–298, 1980.

[16] N. MacDonald, “Memory array of integrated circuits capable of re-placing faulty cells with a spare,” U.S. Patent 5 406 565, Apr. 11, 1995.

[17] C. Wu and C. Wong, “Dynamic spare column replacement memorysystem,” U.S. Patent 5 781 717, July 14, 1998.

[18] E. E. Swartzlander, “Parallel counters,” IEEE Trans. Comput., vol. 22,no. 11, pp. 1021–1024, Nov. 1973.

[19] D. K. Bhavsar, “An algorithm for row-column self-repair of rams andits implementation in the alpha 21264,” in Proc. Int. Test Conf., 1999,pp. 311–318.

[20] J. Loughry, J. I. Hemert, and L. Schoofs, “Efficiently enu-merating the subsets of a set,” 2000. [Online]. Available: ap-plied-math.org/subset.pdf

[21] X. Du and W.-T. Cheng, “At-speed built-in self-repair analyzer forembedded word-oriented memories,” in Proc. Int. Conf. VLSI Design,2004, pp. 895–900.

[22] D. Tang and L. Woo, “Exhaustive test pattern generation with con-stant weight vectors,” IEEE Trans. Comput., vol. C-32, no. 12, pp.1145–1150, Dec. 1983.

[23] N. H.Weste and D. Harris, CMOS VLSI Design: A Circuits and SystemsPerspective. Boston, MA: Addison-Wesley, 2005.

[24] G. Bai and H. Fernau, “Constraint bipartite vertex cover: Simpler exactalgorithms and implementations,” in Proc. Int. Workshop Frontiers inAlgorithmics, 2008, pp. 67–78.

Jaeyong Chung (S’09–M’11) received the B.S. de-gree in electrical engineering fromYonsei University,Seoul, Korea, in 2006, and the M.S. and Ph.D. de-grees in electrical and computer engineering from theDepartment of Electrical and Computer Engineering,University of Texas, Austin, in 2008 and 2011, re-spectively.He joined Synopsys, Inc., Mountain View, CA, in

2011. He is currently a member of the Design Com-piler Team, Synopsys, Inc., where he focuses on re-search and development in logic synthesis and opti-

mization topics. His current research interests include combinational optimiza-tion, timing analysis, yield optimization, and very large scale integration testing.Dr. Chung was the recipient of Best Paper Award nominations at the Interna-

tional Conference on Computer-Aided Design in 2009 and the Asia and SouthPacific Design Automation Conference in 2011. One of his co-authored paperswas selected in the Asian Test Symposium 20th Anniversary Compendium.

Joonsung Park (S’07–M’09) received the B.Eng.degree in electrical engineering from the KoreaUniversity, Seoul, Korea, in 2003, the M.Sci. degreein electrical engineering from the University ofMichigan, Ann Arbor, in 2005, and the Ph.D. degreein electrical and computer engineering from theUniversity of Texas at Austin, Austin, in 2009.He is currently an Electrical Design Engineer with

Texas Instruments, Inc., Dallas. His research interestincludes VLSI and mixed-signal circuit design andtest methodology.

Jacob A. Abraham (S’71–M’74–SM’84–F’85)received the Ph.D. degree in electrical engineeringand computer science from Stanford University,Stanford, CA, in 1974.He is currently a Professor with the Department

of Electrical and Computer Engineering, Universityof Texas, Austin. He is also the Director of theComputer Engineering Research Center and holdsthe Cockrell Family Regents Chair in Engineering.From 1975 to 1988, he was on the faculty of theUniversity of Illinois at Urbana-Champaign, Urbana.

He has published extensively and is included in the Thomson Reuters List ofHighly Cited Researchers. He has supervised more than 80 Ph.D. dissertationsand is particularly proud of the accomplishments of his students, many ofwhom occupy senior positions with academia and industry. His current researchinterests include VLSI design and test, formal verification, and fault-tolerantcomputing.Dr. Abraham is a fellow of the ACM and was the recipient of the 2005 IEEE

Emanuel R. Piore Award.

A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories

Documents

Transcript of A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories