Solid-State Electronics 53 (2009) 773–778

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Solid-State Electronics

journal homepage: www.elsevier .com/locate /sse

A 65 nm test structure for SRAM device variability and NBTI statistics

Thomas Fischer a,*, Ettore Amirante b, Peter Huber b, Karl Hofmann b, Martin Ostermayr b,Doris Schmitt-Landsiedel a

a Technische Universität München, Theresienstr. 90, 80290 München, Germanyb Infineon Technologies AG, Am Campeon 1, 85579 Neubiberg, Germany

a r t i c l e i n f o

Article history:Received 12 November 2008Accepted 12 February 2009Available online 25 April 2009

The review of this paper was arranged byProf. P. Ashburn

Keywords:VariabilitySRAMNBTITest structure

0038-1101/$ - see front matter � 2009 Elsevier Ltd. Adoi:10.1016/j.sse.2009.02.012

* Corresponding author. Tel.: +49 89 289 22916.E-mail address: thomas.fischer@mytum.de (T. Fisc

a b s t r a c t

We present the results of a test structure that allows to measure the variation of SRAM p-MOS and n-MOStransistors in a dense environment and to apply Negative Bias Temperature Instability (NBTI) stress onthe p-MOS transistors. The threshold voltage ðVthÞ and drain current ðIdÞ distributions of p-MOS SRAMtransistors pre- and post-NBTI stress are measured and analyzed. The probability density functions(PDF) of both transistor parameters Vth and Id follow a Gaussian distribution pre- and post-NBTI stress,but the difference in the transistor parameters of an individual device is not Gaussian distributed. Thestandard deviation in the difference of Vth is about 50% of the mean for the small SRAM p-MOS transistor.The impact of the additional variation induced by NBTI stress is shown for the static noise margin of a 6TSRAM cell.

� 2009 Elsevier Ltd. All rights reserved.

1. Introduction

Following Moore’s law by pushing CMOS to smaller and smallerdevice sizes is on the one hand a challenge because fabricating afunctional device at a new technology node gets more and moredifficult. On the other hand increasing device variability makes itharder to fabricate a large number of devices on a chip that workwithin specification limits. Global, systematic variations, that af-fect all devices in the same way, can be reduced by process learn-ing, but local, statistic variations cannot be avoided. The two mainsources of local variations are the stochastic dopant distribution inthe transistor and the line edge roughness (LER). Transistor thresh-old voltage variation due to stochastic dopant variation and LER in-creases with smaller device areas, therefore local variations getlarger with shrinking devices.

SRAM cells suffer most from local variability. To keep the area ofSRAM arrays in SoC small the memory cells must be as small aspossible in a technology. But these small transistors show alsothe largest stochastic variation. Modern systems on a chip (SoC)have large SRAM arrays and therefore a huge stochastic spread ofthe devices. It is possible to measure critical SRAM performanceswith large array test structures [1].

Another factor of variability is the degradation of transistorparameters over time that also lowers the operating margin ofSRAM cells [2,3]. The Negative Bias Temperature Instability (NBTI)

ll rights reserved.

her).

is a long known degradation mechanism [4]. During NBTI stress(high gate field and elevated temperature) Si–H bonds at theSi–SiO2 interface break and act as traps. This increases the thresh-old voltage of the devices and affects the performance and yield ofsemiconductor systems. NBTI has become a major concern insub-100 nm technologies [5] due to the larger gate oxide fields intransistors with thin gate oxides and the introduction of nitridedoxides [6]. The knowledge of variability and reliability mechanismslike NBTI is essential to design functional SRAM cells and arrays insub-100 nm technologies.

We have developed a test structure to measure SRAM devicevariability for up to 1 MBit SRAM n-FET and p-FET transistors in65 nm CMOS technologies that is also able to measure the variabil-ity induced by NBTI device degradation [7].

At first we will show the design of the test structure. Then wewill present measurements of SRAM device variability measure-ments, followed by a measurement of NBTI variability. The paperends with a summary.

2. Test structure

The NBTI variation test structure has a 1 MBit array of SRAM n-type and p-type devices. To measure the variation of the un-stressed and stressed SRAM devices it is necessary to place the de-vices as densely packed as they are in the normal SRAM array. It isalso important that the layout around the measured device is asclose as possible to the layout of the original SRAM array to

774 T. Fischer et al. / Solid-State Electronics 53 (2009) 773–778

incorporate all the effects of the dense layout and the appliedground rule waivers not present in insulated single transistors.Therefore a standard SRAM cell layout was modified to gain accessto a single SRAM transistor in the standard array topology withoutchanging the cell layout considerably.

Fig. 1 shows the circuit and the layout of a 65 nm technologySRAM core cell. Fig. 2 shows the modified layout. The upper polystripes were connected to contact the gate of the p-type load tran-

Fig. 1. Layout and schematic of

Fig. 2. Layout and schematic of t

Fig. 3. Schematic of the proposed 1 MBit

sistor PL1 and n-type pass gate PG2 to the word-lines (WL) of theSRAM array. The metal layer one was changed to connect the drainof the PG2 transistor to VSS and to short circuit the n-type drivetransistor PD2. On the other side of the SRAM cell the source ofthe PL1 transistor is now connected to the second bit-line (nowBL_P) via a metal 1 connection. The diffusion area of the PL2 tran-sistor was shortened and the local interconnet (LC) was removed todeactivate transistor PL2. All these changes affect the environment

a 65 nm 6T SRAM core cell.

he SRAM transistor test cell.

SRAM transistor NBTI test structure.

0−0.05

0

0.05

0.1

0.15

0.2

measurement time

ΔV th

measuementlinear fit

Fig. 4. DVth versus measurement time and the linear trend.

0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

0.0001

0.050.1

0.250.5

0.750.9

0.950.99

0.9990.9999

Id [a.u.]

Prob

abilit

y

t=0t=10000

Fig. 5. Distribution of the measured 65 nm SRAM p-MOS transistor drain currentspre- and post-NBTI stress ðtstress ¼ 10;000 sÞ.

−1 0 1 2 3 4 5 6 7x 10−6

0.0001

0.050.1

0.250.5

0.750.9

0.950.99

0.9990.9999

Δ Id [A]

Prob

abilit

y

Fig. 6. Distribution of the measured DId .

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

0.001

0.01

0.05 0.10 0.25

0.50

0.75 0.90 0.95

0.99

0.999

Vth [a.u.]

Prob

abilit

y

Normal Probability Plot

n−Fet Vth measurementGaussian Distribution

Fig. 7. Distribution of 128 k measured 65 nm SRAM n-MOS transistor thresholdvoltages.

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

0.001

0.01

0.05 0.10 0.25

0.50

0.75 0.90 0.95

0.99

0.999

Vth [a.u.]

Prob

abilit

y

Normal Probability Plot

tstress=0s

tstress=100s

tstress=10.000s

Fig. 8. Distribution of 128 k measured 65 nm SRAM p-MOS transistor thresholdvoltages before ðtstress ¼ 0 sÞ and after 100 s and 10,000 s NBTI stress.

T. Fischer et al. / Solid-State Electronics 53 (2009) 773–778 775

around the measured transistors PG2 and PL1 as little as possibleby retaining the same size and density as in a standard SRAM array.This offers the possibility to measure the p-type and n-type tran-sistors individually in the dense SRAM array by the use of thetwo bit-lines BL_N and BL_P and the word-line. The schematic inFig. 2 shows that the circuit has no SRAM functionality any morebut gives access to the SRAM p-type transistor PL1 and the SRAMn-type access transistor PG2.

The layout of the test structure cell can be placed in an arraylike a standard SRAM cell, i.e. it is mirrored horizontally and verti-cally and placed in a 1 MBit array including strap cells for substratecontact.

Shift registers were used to address columns and rows of thearray with only two external clock signals. The schematic of thetest structure array is shown in Fig. 3. The bit-lines (BL_N and

Fig. 9. Spatial map of p-FET threshold voltages.

−0.05 0 0.05 0.1 0.15

0.00010.001

0.01

0.1

0.5

0.9

0.99

0.9990.9999

Normal Probability Plot

Δ Vth [mV]

Prob

abilit

y

tstress = 1s

modelnormal cdftstress = 100s

modelnormal cdftstress = 10.000s

modelnormal cdf

Fig. 11. Distribution of 128 k measured 65 nm SRAM p-MOS DVth devices after 1 s,100 s and 10,000 s NBTI stress compared to the normal distribution and thepredicted distribution by Rauch [9].

0 5 10 15 20 25−0.2

0

0.2

0.4

0.6

0.8

1

1.2

Auto

corre

latio

n C

oeffi

cien

t

Lag

Bit−line directionWord−line direction

Fig. 10. Autocorrelation coefficients of p-FET threshold voltage in bit-line andword-line direction.

Table 1Statistical data of measured Vth distributions pre- and post-NBTI stressðtstress ¼ 10;000 sÞ.

r=l (%) l (mV) r (mV)

Vth;t¼0 7.79Vth;t¼100 7.84Vth;t¼10;000 7.85DVth 50.3 42.2 21.2

776 T. Fischer et al. / Solid-State Electronics 53 (2009) 773–778

BL_P) are accessible via a multiplexer that is controlled by thebit-line shift register. This register also controls the signalsPCH_N and PCH_P of the pre-charge transistors in such a waythat there is no voltage difference across the multiplexers atthe unselected bit-lines to avoid leakage current during Id;sat

and Vth;sat measurements. When the word-line clock is at ‘HIGH’the word-lines are forced to ground potential. This enables themeasurement of the off-state leakage current trough the accessdevices connected to a bit-line.

The shift register at the word-line side generates the signalWL_SEL. Together with the global signal P/N the XOR-gate setsthe word-line of the selected row to either HIGH for measurementson the n-type transistors or to LOW for measurement of the p-typetransistors. The inverter that drives the word-lines has a separatepower domain. This allows a gate voltage sweep of the measuredtransistor by sweeping either the VDD_WL node to obtain the in-put characteristic of the n-type transistor or sweeping the VSS_WLnode for the input characteristic of the p-type transistor.

By setting the P/N signal to LOW all unselected word-lines areset to VSS_WL and the stress transistor charges all drains of thep-MOS transistors to the supply voltage. Thus the complete arrayis under NBTI stress conditions with a high Vgs and Vds ¼ 0. At ele-vated supply voltage and temperature the aging of the memory ar-ray is accelerated.

3. Measurement results

The test structure was fabricated in a low power 65 nm CMOSprocess with a plasma nitrided gate oxide of 18 Å thickness.

In a first experiment the packaged dies were measured at a con-stant T = 25 �C pre-stress and then stressed at T = 125 �C andVgs ¼ 2:4 V for tstress ¼ 10;000 s. Due to the long measurement timeof the large number of measured devices a long recovery time oftrecover ¼ 500 s was chosen to measure only the settled NBTI drift.In Fig. 4 the results of the DVth ¼ Vth;tstress � Vth;t0 measurementsare plotted versus the measurement time. After such a long recov-ery time there is no decrease in DVth visible, that might be causedby further de-trapping of trapped interface charges [8].

The data from 1 million drain current Id measurements pre- andpost-NBTI stress show a Gaussian distribution for the p-MOS SRAMtransistor (Fig. 5). The distribution of the drain current differencepre- and post-NBTI stress DId however shows a non-normal distri-bution (Fig. 6).

The threshold voltage of the devices was extracted from theID � VGS curve using the constant current criteria. First the gatevoltages was swept with a resolution of 50 mV to find the approx-imate VGS around the constant current criteria. The exact thresholdvoltage was then determined by a second voltage sweep using 30samples around the constant current definition. This measurementalgorithm was implemented in a test script and run directly on a

0 5 10 15 20 25−0.2

0

0.2

0.4

0.6

0.8

1

1.2

Auto

corre

latio

n C

oeffi

cien

t

Lag

Bit−line directionWord−line direction

Fig. 12. Autocorrelation coefficients of p-FET threshold voltage differences DVth inbit-line and word-line direction.

100 101 102 103 10410−3

10−2

10−1

tstress [s]

ΔVth

[V]

mean ΔVth~t0.26

std ΔVth~t0.13

Fig. 14. The mean and the standard deviation measured DVth versus the stress time.

t=100s t=600s t=10,000s

0.8

0.82

0.84

0.86

0.88

0.90

SNM

/ SN

Mt0

@ 3

σRDF + μNBTIRDF + μNBTI + σNBTI

Fig. 15. SNM of a 6T SRAM cell with random dopant fluctuation (RDF) and NBTIinduced shift of lðVth;PLÞ and rðVth;PLÞ at the 3r worst case point for different stress

T. Fischer et al. / Solid-State Electronics 53 (2009) 773–778 777

Keithley 2602 parameter analyzer. With this setup it is possible toget reliable measurements of 128,000 devices in 3.5 h.

Fig. 7 shows the distribution of 128 k measured n-FET devices.The distribution shows a good fit to the Gaussian cdf. The sameobservation can be made for the threshold voltage distribution ofthe p-FET device before NBTI stress ðtstress ¼ 0 sÞ (Fig. 8). The spacialdistribution of the measured threshold voltages is presented inFig. 9. No spatial correlation is visible in this plot. The spatial auto-correlation (Fig. 10) along the bit-line and word-line of the devicearray shows only random behavior and no dependence in row orcolumn direction.

The complete array was then stressed at 2.4 V negative gate biasand T = 125 �C with different stress times. The threshold voltagedistribution post-NBTI stress was measured afterwards. Fig. 8shows that the threshold voltage distribution is still Gaussian afterNBTI stress, but the mean value increased significantly while thestandard deviation only increased slightly. Table 1 shows thatthe relative standard deviation r=l stays constant with respectto the stress time. The distribution of the threshold voltage differ-ence of a individual device DVth ¼ Vth;tstress � Vth;t0 however shows a

0.7 0.8 0.9 1 1.1 1.2 1.3−0.05

0

0.05

0.1

0.15

Vth,t0 [a.u.]

ΔV th

[V]

Fig. 13. Correlation of initial threshold voltages and NBTI induced threshold voltageshift ðtstress ¼ 10; 000 sÞ.

times.

clearly non-normal distribution as shown in Fig. 11 with a veryhigh variability. See Fig. 12 for autocorrelation coefficients of DVth.

The maximum threshold voltage shift out of these 128 k mea-surements is over 150 mV while there are also negative thresholdvoltage shifts. These can be explained by the Poisson statistics ofthe trapping and detrapping process of the interface states andare also reported by Agostinelli et al. [10] and Rauch [9]. Howeverthese large shifts in the threshold voltage are not correlated withthe initial threshold voltage as shown in Fig. 13. This fact is verybeneficial for circuit design, because for example large DVth donot necessarily add to large threshold voltages caused by randomdopant fluctuations. Due to the uncorrelation, the distribution afterNBTI stress Vth;tstress is a convolution of the initial distribution Vth;t0

and the distribution of the NBTI shift DVth;NBTI.

PðVth;tstress Þ ¼ PðDVth;NBTIÞ � PðVth;t0Þ ð1Þ

A model of the DVth distribution based on the Poisson statistic ofthe trapping and de-trapping of interface states and the Gaussiandistribution of the trap location was developed by Rauch [9].Fig. 11 shows our data compared to a normal PDF and the above

778 T. Fischer et al. / Solid-State Electronics 53 (2009) 773–778

mentioned model. The measurement data show a reasonable fit tothe model. The deviations might be explained by the large relaxa-tion time between the measurements.

The mean and the standard deviation of 128 k DVth measure-ments at different stress times is shown in Fig. 14. Both the meanand the standard deviation are clearly � tn with n ¼ 0:13 for thestandard deviation and n ¼ 0:26 for the mean of DVth. This corre-sponds well to figures reported in [6] for a technology with a sim-ilar tox and a nitrided gate oxide.

4. Impact on SRAM performances

[2,3] have shown that NBTI stress degrades the read stabilitybut improves the ability to write a cell. To study the impact ofthe measured transistor parameter shift and increased variabilityon the SRAM cell the static noise margin during read access [11]was simulated. Fig. 15 shows the worst case SNM for the 3r pointcalculated from l(SNM) and r(SNM) obtained form SPICE MonteCarlo simulations. The lðVthPLÞ and rðVthPLÞ for the p-MOS SRAMtransistors used for the pre- and post-NBTI simulations were takenfrom the measurement results shown above. Fig. 15 shows thedegradation of SNM decrease due to the mean shift of the thresh-old voltage of the PL transistor, but also shows the effect of theadditional variation that is caused by the statistics of the NBTI in-duced threshold voltage shift.

5. Conclusion

In this paper we presented a 1 MBit array test structure that al-lows the measurement of n-type and p-type SRAM transistors.NBTI stress was applied to the array and the device parametersthreshold voltage and drain current distributions of SRAM transis-tors were measured pre- and post-NBTI stress. The measurementsfor up to 1 million devices show a Gaussian distribution for the de-vice parameters pre- and post-NBTI stress. The NBTI induced Vth

shift however is not Gaussian distributed and shows a large vari-ability of up to 50% of its mean value, but is uncorrelated to the ini-tial Vth distribution. The impact on the stability of the SRAM celldue to the statistics of NBTI was shown.

Acknowledgements

This work has been supported by the German ministry ofeducation and research (BMBF) within the project ‘HONEY’ (Pro-ject ID 01M3184A). The content is the sole responsibility of theauthors.

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